2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
86 extern unsigned long dart_tablebase;
87 #endif /* CONFIG_U3_DART */
89 static unsigned long _SDR1;
90 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
92 struct hash_pte *htab_address;
93 unsigned long htab_size_bytes;
94 unsigned long htab_hash_mask;
95 int mmu_linear_psize = MMU_PAGE_4K;
96 int mmu_virtual_psize = MMU_PAGE_4K;
97 int mmu_vmalloc_psize = MMU_PAGE_4K;
98 #ifdef CONFIG_SPARSEMEM_VMEMMAP
99 int mmu_vmemmap_psize = MMU_PAGE_4K;
101 int mmu_io_psize = MMU_PAGE_4K;
102 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
103 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
104 u16 mmu_slb_size = 64;
105 #ifdef CONFIG_HUGETLB_PAGE
106 unsigned int HPAGE_SHIFT;
108 #ifdef CONFIG_PPC_64K_PAGES
109 int mmu_ci_restrictions;
111 #ifdef CONFIG_DEBUG_PAGEALLOC
112 static u8 *linear_map_hash_slots;
113 static unsigned long linear_map_hash_count;
114 static DEFINE_SPINLOCK(linear_map_hash_lock);
115 #endif /* CONFIG_DEBUG_PAGEALLOC */
117 /* There are definitions of page sizes arrays to be used when none
118 * is provided by the firmware.
121 /* Pre-POWER4 CPUs (4k pages only)
123 static struct mmu_psize_def mmu_psize_defaults_old[] = {
133 /* POWER4, GPUL, POWER5
135 * Support for 16Mb large pages
137 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
154 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
156 unsigned long rflags = pteflags & 0x1fa;
158 /* _PAGE_EXEC -> NOEXEC */
159 if ((pteflags & _PAGE_EXEC) == 0)
162 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
163 * need to add in 0x1 if it's a read-only user page
165 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
166 (pteflags & _PAGE_DIRTY)))
170 return rflags | HPTE_R_C;
173 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
174 unsigned long pstart, unsigned long prot,
175 int psize, int ssize)
177 unsigned long vaddr, paddr;
178 unsigned int step, shift;
181 shift = mmu_psize_defs[psize].shift;
184 prot = htab_convert_pte_flags(prot);
186 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
187 vstart, vend, pstart, prot, psize, ssize);
189 for (vaddr = vstart, paddr = pstart; vaddr < vend;
190 vaddr += step, paddr += step) {
191 unsigned long hash, hpteg;
192 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
193 unsigned long va = hpt_va(vaddr, vsid, ssize);
194 unsigned long tprot = prot;
196 /* Make kernel text executable */
197 if (in_kernel_text(vaddr))
200 hash = hpt_hash(va, shift, ssize);
201 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
203 BUG_ON(!ppc_md.hpte_insert);
204 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
205 HPTE_V_BOLTED, psize, ssize);
209 #ifdef CONFIG_DEBUG_PAGEALLOC
210 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
211 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
212 #endif /* CONFIG_DEBUG_PAGEALLOC */
214 return ret < 0 ? ret : 0;
217 #ifdef CONFIG_MEMORY_HOTPLUG
218 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
219 int psize, int ssize)
222 unsigned int step, shift;
224 shift = mmu_psize_defs[psize].shift;
227 if (!ppc_md.hpte_removebolted) {
228 printk(KERN_WARNING "Platform doesn't implement "
229 "hpte_removebolted\n");
233 for (vaddr = vstart; vaddr < vend; vaddr += step)
234 ppc_md.hpte_removebolted(vaddr, psize, ssize);
238 #endif /* CONFIG_MEMORY_HOTPLUG */
240 static int __init htab_dt_scan_seg_sizes(unsigned long node,
241 const char *uname, int depth,
244 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
246 unsigned long size = 0;
248 /* We are scanning "cpu" nodes only */
249 if (type == NULL || strcmp(type, "cpu") != 0)
252 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
256 for (; size >= 4; size -= 4, ++prop) {
258 DBG("1T segment support detected\n");
259 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
263 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
267 static void __init htab_init_seg_sizes(void)
269 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
272 static int __init htab_dt_scan_page_sizes(unsigned long node,
273 const char *uname, int depth,
276 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
278 unsigned long size = 0;
280 /* We are scanning "cpu" nodes only */
281 if (type == NULL || strcmp(type, "cpu") != 0)
284 prop = (u32 *)of_get_flat_dt_prop(node,
285 "ibm,segment-page-sizes", &size);
287 DBG("Page sizes from device-tree:\n");
289 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
291 unsigned int shift = prop[0];
292 unsigned int slbenc = prop[1];
293 unsigned int lpnum = prop[2];
294 unsigned int lpenc = 0;
295 struct mmu_psize_def *def;
298 size -= 3; prop += 3;
299 while(size > 0 && lpnum) {
300 if (prop[0] == shift)
302 prop += 2; size -= 2;
317 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
325 def = &mmu_psize_defs[idx];
330 def->avpnm = (1 << (shift - 23)) - 1;
333 /* We don't know for sure what's up with tlbiel, so
334 * for now we only set it for 4K and 64K pages
336 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
341 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
342 "tlbiel=%d, penc=%d\n",
343 idx, shift, def->sllp, def->avpnm, def->tlbiel,
351 #ifdef CONFIG_HUGETLB_PAGE
352 /* Scan for 16G memory blocks that have been set aside for huge pages
353 * and reserve those blocks for 16G huge pages.
355 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
356 const char *uname, int depth,
358 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
359 unsigned long *addr_prop;
360 u32 *page_count_prop;
361 unsigned int expected_pages;
362 long unsigned int phys_addr;
363 long unsigned int block_size;
365 /* We are scanning "memory" nodes only */
366 if (type == NULL || strcmp(type, "memory") != 0)
369 /* This property is the log base 2 of the number of virtual pages that
370 * will represent this memory block. */
371 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
372 if (page_count_prop == NULL)
374 expected_pages = (1 << page_count_prop[0]);
375 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
376 if (addr_prop == NULL)
378 phys_addr = addr_prop[0];
379 block_size = addr_prop[1];
380 if (block_size != (16 * GB))
382 printk(KERN_INFO "Huge page(16GB) memory: "
383 "addr = 0x%lX size = 0x%lX pages = %d\n",
384 phys_addr, block_size, expected_pages);
385 lmb_reserve(phys_addr, block_size * expected_pages);
386 add_gpage(phys_addr, block_size, expected_pages);
389 #endif /* CONFIG_HUGETLB_PAGE */
391 static void __init htab_init_page_sizes(void)
395 /* Default to 4K pages only */
396 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
397 sizeof(mmu_psize_defaults_old));
400 * Try to find the available page sizes in the device-tree
402 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
403 if (rc != 0) /* Found */
407 * Not in the device-tree, let's fallback on known size
408 * list for 16M capable GP & GR
410 if (cpu_has_feature(CPU_FTR_16M_PAGE))
411 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
412 sizeof(mmu_psize_defaults_gp));
414 #ifndef CONFIG_DEBUG_PAGEALLOC
416 * Pick a size for the linear mapping. Currently, we only support
417 * 16M, 1M and 4K which is the default
419 if (mmu_psize_defs[MMU_PAGE_16M].shift)
420 mmu_linear_psize = MMU_PAGE_16M;
421 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
422 mmu_linear_psize = MMU_PAGE_1M;
423 #endif /* CONFIG_DEBUG_PAGEALLOC */
425 #ifdef CONFIG_PPC_64K_PAGES
427 * Pick a size for the ordinary pages. Default is 4K, we support
428 * 64K for user mappings and vmalloc if supported by the processor.
429 * We only use 64k for ioremap if the processor
430 * (and firmware) support cache-inhibited large pages.
431 * If not, we use 4k and set mmu_ci_restrictions so that
432 * hash_page knows to switch processes that use cache-inhibited
433 * mappings to 4k pages.
435 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
436 mmu_virtual_psize = MMU_PAGE_64K;
437 mmu_vmalloc_psize = MMU_PAGE_64K;
438 if (mmu_linear_psize == MMU_PAGE_4K)
439 mmu_linear_psize = MMU_PAGE_64K;
440 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
442 * Don't use 64k pages for ioremap on pSeries, since
443 * that would stop us accessing the HEA ethernet.
445 if (!machine_is(pseries))
446 mmu_io_psize = MMU_PAGE_64K;
448 mmu_ci_restrictions = 1;
450 #endif /* CONFIG_PPC_64K_PAGES */
452 #ifdef CONFIG_SPARSEMEM_VMEMMAP
453 /* We try to use 16M pages for vmemmap if that is supported
454 * and we have at least 1G of RAM at boot
456 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
457 lmb_phys_mem_size() >= 0x40000000)
458 mmu_vmemmap_psize = MMU_PAGE_16M;
459 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
460 mmu_vmemmap_psize = MMU_PAGE_64K;
462 mmu_vmemmap_psize = MMU_PAGE_4K;
463 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
465 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
466 "virtual = %d, io = %d"
467 #ifdef CONFIG_SPARSEMEM_VMEMMAP
471 mmu_psize_defs[mmu_linear_psize].shift,
472 mmu_psize_defs[mmu_virtual_psize].shift,
473 mmu_psize_defs[mmu_io_psize].shift
474 #ifdef CONFIG_SPARSEMEM_VMEMMAP
475 ,mmu_psize_defs[mmu_vmemmap_psize].shift
479 #ifdef CONFIG_HUGETLB_PAGE
480 /* Reserve 16G huge page memory sections for huge pages */
481 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
483 /* Set default large page size. Currently, we pick 16M or 1M depending
484 * on what is available
486 if (mmu_psize_defs[MMU_PAGE_16M].shift)
487 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift;
488 /* With 4k/4level pagetables, we can't (for now) cope with a
489 * huge page size < PMD_SIZE */
490 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
491 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift;
492 #endif /* CONFIG_HUGETLB_PAGE */
495 static int __init htab_dt_scan_pftsize(unsigned long node,
496 const char *uname, int depth,
499 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
502 /* We are scanning "cpu" nodes only */
503 if (type == NULL || strcmp(type, "cpu") != 0)
506 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
508 /* pft_size[0] is the NUMA CEC cookie */
509 ppc64_pft_size = prop[1];
515 static unsigned long __init htab_get_table_size(void)
517 unsigned long mem_size, rnd_mem_size, pteg_count;
519 /* If hash size isn't already provided by the platform, we try to
520 * retrieve it from the device-tree. If it's not there neither, we
521 * calculate it now based on the total RAM size
523 if (ppc64_pft_size == 0)
524 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
526 return 1UL << ppc64_pft_size;
528 /* round mem_size up to next power of 2 */
529 mem_size = lmb_phys_mem_size();
530 rnd_mem_size = 1UL << __ilog2(mem_size);
531 if (rnd_mem_size < mem_size)
535 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
537 return pteg_count << 7;
540 #ifdef CONFIG_MEMORY_HOTPLUG
541 void create_section_mapping(unsigned long start, unsigned long end)
543 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
544 PAGE_KERNEL, mmu_linear_psize,
548 int remove_section_mapping(unsigned long start, unsigned long end)
550 return htab_remove_mapping(start, end, mmu_linear_psize,
553 #endif /* CONFIG_MEMORY_HOTPLUG */
555 static inline void make_bl(unsigned int *insn_addr, void *func)
557 unsigned long funcp = *((unsigned long *)func);
558 int offset = funcp - (unsigned long)insn_addr;
560 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
561 flush_icache_range((unsigned long)insn_addr, 4+
562 (unsigned long)insn_addr);
565 static void __init htab_finish_init(void)
567 extern unsigned int *htab_call_hpte_insert1;
568 extern unsigned int *htab_call_hpte_insert2;
569 extern unsigned int *htab_call_hpte_remove;
570 extern unsigned int *htab_call_hpte_updatepp;
572 #ifdef CONFIG_PPC_HAS_HASH_64K
573 extern unsigned int *ht64_call_hpte_insert1;
574 extern unsigned int *ht64_call_hpte_insert2;
575 extern unsigned int *ht64_call_hpte_remove;
576 extern unsigned int *ht64_call_hpte_updatepp;
578 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
579 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
580 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
581 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
582 #endif /* CONFIG_PPC_HAS_HASH_64K */
584 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
585 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
586 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
587 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
590 void __init htab_initialize(void)
593 unsigned long pteg_count;
595 unsigned long base = 0, size = 0, limit;
598 DBG(" -> htab_initialize()\n");
600 /* Initialize segment sizes */
601 htab_init_seg_sizes();
603 /* Initialize page sizes */
604 htab_init_page_sizes();
606 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
607 mmu_kernel_ssize = MMU_SEGSIZE_1T;
608 mmu_highuser_ssize = MMU_SEGSIZE_1T;
609 printk(KERN_INFO "Using 1TB segments\n");
613 * Calculate the required size of the htab. We want the number of
614 * PTEGs to equal one half the number of real pages.
616 htab_size_bytes = htab_get_table_size();
617 pteg_count = htab_size_bytes >> 7;
619 htab_hash_mask = pteg_count - 1;
621 if (firmware_has_feature(FW_FEATURE_LPAR)) {
622 /* Using a hypervisor which owns the htab */
626 /* Find storage for the HPT. Must be contiguous in
627 * the absolute address space. On cell we want it to be
628 * in the first 2 Gig so we can use it for IOMMU hacks.
630 if (machine_is(cell))
635 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
637 DBG("Hash table allocated at %lx, size: %lx\n", table,
640 htab_address = abs_to_virt(table);
642 /* htab absolute addr + encoded htabsize */
643 _SDR1 = table + __ilog2(pteg_count) - 11;
645 /* Initialize the HPT with no entries */
646 memset((void *)table, 0, htab_size_bytes);
649 mtspr(SPRN_SDR1, _SDR1);
654 #ifdef CONFIG_DEBUG_PAGEALLOC
655 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
656 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
658 memset(linear_map_hash_slots, 0, linear_map_hash_count);
659 #endif /* CONFIG_DEBUG_PAGEALLOC */
661 /* On U3 based machines, we need to reserve the DART area and
662 * _NOT_ map it to avoid cache paradoxes as it's remapped non
666 /* create bolted the linear mapping in the hash table */
667 for (i=0; i < lmb.memory.cnt; i++) {
668 base = (unsigned long)__va(lmb.memory.region[i].base);
669 size = lmb.memory.region[i].size;
671 DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
674 #ifdef CONFIG_U3_DART
675 /* Do not map the DART space. Fortunately, it will be aligned
676 * in such a way that it will not cross two lmb regions and
677 * will fit within a single 16Mb page.
678 * The DART space is assumed to be a full 16Mb region even if
679 * we only use 2Mb of that space. We will use more of it later
680 * for AGP GART. We have to use a full 16Mb large page.
682 DBG("DART base: %lx\n", dart_tablebase);
684 if (dart_tablebase != 0 && dart_tablebase >= base
685 && dart_tablebase < (base + size)) {
686 unsigned long dart_table_end = dart_tablebase + 16 * MB;
687 if (base != dart_tablebase)
688 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
692 if ((base + size) > dart_table_end)
693 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
695 __pa(dart_table_end),
701 #endif /* CONFIG_U3_DART */
702 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
703 prot, mmu_linear_psize, mmu_kernel_ssize));
707 * If we have a memory_limit and we've allocated TCEs then we need to
708 * explicitly map the TCE area at the top of RAM. We also cope with the
709 * case that the TCEs start below memory_limit.
710 * tce_alloc_start/end are 16MB aligned so the mapping should work
711 * for either 4K or 16MB pages.
713 if (tce_alloc_start) {
714 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
715 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
717 if (base + size >= tce_alloc_start)
718 tce_alloc_start = base + size + 1;
720 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
721 __pa(tce_alloc_start), prot,
722 mmu_linear_psize, mmu_kernel_ssize));
727 DBG(" <- htab_initialize()\n");
732 void htab_initialize_secondary(void)
734 if (!firmware_has_feature(FW_FEATURE_LPAR))
735 mtspr(SPRN_SDR1, _SDR1);
739 * Called by asm hashtable.S for doing lazy icache flush
741 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
745 if (!pfn_valid(pte_pfn(pte)))
748 page = pte_page(pte);
751 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
753 __flush_dcache_icache(page_address(page));
754 set_bit(PG_arch_1, &page->flags);
761 #ifdef CONFIG_PPC_MM_SLICES
762 unsigned int get_paca_psize(unsigned long addr)
764 unsigned long index, slices;
766 if (addr < SLICE_LOW_TOP) {
767 slices = get_paca()->context.low_slices_psize;
768 index = GET_LOW_SLICE_INDEX(addr);
770 slices = get_paca()->context.high_slices_psize;
771 index = GET_HIGH_SLICE_INDEX(addr);
773 return (slices >> (index * 4)) & 0xF;
777 unsigned int get_paca_psize(unsigned long addr)
779 return get_paca()->context.user_psize;
784 * Demote a segment to using 4k pages.
785 * For now this makes the whole process use 4k pages.
787 #ifdef CONFIG_PPC_64K_PAGES
788 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
790 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
792 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
793 #ifdef CONFIG_SPU_BASE
794 spu_flush_all_slbs(mm);
796 if (get_paca_psize(addr) != MMU_PAGE_4K) {
797 get_paca()->context = mm->context;
798 slb_flush_and_rebolt();
801 #endif /* CONFIG_PPC_64K_PAGES */
803 #ifdef CONFIG_PPC_SUBPAGE_PROT
805 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
806 * Userspace sets the subpage permissions using the subpage_prot system call.
808 * Result is 0: full permissions, _PAGE_RW: read-only,
809 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
811 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
813 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
817 if (ea >= spt->maxaddr)
819 if (ea < 0x100000000) {
820 /* addresses below 4GB use spt->low_prot */
821 sbpm = spt->low_prot;
823 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
827 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
830 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
832 /* extract 2-bit bitfield for this 4k subpage */
833 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
835 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
836 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
840 #else /* CONFIG_PPC_SUBPAGE_PROT */
841 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
849 * 1 - normal page fault
850 * -1 - critical hash insertion error
851 * -2 - access not permitted by subpage protection mechanism
853 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
857 struct mm_struct *mm;
860 int rc, user_region = 0, local = 0;
863 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
866 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
867 DBG_LOW(" out of pgtable range !\n");
871 /* Get region & vsid */
872 switch (REGION_ID(ea)) {
877 DBG_LOW(" user region with no mm !\n");
880 psize = get_slice_psize(mm, ea);
881 ssize = user_segment_size(ea);
882 vsid = get_vsid(mm->context.id, ea, ssize);
884 case VMALLOC_REGION_ID:
886 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
887 if (ea < VMALLOC_END)
888 psize = mmu_vmalloc_psize;
890 psize = mmu_io_psize;
891 ssize = mmu_kernel_ssize;
895 * Send the problem up to do_page_fault
899 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
906 /* Check CPU locality */
907 tmp = cpumask_of_cpu(smp_processor_id());
908 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
911 #ifdef CONFIG_HUGETLB_PAGE
912 /* Handle hugepage regions */
913 if (HPAGE_SHIFT && mmu_huge_psizes[psize]) {
914 DBG_LOW(" -> huge page !\n");
915 return hash_huge_page(mm, access, ea, vsid, local, trap);
917 #endif /* CONFIG_HUGETLB_PAGE */
919 #ifndef CONFIG_PPC_64K_PAGES
920 /* If we use 4K pages and our psize is not 4K, then we are hitting
921 * a special driver mapping, we need to align the address before
924 if (psize != MMU_PAGE_4K)
925 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
926 #endif /* CONFIG_PPC_64K_PAGES */
928 /* Get PTE and page size from page tables */
929 ptep = find_linux_pte(pgdir, ea);
930 if (ptep == NULL || !pte_present(*ptep)) {
931 DBG_LOW(" no PTE !\n");
935 #ifndef CONFIG_PPC_64K_PAGES
936 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
938 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
939 pte_val(*(ptep + PTRS_PER_PTE)));
941 /* Pre-check access permissions (will be re-checked atomically
942 * in __hash_page_XX but this pre-check is a fast path
944 if (access & ~pte_val(*ptep)) {
945 DBG_LOW(" no access !\n");
949 /* Do actual hashing */
950 #ifdef CONFIG_PPC_64K_PAGES
951 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
952 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
953 demote_segment_4k(mm, ea);
957 /* If this PTE is non-cacheable and we have restrictions on
958 * using non cacheable large pages, then we switch to 4k
960 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
961 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
963 demote_segment_4k(mm, ea);
965 } else if (ea < VMALLOC_END) {
967 * some driver did a non-cacheable mapping
968 * in vmalloc space, so switch vmalloc
971 printk(KERN_ALERT "Reducing vmalloc segment "
972 "to 4kB pages because of "
973 "non-cacheable mapping\n");
974 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
975 #ifdef CONFIG_SPU_BASE
976 spu_flush_all_slbs(mm);
981 if (psize != get_paca_psize(ea)) {
982 get_paca()->context = mm->context;
983 slb_flush_and_rebolt();
985 } else if (get_paca()->vmalloc_sllp !=
986 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
987 get_paca()->vmalloc_sllp =
988 mmu_psize_defs[mmu_vmalloc_psize].sllp;
989 slb_vmalloc_update();
991 #endif /* CONFIG_PPC_64K_PAGES */
993 #ifdef CONFIG_PPC_HAS_HASH_64K
994 if (psize == MMU_PAGE_64K)
995 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
997 #endif /* CONFIG_PPC_HAS_HASH_64K */
999 int spp = subpage_protection(pgdir, ea);
1003 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1007 #ifndef CONFIG_PPC_64K_PAGES
1008 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1010 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1011 pte_val(*(ptep + PTRS_PER_PTE)));
1013 DBG_LOW(" -> rc=%d\n", rc);
1016 EXPORT_SYMBOL_GPL(hash_page);
1018 void hash_preload(struct mm_struct *mm, unsigned long ea,
1019 unsigned long access, unsigned long trap)
1025 unsigned long flags;
1029 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1031 #ifdef CONFIG_PPC_MM_SLICES
1032 /* We only prefault standard pages for now */
1033 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1037 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1038 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1040 /* Get Linux PTE if available */
1044 ptep = find_linux_pte(pgdir, ea);
1048 #ifdef CONFIG_PPC_64K_PAGES
1049 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1050 * a 64K kernel), then we don't preload, hash_page() will take
1051 * care of it once we actually try to access the page.
1052 * That way we don't have to duplicate all of the logic for segment
1053 * page size demotion here
1055 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1057 #endif /* CONFIG_PPC_64K_PAGES */
1060 ssize = user_segment_size(ea);
1061 vsid = get_vsid(mm->context.id, ea, ssize);
1063 /* Hash doesn't like irqs */
1064 local_irq_save(flags);
1066 /* Is that local to this CPU ? */
1067 mask = cpumask_of_cpu(smp_processor_id());
1068 if (cpus_equal(mm->cpu_vm_mask, mask))
1072 #ifdef CONFIG_PPC_HAS_HASH_64K
1073 if (mm->context.user_psize == MMU_PAGE_64K)
1074 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1076 #endif /* CONFIG_PPC_HAS_HASH_64K */
1077 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1078 subpage_protection(pgdir, ea));
1080 local_irq_restore(flags);
1083 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1084 * do not forget to update the assembly call site !
1086 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1089 unsigned long hash, index, shift, hidx, slot;
1091 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1092 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1093 hash = hpt_hash(va, shift, ssize);
1094 hidx = __rpte_to_hidx(pte, index);
1095 if (hidx & _PTEIDX_SECONDARY)
1097 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1098 slot += hidx & _PTEIDX_GROUP_IX;
1099 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
1100 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1101 } pte_iterate_hashed_end();
1104 void flush_hash_range(unsigned long number, int local)
1106 if (ppc_md.flush_hash_range)
1107 ppc_md.flush_hash_range(number, local);
1110 struct ppc64_tlb_batch *batch =
1111 &__get_cpu_var(ppc64_tlb_batch);
1113 for (i = 0; i < number; i++)
1114 flush_hash_page(batch->vaddr[i], batch->pte[i],
1115 batch->psize, batch->ssize, local);
1120 * low_hash_fault is called when we the low level hash code failed
1121 * to instert a PTE due to an hypervisor error
1123 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1125 if (user_mode(regs)) {
1126 #ifdef CONFIG_PPC_SUBPAGE_PROT
1128 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1131 _exception(SIGBUS, regs, BUS_ADRERR, address);
1133 bad_page_fault(regs, address, SIGBUS);
1136 #ifdef CONFIG_DEBUG_PAGEALLOC
1137 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1139 unsigned long hash, hpteg;
1140 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1141 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1142 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1145 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1146 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1148 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1149 mode, HPTE_V_BOLTED,
1150 mmu_linear_psize, mmu_kernel_ssize);
1152 spin_lock(&linear_map_hash_lock);
1153 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1154 linear_map_hash_slots[lmi] = ret | 0x80;
1155 spin_unlock(&linear_map_hash_lock);
1158 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1160 unsigned long hash, hidx, slot;
1161 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1162 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1164 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1165 spin_lock(&linear_map_hash_lock);
1166 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1167 hidx = linear_map_hash_slots[lmi] & 0x7f;
1168 linear_map_hash_slots[lmi] = 0;
1169 spin_unlock(&linear_map_hash_lock);
1170 if (hidx & _PTEIDX_SECONDARY)
1172 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1173 slot += hidx & _PTEIDX_GROUP_IX;
1174 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1177 void kernel_map_pages(struct page *page, int numpages, int enable)
1179 unsigned long flags, vaddr, lmi;
1182 local_irq_save(flags);
1183 for (i = 0; i < numpages; i++, page++) {
1184 vaddr = (unsigned long)page_address(page);
1185 lmi = __pa(vaddr) >> PAGE_SHIFT;
1186 if (lmi >= linear_map_hash_count)
1189 kernel_map_linear_page(vaddr, lmi);
1191 kernel_unmap_linear_page(vaddr, lmi);
1193 local_irq_restore(flags);
1195 #endif /* CONFIG_DEBUG_PAGEALLOC */