2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
37 #include <asm/processor.h>
38 #include <asm/pgtable.h>
40 #include <asm/mmu_context.h>
42 #include <asm/types.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/tlbflush.h>
50 #include <asm/cacheflush.h>
51 #include <asm/cputable.h>
52 #include <asm/sections.h>
55 #include <asm/code-patching.h>
56 #include <asm/fadump.h>
57 #include <asm/firmware.h>
60 #define DBG(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...) udbg_printf(fmt)
68 #define DBG_LOW(fmt...)
76 * Note: pte --> Linux PTE
77 * HPTE --> PowerPC Hashed Page Table Entry
80 * htab_initialize is called with the MMU off (of course), but
81 * the kernel has been copied down to zero so it can directly
82 * reference global data. At this point it is very difficult
83 * to print debug info.
88 extern unsigned long dart_tablebase;
89 #endif /* CONFIG_U3_DART */
91 static unsigned long _SDR1;
92 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
94 struct hash_pte *htab_address;
95 unsigned long htab_size_bytes;
96 unsigned long htab_hash_mask;
97 EXPORT_SYMBOL_GPL(htab_hash_mask);
98 int mmu_linear_psize = MMU_PAGE_4K;
99 int mmu_virtual_psize = MMU_PAGE_4K;
100 int mmu_vmalloc_psize = MMU_PAGE_4K;
101 #ifdef CONFIG_SPARSEMEM_VMEMMAP
102 int mmu_vmemmap_psize = MMU_PAGE_4K;
104 int mmu_io_psize = MMU_PAGE_4K;
105 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
106 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
107 u16 mmu_slb_size = 64;
108 EXPORT_SYMBOL_GPL(mmu_slb_size);
109 #ifdef CONFIG_PPC_64K_PAGES
110 int mmu_ci_restrictions;
112 #ifdef CONFIG_DEBUG_PAGEALLOC
113 static u8 *linear_map_hash_slots;
114 static unsigned long linear_map_hash_count;
115 static DEFINE_SPINLOCK(linear_map_hash_lock);
116 #endif /* CONFIG_DEBUG_PAGEALLOC */
118 /* There are definitions of page sizes arrays to be used when none
119 * is provided by the firmware.
122 /* Pre-POWER4 CPUs (4k pages only)
124 static struct mmu_psize_def mmu_psize_defaults_old[] = {
134 /* POWER4, GPUL, POWER5
136 * Support for 16Mb large pages
138 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
155 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
157 unsigned long rflags = pteflags & 0x1fa;
159 /* _PAGE_EXEC -> NOEXEC */
160 if ((pteflags & _PAGE_EXEC) == 0)
163 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
164 * need to add in 0x1 if it's a read-only user page
166 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
167 (pteflags & _PAGE_DIRTY)))
171 return rflags | HPTE_R_C;
174 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
175 unsigned long pstart, unsigned long prot,
176 int psize, int ssize)
178 unsigned long vaddr, paddr;
179 unsigned int step, shift;
182 shift = mmu_psize_defs[psize].shift;
185 prot = htab_convert_pte_flags(prot);
187 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
188 vstart, vend, pstart, prot, psize, ssize);
190 for (vaddr = vstart, paddr = pstart; vaddr < vend;
191 vaddr += step, paddr += step) {
192 unsigned long hash, hpteg;
193 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
194 unsigned long va = hpt_va(vaddr, vsid, ssize);
195 unsigned long tprot = prot;
197 /* Make kernel text executable */
198 if (overlaps_kernel_text(vaddr, vaddr + step))
201 hash = hpt_hash(va, shift, ssize);
202 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
204 BUG_ON(!ppc_md.hpte_insert);
205 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
206 HPTE_V_BOLTED, psize, ssize);
210 #ifdef CONFIG_DEBUG_PAGEALLOC
211 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
212 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
213 #endif /* CONFIG_DEBUG_PAGEALLOC */
215 return ret < 0 ? ret : 0;
218 #ifdef CONFIG_MEMORY_HOTPLUG
219 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
220 int psize, int ssize)
223 unsigned int step, shift;
225 shift = mmu_psize_defs[psize].shift;
228 if (!ppc_md.hpte_removebolted) {
229 printk(KERN_WARNING "Platform doesn't implement "
230 "hpte_removebolted\n");
234 for (vaddr = vstart; vaddr < vend; vaddr += step)
235 ppc_md.hpte_removebolted(vaddr, psize, ssize);
239 #endif /* CONFIG_MEMORY_HOTPLUG */
241 static int __init htab_dt_scan_seg_sizes(unsigned long node,
242 const char *uname, int depth,
245 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
247 unsigned long size = 0;
249 /* We are scanning "cpu" nodes only */
250 if (type == NULL || strcmp(type, "cpu") != 0)
253 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
257 for (; size >= 4; size -= 4, ++prop) {
259 DBG("1T segment support detected\n");
260 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
264 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
268 static void __init htab_init_seg_sizes(void)
270 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
273 static int __init htab_dt_scan_page_sizes(unsigned long node,
274 const char *uname, int depth,
277 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
279 unsigned long size = 0;
281 /* We are scanning "cpu" nodes only */
282 if (type == NULL || strcmp(type, "cpu") != 0)
285 prop = (u32 *)of_get_flat_dt_prop(node,
286 "ibm,segment-page-sizes", &size);
288 DBG("Page sizes from device-tree:\n");
290 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
292 unsigned int shift = prop[0];
293 unsigned int slbenc = prop[1];
294 unsigned int lpnum = prop[2];
295 unsigned int lpenc = 0;
296 struct mmu_psize_def *def;
299 size -= 3; prop += 3;
300 while(size > 0 && lpnum) {
301 if (prop[0] == shift)
303 prop += 2; size -= 2;
318 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
326 def = &mmu_psize_defs[idx];
331 def->avpnm = (1 << (shift - 23)) - 1;
334 /* We don't know for sure what's up with tlbiel, so
335 * for now we only set it for 4K and 64K pages
337 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
342 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
343 "tlbiel=%d, penc=%d\n",
344 idx, shift, def->sllp, def->avpnm, def->tlbiel,
352 #ifdef CONFIG_HUGETLB_PAGE
353 /* Scan for 16G memory blocks that have been set aside for huge pages
354 * and reserve those blocks for 16G huge pages.
356 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
357 const char *uname, int depth,
359 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
360 unsigned long *addr_prop;
361 u32 *page_count_prop;
362 unsigned int expected_pages;
363 long unsigned int phys_addr;
364 long unsigned int block_size;
366 /* We are scanning "memory" nodes only */
367 if (type == NULL || strcmp(type, "memory") != 0)
370 /* This property is the log base 2 of the number of virtual pages that
371 * will represent this memory block. */
372 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
373 if (page_count_prop == NULL)
375 expected_pages = (1 << page_count_prop[0]);
376 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
377 if (addr_prop == NULL)
379 phys_addr = addr_prop[0];
380 block_size = addr_prop[1];
381 if (block_size != (16 * GB))
383 printk(KERN_INFO "Huge page(16GB) memory: "
384 "addr = 0x%lX size = 0x%lX pages = %d\n",
385 phys_addr, block_size, expected_pages);
386 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
387 memblock_reserve(phys_addr, block_size * expected_pages);
388 add_gpage(phys_addr, block_size, expected_pages);
392 #endif /* CONFIG_HUGETLB_PAGE */
394 static void __init htab_init_page_sizes(void)
398 /* Default to 4K pages only */
399 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
400 sizeof(mmu_psize_defaults_old));
403 * Try to find the available page sizes in the device-tree
405 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
406 if (rc != 0) /* Found */
410 * Not in the device-tree, let's fallback on known size
411 * list for 16M capable GP & GR
413 if (mmu_has_feature(MMU_FTR_16M_PAGE))
414 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
415 sizeof(mmu_psize_defaults_gp));
417 #ifndef CONFIG_DEBUG_PAGEALLOC
419 * Pick a size for the linear mapping. Currently, we only support
420 * 16M, 1M and 4K which is the default
422 if (mmu_psize_defs[MMU_PAGE_16M].shift)
423 mmu_linear_psize = MMU_PAGE_16M;
424 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
425 mmu_linear_psize = MMU_PAGE_1M;
426 #endif /* CONFIG_DEBUG_PAGEALLOC */
428 #ifdef CONFIG_PPC_64K_PAGES
430 * Pick a size for the ordinary pages. Default is 4K, we support
431 * 64K for user mappings and vmalloc if supported by the processor.
432 * We only use 64k for ioremap if the processor
433 * (and firmware) support cache-inhibited large pages.
434 * If not, we use 4k and set mmu_ci_restrictions so that
435 * hash_page knows to switch processes that use cache-inhibited
436 * mappings to 4k pages.
438 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
439 mmu_virtual_psize = MMU_PAGE_64K;
440 mmu_vmalloc_psize = MMU_PAGE_64K;
441 if (mmu_linear_psize == MMU_PAGE_4K)
442 mmu_linear_psize = MMU_PAGE_64K;
443 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
445 * Don't use 64k pages for ioremap on pSeries, since
446 * that would stop us accessing the HEA ethernet.
448 if (!machine_is(pseries))
449 mmu_io_psize = MMU_PAGE_64K;
451 mmu_ci_restrictions = 1;
453 #endif /* CONFIG_PPC_64K_PAGES */
455 #ifdef CONFIG_SPARSEMEM_VMEMMAP
456 /* We try to use 16M pages for vmemmap if that is supported
457 * and we have at least 1G of RAM at boot
459 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
460 memblock_phys_mem_size() >= 0x40000000)
461 mmu_vmemmap_psize = MMU_PAGE_16M;
462 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
463 mmu_vmemmap_psize = MMU_PAGE_64K;
465 mmu_vmemmap_psize = MMU_PAGE_4K;
466 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
468 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
469 "virtual = %d, io = %d"
470 #ifdef CONFIG_SPARSEMEM_VMEMMAP
474 mmu_psize_defs[mmu_linear_psize].shift,
475 mmu_psize_defs[mmu_virtual_psize].shift,
476 mmu_psize_defs[mmu_io_psize].shift
477 #ifdef CONFIG_SPARSEMEM_VMEMMAP
478 ,mmu_psize_defs[mmu_vmemmap_psize].shift
482 #ifdef CONFIG_HUGETLB_PAGE
483 /* Reserve 16G huge page memory sections for huge pages */
484 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
485 #endif /* CONFIG_HUGETLB_PAGE */
488 static int __init htab_dt_scan_pftsize(unsigned long node,
489 const char *uname, int depth,
492 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
495 /* We are scanning "cpu" nodes only */
496 if (type == NULL || strcmp(type, "cpu") != 0)
499 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
501 /* pft_size[0] is the NUMA CEC cookie */
502 ppc64_pft_size = prop[1];
508 static unsigned long __init htab_get_table_size(void)
510 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
512 /* If hash size isn't already provided by the platform, we try to
513 * retrieve it from the device-tree. If it's not there neither, we
514 * calculate it now based on the total RAM size
516 if (ppc64_pft_size == 0)
517 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
519 return 1UL << ppc64_pft_size;
521 /* round mem_size up to next power of 2 */
522 mem_size = memblock_phys_mem_size();
523 rnd_mem_size = 1UL << __ilog2(mem_size);
524 if (rnd_mem_size < mem_size)
528 psize = mmu_psize_defs[mmu_virtual_psize].shift;
529 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
531 return pteg_count << 7;
534 #ifdef CONFIG_MEMORY_HOTPLUG
535 int create_section_mapping(unsigned long start, unsigned long end)
537 return htab_bolt_mapping(start, end, __pa(start),
538 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
542 int remove_section_mapping(unsigned long start, unsigned long end)
544 return htab_remove_mapping(start, end, mmu_linear_psize,
547 #endif /* CONFIG_MEMORY_HOTPLUG */
549 #define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
551 static void __init htab_finish_init(void)
553 extern unsigned int *htab_call_hpte_insert1;
554 extern unsigned int *htab_call_hpte_insert2;
555 extern unsigned int *htab_call_hpte_remove;
556 extern unsigned int *htab_call_hpte_updatepp;
558 #ifdef CONFIG_PPC_HAS_HASH_64K
559 extern unsigned int *ht64_call_hpte_insert1;
560 extern unsigned int *ht64_call_hpte_insert2;
561 extern unsigned int *ht64_call_hpte_remove;
562 extern unsigned int *ht64_call_hpte_updatepp;
564 patch_branch(ht64_call_hpte_insert1,
565 FUNCTION_TEXT(ppc_md.hpte_insert),
567 patch_branch(ht64_call_hpte_insert2,
568 FUNCTION_TEXT(ppc_md.hpte_insert),
570 patch_branch(ht64_call_hpte_remove,
571 FUNCTION_TEXT(ppc_md.hpte_remove),
573 patch_branch(ht64_call_hpte_updatepp,
574 FUNCTION_TEXT(ppc_md.hpte_updatepp),
577 #endif /* CONFIG_PPC_HAS_HASH_64K */
579 patch_branch(htab_call_hpte_insert1,
580 FUNCTION_TEXT(ppc_md.hpte_insert),
582 patch_branch(htab_call_hpte_insert2,
583 FUNCTION_TEXT(ppc_md.hpte_insert),
585 patch_branch(htab_call_hpte_remove,
586 FUNCTION_TEXT(ppc_md.hpte_remove),
588 patch_branch(htab_call_hpte_updatepp,
589 FUNCTION_TEXT(ppc_md.hpte_updatepp),
593 static void __init htab_initialize(void)
596 unsigned long pteg_count;
598 unsigned long base = 0, size = 0, limit;
599 struct memblock_region *reg;
601 DBG(" -> htab_initialize()\n");
603 /* Initialize segment sizes */
604 htab_init_seg_sizes();
606 /* Initialize page sizes */
607 htab_init_page_sizes();
609 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
610 mmu_kernel_ssize = MMU_SEGSIZE_1T;
611 mmu_highuser_ssize = MMU_SEGSIZE_1T;
612 printk(KERN_INFO "Using 1TB segments\n");
616 * Calculate the required size of the htab. We want the number of
617 * PTEGs to equal one half the number of real pages.
619 htab_size_bytes = htab_get_table_size();
620 pteg_count = htab_size_bytes >> 7;
622 htab_hash_mask = pteg_count - 1;
624 if (firmware_has_feature(FW_FEATURE_LPAR)) {
625 /* Using a hypervisor which owns the htab */
628 #ifdef CONFIG_FA_DUMP
630 * If firmware assisted dump is active firmware preserves
631 * the contents of htab along with entire partition memory.
632 * Clear the htab if firmware assisted dump is active so
633 * that we dont end up using old mappings.
635 if (is_fadump_active() && ppc_md.hpte_clear_all)
636 ppc_md.hpte_clear_all();
639 /* Find storage for the HPT. Must be contiguous in
640 * the absolute address space. On cell we want it to be
641 * in the first 2 Gig so we can use it for IOMMU hacks.
643 if (machine_is(cell))
646 limit = MEMBLOCK_ALLOC_ANYWHERE;
648 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
650 DBG("Hash table allocated at %lx, size: %lx\n", table,
653 htab_address = __va(table);
655 /* htab absolute addr + encoded htabsize */
656 _SDR1 = table + __ilog2(pteg_count) - 11;
658 /* Initialize the HPT with no entries */
659 memset((void *)table, 0, htab_size_bytes);
662 mtspr(SPRN_SDR1, _SDR1);
665 prot = pgprot_val(PAGE_KERNEL);
667 #ifdef CONFIG_DEBUG_PAGEALLOC
668 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
669 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
671 memset(linear_map_hash_slots, 0, linear_map_hash_count);
672 #endif /* CONFIG_DEBUG_PAGEALLOC */
674 /* On U3 based machines, we need to reserve the DART area and
675 * _NOT_ map it to avoid cache paradoxes as it's remapped non
679 /* create bolted the linear mapping in the hash table */
680 for_each_memblock(memory, reg) {
681 base = (unsigned long)__va(reg->base);
684 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
687 #ifdef CONFIG_U3_DART
688 /* Do not map the DART space. Fortunately, it will be aligned
689 * in such a way that it will not cross two memblock regions and
690 * will fit within a single 16Mb page.
691 * The DART space is assumed to be a full 16Mb region even if
692 * we only use 2Mb of that space. We will use more of it later
693 * for AGP GART. We have to use a full 16Mb large page.
695 DBG("DART base: %lx\n", dart_tablebase);
697 if (dart_tablebase != 0 && dart_tablebase >= base
698 && dart_tablebase < (base + size)) {
699 unsigned long dart_table_end = dart_tablebase + 16 * MB;
700 if (base != dart_tablebase)
701 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
705 if ((base + size) > dart_table_end)
706 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
708 __pa(dart_table_end),
714 #endif /* CONFIG_U3_DART */
715 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
716 prot, mmu_linear_psize, mmu_kernel_ssize));
718 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
721 * If we have a memory_limit and we've allocated TCEs then we need to
722 * explicitly map the TCE area at the top of RAM. We also cope with the
723 * case that the TCEs start below memory_limit.
724 * tce_alloc_start/end are 16MB aligned so the mapping should work
725 * for either 4K or 16MB pages.
727 if (tce_alloc_start) {
728 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
729 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
731 if (base + size >= tce_alloc_start)
732 tce_alloc_start = base + size + 1;
734 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
735 __pa(tce_alloc_start), prot,
736 mmu_linear_psize, mmu_kernel_ssize));
741 DBG(" <- htab_initialize()\n");
746 void __init early_init_mmu(void)
748 /* Setup initial STAB address in the PACA */
749 get_paca()->stab_real = __pa((u64)&initial_stab);
750 get_paca()->stab_addr = (u64)&initial_stab;
752 /* Initialize the MMU Hash table and create the linear mapping
753 * of memory. Has to be done before stab/slb initialization as
754 * this is currently where the page size encoding is obtained
758 /* Initialize stab / SLB management */
759 if (mmu_has_feature(MMU_FTR_SLB))
764 void __cpuinit early_init_mmu_secondary(void)
766 /* Initialize hash table for that CPU */
767 if (!firmware_has_feature(FW_FEATURE_LPAR))
768 mtspr(SPRN_SDR1, _SDR1);
770 /* Initialize STAB/SLB. We use a virtual address as it works
771 * in real mode on pSeries.
773 if (mmu_has_feature(MMU_FTR_SLB))
776 stab_initialize(get_paca()->stab_addr);
778 #endif /* CONFIG_SMP */
781 * Called by asm hashtable.S for doing lazy icache flush
783 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
787 if (!pfn_valid(pte_pfn(pte)))
790 page = pte_page(pte);
793 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
795 flush_dcache_icache_page(page);
796 set_bit(PG_arch_1, &page->flags);
803 #ifdef CONFIG_PPC_MM_SLICES
804 unsigned int get_paca_psize(unsigned long addr)
806 unsigned long index, slices;
808 if (addr < SLICE_LOW_TOP) {
809 slices = get_paca()->context.low_slices_psize;
810 index = GET_LOW_SLICE_INDEX(addr);
812 slices = get_paca()->context.high_slices_psize;
813 index = GET_HIGH_SLICE_INDEX(addr);
815 return (slices >> (index * 4)) & 0xF;
819 unsigned int get_paca_psize(unsigned long addr)
821 return get_paca()->context.user_psize;
826 * Demote a segment to using 4k pages.
827 * For now this makes the whole process use 4k pages.
829 #ifdef CONFIG_PPC_64K_PAGES
830 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
832 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
834 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
835 #ifdef CONFIG_SPU_BASE
836 spu_flush_all_slbs(mm);
838 if (get_paca_psize(addr) != MMU_PAGE_4K) {
839 get_paca()->context = mm->context;
840 slb_flush_and_rebolt();
843 #endif /* CONFIG_PPC_64K_PAGES */
845 #ifdef CONFIG_PPC_SUBPAGE_PROT
847 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
848 * Userspace sets the subpage permissions using the subpage_prot system call.
850 * Result is 0: full permissions, _PAGE_RW: read-only,
851 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
853 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
855 struct subpage_prot_table *spt = &mm->context.spt;
859 if (ea >= spt->maxaddr)
861 if (ea < 0x100000000) {
862 /* addresses below 4GB use spt->low_prot */
863 sbpm = spt->low_prot;
865 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
869 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
872 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
874 /* extract 2-bit bitfield for this 4k subpage */
875 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
877 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
878 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
882 #else /* CONFIG_PPC_SUBPAGE_PROT */
883 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
889 void hash_failure_debug(unsigned long ea, unsigned long access,
890 unsigned long vsid, unsigned long trap,
891 int ssize, int psize, unsigned long pte)
893 if (!printk_ratelimit())
895 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
896 ea, access, current->comm);
897 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
898 trap, vsid, ssize, psize, pte);
903 * 1 - normal page fault
904 * -1 - critical hash insertion error
905 * -2 - access not permitted by subpage protection mechanism
907 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
911 struct mm_struct *mm;
914 const struct cpumask *tmp;
915 int rc, user_region = 0, local = 0;
918 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
921 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
922 DBG_LOW(" out of pgtable range !\n");
926 /* Get region & vsid */
927 switch (REGION_ID(ea)) {
932 DBG_LOW(" user region with no mm !\n");
935 psize = get_slice_psize(mm, ea);
936 ssize = user_segment_size(ea);
937 vsid = get_vsid(mm->context.id, ea, ssize);
939 case VMALLOC_REGION_ID:
941 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
942 if (ea < VMALLOC_END)
943 psize = mmu_vmalloc_psize;
945 psize = mmu_io_psize;
946 ssize = mmu_kernel_ssize;
950 * Send the problem up to do_page_fault
954 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
961 /* Check CPU locality */
962 tmp = cpumask_of(smp_processor_id());
963 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
966 #ifndef CONFIG_PPC_64K_PAGES
967 /* If we use 4K pages and our psize is not 4K, then we might
968 * be hitting a special driver mapping, and need to align the
969 * address before we fetch the PTE.
971 * It could also be a hugepage mapping, in which case this is
972 * not necessary, but it's not harmful, either.
974 if (psize != MMU_PAGE_4K)
975 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
976 #endif /* CONFIG_PPC_64K_PAGES */
978 /* Get PTE and page size from page tables */
979 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
980 if (ptep == NULL || !pte_present(*ptep)) {
981 DBG_LOW(" no PTE !\n");
985 /* Add _PAGE_PRESENT to the required access perm */
986 access |= _PAGE_PRESENT;
988 /* Pre-check access permissions (will be re-checked atomically
989 * in __hash_page_XX but this pre-check is a fast path
991 if (access & ~pte_val(*ptep)) {
992 DBG_LOW(" no access !\n");
996 #ifdef CONFIG_HUGETLB_PAGE
998 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
999 ssize, hugeshift, psize);
1000 #endif /* CONFIG_HUGETLB_PAGE */
1002 #ifndef CONFIG_PPC_64K_PAGES
1003 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1005 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1006 pte_val(*(ptep + PTRS_PER_PTE)));
1008 /* Do actual hashing */
1009 #ifdef CONFIG_PPC_64K_PAGES
1010 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1011 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1012 demote_segment_4k(mm, ea);
1013 psize = MMU_PAGE_4K;
1016 /* If this PTE is non-cacheable and we have restrictions on
1017 * using non cacheable large pages, then we switch to 4k
1019 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1020 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1022 demote_segment_4k(mm, ea);
1023 psize = MMU_PAGE_4K;
1024 } else if (ea < VMALLOC_END) {
1026 * some driver did a non-cacheable mapping
1027 * in vmalloc space, so switch vmalloc
1030 printk(KERN_ALERT "Reducing vmalloc segment "
1031 "to 4kB pages because of "
1032 "non-cacheable mapping\n");
1033 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1034 #ifdef CONFIG_SPU_BASE
1035 spu_flush_all_slbs(mm);
1040 if (psize != get_paca_psize(ea)) {
1041 get_paca()->context = mm->context;
1042 slb_flush_and_rebolt();
1044 } else if (get_paca()->vmalloc_sllp !=
1045 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1046 get_paca()->vmalloc_sllp =
1047 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1048 slb_vmalloc_update();
1050 #endif /* CONFIG_PPC_64K_PAGES */
1052 #ifdef CONFIG_PPC_HAS_HASH_64K
1053 if (psize == MMU_PAGE_64K)
1054 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1056 #endif /* CONFIG_PPC_HAS_HASH_64K */
1058 int spp = subpage_protection(mm, ea);
1062 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1066 /* Dump some info in case of hash insertion failure, they should
1067 * never happen so it is really useful to know if/when they do
1070 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1072 #ifndef CONFIG_PPC_64K_PAGES
1073 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1075 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1076 pte_val(*(ptep + PTRS_PER_PTE)));
1078 DBG_LOW(" -> rc=%d\n", rc);
1081 EXPORT_SYMBOL_GPL(hash_page);
1083 void hash_preload(struct mm_struct *mm, unsigned long ea,
1084 unsigned long access, unsigned long trap)
1089 unsigned long flags;
1090 int rc, ssize, local = 0;
1092 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1094 #ifdef CONFIG_PPC_MM_SLICES
1095 /* We only prefault standard pages for now */
1096 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1100 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1101 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1103 /* Get Linux PTE if available */
1107 ptep = find_linux_pte(pgdir, ea);
1111 #ifdef CONFIG_PPC_64K_PAGES
1112 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1113 * a 64K kernel), then we don't preload, hash_page() will take
1114 * care of it once we actually try to access the page.
1115 * That way we don't have to duplicate all of the logic for segment
1116 * page size demotion here
1118 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1120 #endif /* CONFIG_PPC_64K_PAGES */
1123 ssize = user_segment_size(ea);
1124 vsid = get_vsid(mm->context.id, ea, ssize);
1126 /* Hash doesn't like irqs */
1127 local_irq_save(flags);
1129 /* Is that local to this CPU ? */
1130 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1134 #ifdef CONFIG_PPC_HAS_HASH_64K
1135 if (mm->context.user_psize == MMU_PAGE_64K)
1136 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1138 #endif /* CONFIG_PPC_HAS_HASH_64K */
1139 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1140 subpage_protection(mm, ea));
1142 /* Dump some info in case of hash insertion failure, they should
1143 * never happen so it is really useful to know if/when they do
1146 hash_failure_debug(ea, access, vsid, trap, ssize,
1147 mm->context.user_psize, pte_val(*ptep));
1149 local_irq_restore(flags);
1152 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1153 * do not forget to update the assembly call site !
1155 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1158 unsigned long hash, index, shift, hidx, slot;
1160 DBG_LOW("flush_hash_page(va=%016lx)\n", va);
1161 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1162 hash = hpt_hash(va, shift, ssize);
1163 hidx = __rpte_to_hidx(pte, index);
1164 if (hidx & _PTEIDX_SECONDARY)
1166 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1167 slot += hidx & _PTEIDX_GROUP_IX;
1168 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1169 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1170 } pte_iterate_hashed_end();
1173 void flush_hash_range(unsigned long number, int local)
1175 if (ppc_md.flush_hash_range)
1176 ppc_md.flush_hash_range(number, local);
1179 struct ppc64_tlb_batch *batch =
1180 &__get_cpu_var(ppc64_tlb_batch);
1182 for (i = 0; i < number; i++)
1183 flush_hash_page(batch->vaddr[i], batch->pte[i],
1184 batch->psize, batch->ssize, local);
1189 * low_hash_fault is called when we the low level hash code failed
1190 * to instert a PTE due to an hypervisor error
1192 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1194 if (user_mode(regs)) {
1195 #ifdef CONFIG_PPC_SUBPAGE_PROT
1197 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1200 _exception(SIGBUS, regs, BUS_ADRERR, address);
1202 bad_page_fault(regs, address, SIGBUS);
1205 #ifdef CONFIG_DEBUG_PAGEALLOC
1206 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1208 unsigned long hash, hpteg;
1209 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1210 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1211 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1214 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1215 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1217 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1218 mode, HPTE_V_BOLTED,
1219 mmu_linear_psize, mmu_kernel_ssize);
1221 spin_lock(&linear_map_hash_lock);
1222 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1223 linear_map_hash_slots[lmi] = ret | 0x80;
1224 spin_unlock(&linear_map_hash_lock);
1227 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1229 unsigned long hash, hidx, slot;
1230 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1231 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1233 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1234 spin_lock(&linear_map_hash_lock);
1235 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1236 hidx = linear_map_hash_slots[lmi] & 0x7f;
1237 linear_map_hash_slots[lmi] = 0;
1238 spin_unlock(&linear_map_hash_lock);
1239 if (hidx & _PTEIDX_SECONDARY)
1241 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1242 slot += hidx & _PTEIDX_GROUP_IX;
1243 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1246 void kernel_map_pages(struct page *page, int numpages, int enable)
1248 unsigned long flags, vaddr, lmi;
1251 local_irq_save(flags);
1252 for (i = 0; i < numpages; i++, page++) {
1253 vaddr = (unsigned long)page_address(page);
1254 lmi = __pa(vaddr) >> PAGE_SHIFT;
1255 if (lmi >= linear_map_hash_count)
1258 kernel_map_linear_page(vaddr, lmi);
1260 kernel_unmap_linear_page(vaddr, lmi);
1262 local_irq_restore(flags);
1264 #endif /* CONFIG_DEBUG_PAGEALLOC */
1266 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1267 phys_addr_t first_memblock_size)
1269 /* We don't currently support the first MEMBLOCK not mapping 0
1270 * physical on those processors
1272 BUG_ON(first_memblock_base != 0);
1274 /* On LPAR systems, the first entry is our RMA region,
1275 * non-LPAR 64-bit hash MMU systems don't have a limitation
1276 * on real mode access, but using the first entry works well
1277 * enough. We also clamp it to 1G to avoid some funky things
1278 * such as RTAS bugs etc...
1280 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1282 /* Finally limit subsequent allocations */
1283 memblock_set_current_limit(ppc64_rma_size);