2 * Low-level SLB routines
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
6 * Based on earlier C version:
7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
8 * Copyright (c) 2001 Dave Engebretsen
9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <asm/processor.h>
18 #include <asm/ppc_asm.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cputable.h>
23 #include <asm/pgtable.h>
24 #include <asm/firmware.h>
26 /* void slb_allocate_realmode(unsigned long ea);
28 * Create an SLB entry for the given EA (user or kernel).
29 * r3 = faulting address, r13 = PACA
30 * r9, r10, r11 are clobbered by this function
31 * No other registers are examined or changed.
33 _GLOBAL(slb_allocate_realmode)
34 /* r3 = faulting address */
36 srdi r9,r3,60 /* get region */
37 srdi r10,r3,28 /* get esid */
38 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
40 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
41 blt cr7,0f /* user or kernel? */
43 /* kernel address: proto-VSID = ESID */
44 /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
45 * this code will generate the protoVSID 0xfffffffff for the
46 * top segment. That's ok, the scramble below will translate
47 * it to VSID 0, which is reserved as a bad VSID - one which
48 * will never have any pages in it. */
50 /* Check if hitting the linear mapping or some other kernel space
54 /* Linear mapping encoding bits, the "li" instruction below will
55 * be patched by the kernel at boot
57 _GLOBAL(slb_miss_kernel_load_linear)
61 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
65 #ifdef CONFIG_SPARSEMEM_VMEMMAP
66 /* Check virtual memmap region. To be patches at kernel boot */
69 _GLOBAL(slb_miss_kernel_load_vmemmap)
73 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
75 /* vmalloc mapping gets the encoding from the PACA as the mapping
76 * can be demoted from 64K -> 4K dynamically on some machines
79 cmpldi r11,(VMALLOC_SIZE >> 28) - 1
81 lhz r11,PACAVMALLOCSLLP(r13)
85 _GLOBAL(slb_miss_kernel_load_io)
90 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
93 0: /* user address: proto-VSID = context << 15 | ESID. First check
94 * if the address is within the boundaries of the user region
96 srdi. r9,r10,USER_ESID_BITS
97 bne- 8f /* invalid ea bits set */
100 /* when using slices, we extract the psize off the slice bitmaps
101 * and then we need to get the sllp encoding off the mmu_psize_defs
104 * XXX This is a bit inefficient especially for the normal case,
105 * so we should try to implement a fast path for the standard page
106 * size using the old sllp value so we avoid the array. We cannot
107 * really do dynamic patching unfortunately as processes might flip
108 * between 4k and 64k standard page size
110 #ifdef CONFIG_PPC_MM_SLICES
113 /* below SLICE_LOW_TOP */
117 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
119 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
120 addi r9,r11,PACAHIGHSLICEPSIZE
121 lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
122 /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
123 rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
129 * r9 is get_paca()->context.low_slices_psize, r11 is index
131 ld r9,PACALOWSLICESPSIZE(r13)
134 sldi r11,r11,2 /* index * 4 */
135 /* Extract the psize and multiply to get an array offset */
138 mulli r9,r9,MMUPSIZEDEFSIZE
140 /* Now get to the array and obtain the sllp
143 ld r11,mmu_psize_defs@got(r11)
145 ld r11,MMUPSIZESLLP(r11)
146 ori r11,r11,SLB_VSID_USER
148 /* paca context sllp already contains the SLB_VSID_USER bits */
149 lhz r11,PACACONTEXTSLLP(r13)
150 #endif /* CONFIG_PPC_MM_SLICES */
152 ld r9,PACACONTEXTID(r13)
155 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
156 rldimi r10,r9,USER_ESID_BITS,0
158 bge slb_finish_load_1T
159 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
163 li r10,0 /* BAD_VSID */
164 li r11,SLB_VSID_USER /* flags don't much matter */
169 /* void slb_allocate_user(unsigned long ea);
171 * Create an SLB entry for the given EA (user or kernel).
172 * r3 = faulting address, r13 = PACA
173 * r9, r10, r11 are clobbered by this function
174 * No other registers are examined or changed.
176 * It is called with translation enabled in order to be able to walk the
177 * page tables. This is not currently used.
179 _GLOBAL(slb_allocate_user)
180 /* r3 = faulting address */
181 srdi r10,r3,28 /* get esid */
183 crset 4*cr7+lt /* set "user" flag for later */
185 /* check if we fit in the range covered by the pagetables*/
186 srdi. r9,r3,PGTABLE_EADDR_SIZE
187 crnot 4*cr0+eq,4*cr0+eq
190 /* now we need to get to the page tables in order to get the page
191 * size encoding from the PMD. In the future, we'll be able to deal
192 * with 1T segments too by getting the encoding from the PGD instead
197 rlwinm r11,r10,8,25,28
198 ldx r9,r9,r11 /* get pgd_t */
201 rlwinm r11,r10,3,17,28
202 ldx r9,r9,r11 /* get pmd_t */
206 /* build vsid flags */
207 andi. r11,r9,SLB_VSID_LLP
208 ori r11,r11,SLB_VSID_USER
210 /* get context to calculate proto-VSID */
211 ld r9,PACACONTEXTID(r13)
212 rldimi r10,r9,USER_ESID_BITS,0
214 /* fall through slb_finish_load */
216 #endif /* __DISABLED__ */
220 * Finish loading of an SLB entry and return
222 * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
225 ASM_VSID_SCRAMBLE(r10,r9,256M)
227 * bits above VSID_BITS_256M need to be ignored from r10
228 * also combine VSID and flags
230 rldimi r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M))
232 /* r3 = EA, r11 = VSID data */
234 * Find a slot, round robin. Previously we tried to find a
235 * free slot first but that took too long. Unfortunately we
236 * dont have any LRU information to help us choose a slot.
239 7: ld r10,PACASTABRR(r13)
241 /* This gets soft patched on boot. */
242 _GLOBAL(slb_compare_rr_to_size)
246 li r10,SLB_NUM_BOLTED
249 std r10,PACASTABRR(r13)
252 rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
253 oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
255 /* r3 = ESID data, r11 = VSID data */
258 * No need for an isync before or after this slbmte. The exception
259 * we enter with and the rfid we exit with are context synchronizing.
263 /* we're done for kernel addresses */
264 crclr 4*cr0+eq /* set result to "success" */
267 /* Update the slb cache */
268 lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
269 cmpldi r3,SLB_CACHE_ENTRIES
272 /* still room in the slb cache */
273 sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
274 rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
275 add r11,r11,r13 /* r11 = (u16 *)paca + offset */
276 sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
277 addi r3,r3,1 /* offset++ */
279 1: /* offset >= SLB_CACHE_ENTRIES */
280 li r3,SLB_CACHE_ENTRIES+1
282 sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
283 crclr 4*cr0+eq /* set result to "success" */
287 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
289 * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
292 srdi r10,r10,40-28 /* get 1T ESID */
293 ASM_VSID_SCRAMBLE(r10,r9,1T)
295 * bits above VSID_BITS_1T need to be ignored from r10
296 * also combine VSID and flags
298 rldimi r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T))
299 li r10,MMU_SEGSIZE_1T
300 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
302 /* r3 = EA, r11 = VSID data */
303 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */