arch/powerpc/platforms/85xx/mpc85xx_ads.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/kdev_t.h>
  18 #include <linux/delay.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/of_platform.h>
  21
  22 #include <asm/system.h>
  23 #include <asm/time.h>
  24 #include <asm/machdep.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/mpic.h>
  27 #include <mm/mmu_decl.h>
  28 #include <asm/udbg.h>
  29
  30 #include <sysdev/fsl_soc.h>
  31 #include <sysdev/fsl_pci.h>
  32
  33 #ifdef CONFIG_CPM2
  34 #include <asm/cpm2.h>
  35 #include <sysdev/cpm2_pic.h>
  36 #endif
  37
  38 #include "mpc85xx.h"
  39
  40 #ifdef CONFIG_PCI
  41 static int mpc85xx_exclude_device(struct pci_controller *hose,
  42                                    u_char bus, u_char devfn)
  43 {
  44         if (bus == 0 && PCI_SLOT(devfn) == 0)
  45                 return PCIBIOS_DEVICE_NOT_FOUND;
  46         else
  47                 return PCIBIOS_SUCCESSFUL;
  48 }
  49 #endif /* CONFIG_PCI */
  50
  51 static void __init mpc85xx_ads_pic_init(void)
  52 {
  53         struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
  54                         0, 256, " OpenPIC  ");
  55         BUG_ON(mpic == NULL);
  56         mpic_init(mpic);
  57
  58         mpc85xx_cpm2_pic_init();
  59 }
  60
  61 /*
  62  * Setup the architecture
  63  */
  64 #ifdef CONFIG_CPM2
  65 struct cpm_pin {
  66         int port, pin, flags;
  67 };
  68
  69 static const struct cpm_pin mpc8560_ads_pins[] = {
  70         /* SCC1 */
  71         {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  72         {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  73         {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  74
  75         /* SCC2 */
  76         {2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  77         {2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  78         {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  79         {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  80         {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  81
  82         /* FCC2 */
  83         {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  84         {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  85         {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  86         {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  87         {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  88         {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  89         {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  90         {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  91         {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  92         {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  93         {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  94         {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  95         {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  96         {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  97         {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
  98         {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
  99
 100         /* FCC3 */
 101         {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 102         {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 103         {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 104         {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 105         {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 106         {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 107         {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 108         {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 109         {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 110         {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 111         {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 112         {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 113         {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
 114         {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
 115         {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
 116         {2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 117 };
 118
 119 static void __init init_ioports(void)
 120 {
 121         int i;
 122
 123         for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
 124                 const struct cpm_pin *pin = &mpc8560_ads_pins[i];
 125                 cpm2_set_pin(pin->port, pin->pin, pin->flags);
 126         }
 127
 128         cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
 129         cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
 130         cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
 131         cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
 132         cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
 133         cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
 134         cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
 135         cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
 136 }
 137 #endif
 138
 139 static void __init mpc85xx_ads_setup_arch(void)
 140 {
 141 #ifdef CONFIG_PCI
 142         struct device_node *np;
 143 #endif
 144
 145         if (ppc_md.progress)
 146                 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
 147
 148 #ifdef CONFIG_CPM2
 149         cpm2_reset();
 150         init_ioports();
 151 #endif
 152
 153 #ifdef CONFIG_PCI
 154         for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
 155                 fsl_add_bridge(np, 1);
 156
 157         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 158 #endif
 159 }
 160
 161 static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
 162 {
 163         uint pvid, svid, phid1;
 164
 165         pvid = mfspr(SPRN_PVR);
 166         svid = mfspr(SPRN_SVR);
 167
 168         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 169         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 170         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 171
 172         /* Display cpu Pll setting */
 173         phid1 = mfspr(SPRN_HID1);
 174         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 175 }
 176
 177 machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
 178
 179 /*
 180  * Called very early, device-tree isn't unflattened
 181  */
 182 static int __init mpc85xx_ads_probe(void)
 183 {
 184         unsigned long root = of_get_flat_dt_root();
 185
 186         return of_flat_dt_is_compatible(root, "MPC85xxADS");
 187 }
 188
 189 define_machine(mpc85xx_ads) {
 190         .name                   = "MPC85xx ADS",
 191         .probe                  = mpc85xx_ads_probe,
 192         .setup_arch             = mpc85xx_ads_setup_arch,
 193         .init_IRQ               = mpc85xx_ads_pic_init,
 194         .show_cpuinfo           = mpc85xx_ads_show_cpuinfo,
 195         .get_irq                = mpic_get_irq,
 196         .restart                = fsl_rstcr_restart,
 197         .calibrate_decr         = generic_calibrate_decr,
 198         .progress               = udbg_progress,
 199 };