2 * MPC85xx setup and early boot code plus other random bits.
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/pci.h>
20 #include <linux/kdev_t.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/initrd.h>
26 #include <linux/interrupt.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/of_platform.h>
30 #include <asm/system.h>
31 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
36 #include <asm/machdep.h>
38 #include <asm/pci-bridge.h>
40 #include <mm/mmu_decl.h>
44 #include <asm/i8259.h>
46 #include <sysdev/fsl_soc.h>
47 #include <sysdev/fsl_pci.h>
52 * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
53 * various logic and performs system control functions.
54 * Here is the FPGA/CPLD register map.
57 u8 cm_ver; /* Board version */
58 u8 cm_csr; /* General control/status */
59 u8 cm_rst; /* Reset control */
60 u8 cm_hsclk; /* High speed clock */
61 u8 cm_hsxclk; /* High speed clock extended */
62 u8 cm_led; /* LED data */
63 u8 cm_pci; /* PCI control/status */
64 u8 cm_dma; /* DMA control */
65 u8 res[248]; /* Total 256 bytes */
68 static struct cadmus_reg *cadmus;
72 #define ARCADIA_HOST_BRIDGE_IDSEL 17
73 #define ARCADIA_2ND_BRIDGE_IDSEL 3
75 static int mpc85xx_exclude_device(struct pci_controller *hose,
76 u_char bus, u_char devfn)
78 /* We explicitly do not go past the Tundra 320 Bridge */
79 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
80 return PCIBIOS_DEVICE_NOT_FOUND;
81 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
82 return PCIBIOS_DEVICE_NOT_FOUND;
84 return PCIBIOS_SUCCESSFUL;
87 static void mpc85xx_cds_restart(char *cmd)
92 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
95 /* Use the VIA Super Southbridge to force a PCI reset */
96 pci_read_config_byte(dev, 0x47, &tmp);
97 pci_write_config_byte(dev, 0x47, tmp | 1);
99 /* Flush the outbound PCI write queues */
100 pci_read_config_byte(dev, 0x47, &tmp);
103 * At this point, the harware reset should have triggered.
104 * However, if it doesn't work for some mysterious reason,
105 * just fall through to the default reset below.
112 * If we can't find the VIA chip (maybe the P2P bridge is disabled)
113 * or the VIA chip reset didn't work, just use the default reset.
115 fsl_rstcr_restart(NULL);
118 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
121 if (dev->vendor == PCI_VENDOR_ID_VIA) {
122 switch (dev->device) {
123 case PCI_DEVICE_ID_VIA_82C586_1:
125 * U-Boot does not set the enable bits
126 * for the IDE device. Force them on here.
128 pci_read_config_byte(dev, 0x40, &c);
129 c |= 0x03; /* IDE: Chip Enable Bits */
130 pci_write_config_byte(dev, 0x40, c);
133 * Since only primary interface works, force the
134 * IDE function to standard primary IDE interrupt
138 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
141 * Force legacy USB interrupt routing
143 case PCI_DEVICE_ID_VIA_82C586_2:
144 /* There are two USB controllers.
145 * Identify them by functon number
147 if (PCI_FUNC(dev->devfn) == 3)
151 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
158 static void __devinit skip_fake_bridge(struct pci_dev *dev)
160 /* Make it an error to skip the fake bridge
161 * in pci_setup_device() in probe.c */
162 dev->hdr_type = 0x7f;
164 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
165 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
166 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
168 #define PCI_DEVICE_ID_IDT_TSI310 0x01a7
171 * Fix Tsi310 PCI-X bridge resource.
172 * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
173 * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
175 void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
177 struct pci_dev *dev = bus->self;
178 struct resource *res = bus->resource[0];
181 dev->vendor == PCI_VENDOR_ID_IBM &&
182 dev->device == PCI_DEVICE_ID_IDT_TSI310) {
186 res->flags = IORESOURCE_IO;
187 pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
188 pr_info("mpc85xx_cds: %pR\n", res);
192 fsl_pcibios_fixup_bus(bus);
195 #ifdef CONFIG_PPC_I8259
196 static void mpc85xx_8259_cascade_handler(unsigned int irq,
197 struct irq_desc *desc)
199 unsigned int cascade_irq = i8259_irq();
201 if (cascade_irq != NO_IRQ)
202 /* handle an interrupt from the 8259 */
203 generic_handle_irq(cascade_irq);
205 /* check for any interrupts from the shared IRQ line */
206 handle_fasteoi_irq(irq, desc);
209 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
214 static struct irqaction mpc85xxcds_8259_irqaction = {
215 .handler = mpc85xx_8259_cascade_action,
216 .flags = IRQF_SHARED | IRQF_NO_THREAD,
217 .name = "8259 cascade",
219 #endif /* PPC_I8259 */
220 #endif /* CONFIG_PCI */
222 static void __init mpc85xx_cds_pic_init(void)
225 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
226 0, 256, " OpenPIC ");
227 BUG_ON(mpic == NULL);
231 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
232 static int mpc85xx_cds_8259_attach(void)
235 struct device_node *np = NULL;
236 struct device_node *cascade_node = NULL;
239 /* Initialize the i8259 controller */
240 for_each_node_by_type(np, "interrupt-controller")
241 if (of_device_is_compatible(np, "chrp,iic")) {
246 if (cascade_node == NULL) {
247 printk(KERN_DEBUG "Could not find i8259 PIC\n");
251 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
252 if (cascade_irq == NO_IRQ) {
253 printk(KERN_ERR "Failed to map cascade interrupt\n");
257 i8259_init(cascade_node, 0);
258 of_node_put(cascade_node);
261 * Hook the interrupt to make sure desc->action is never NULL.
262 * This is required to ensure that the interrupt does not get
263 * disabled when the last user of the shared IRQ line frees their
266 if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
267 printk(KERN_ERR "Failed to setup cascade interrupt\n");
271 /* Success. Connect our low-level cascade handler. */
272 irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
276 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
278 #endif /* CONFIG_PPC_I8259 */
281 * Setup the architecture
283 static void __init mpc85xx_cds_setup_arch(void)
285 struct device_node *np;
289 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
291 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
293 pr_err("Could not find FPGA node.\n");
297 cadmus = of_iomap(np, 0);
300 pr_err("Fail to map FPGA area.\n");
304 if (ppc_md.progress) {
306 cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
307 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
308 in_8(&cadmus->cm_ver), cds_pci_slot);
309 ppc_md.progress(buf, 0);
313 for_each_node_by_type(np, "pci") {
314 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
315 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
316 struct resource rsrc;
317 of_address_to_resource(np, 0, &rsrc);
318 if ((rsrc.start & 0xfffff) == 0x8000)
319 fsl_add_bridge(np, 1);
321 fsl_add_bridge(np, 0);
325 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
326 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
330 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
332 uint pvid, svid, phid1;
334 pvid = mfspr(SPRN_PVR);
335 svid = mfspr(SPRN_SVR);
337 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
338 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
339 in_8(&cadmus->cm_ver));
340 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
341 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
343 /* Display cpu Pll setting */
344 phid1 = mfspr(SPRN_HID1);
345 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
350 * Called very early, device-tree isn't unflattened
352 static int __init mpc85xx_cds_probe(void)
354 unsigned long root = of_get_flat_dt_root();
356 return of_flat_dt_is_compatible(root, "MPC85xxCDS");
359 machine_device_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
361 define_machine(mpc85xx_cds) {
362 .name = "MPC85xx CDS",
363 .probe = mpc85xx_cds_probe,
364 .setup_arch = mpc85xx_cds_setup_arch,
365 .init_IRQ = mpc85xx_cds_pic_init,
366 .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
367 .get_irq = mpic_get_irq,
369 .restart = mpc85xx_cds_restart,
370 .pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
372 .restart = fsl_rstcr_restart,
374 .calibrate_decr = generic_calibrate_decr,
375 .progress = udbg_progress,