arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_device.h>
  35 #include <linux/phy.h>
  36 #include <linux/lmb.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/atomic.h>
  40 #include <asm/time.h>
  41 #include <asm/io.h>
  42 #include <asm/machdep.h>
  43 #include <asm/pci-bridge.h>
  44 #include <asm/irq.h>
  45 #include <mm/mmu_decl.h>
  46 #include <asm/prom.h>
  47 #include <asm/udbg.h>
  48 #include <sysdev/fsl_soc.h>
  49 #include <sysdev/fsl_pci.h>
  50 #include <sysdev/simple_gpio.h>
  51 #include <asm/qe.h>
  52 #include <asm/qe_ic.h>
  53 #include <asm/mpic.h>
  54 #include <asm/swiotlb.h>
  55
  56 #undef DEBUG
  57 #ifdef DEBUG
  58 #define DBG(fmt...) udbg_printf(fmt)
  59 #else
  60 #define DBG(fmt...)
  61 #endif
  62
  63 #define MV88E1111_SCR   0x10
  64 #define MV88E1111_SCR_125CLK    0x0010
  65 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
  66 {
  67         int scr;
  68         int err;
  69
  70         /* Workaround for the 125 CLK Toggle */
  71         scr = phy_read(phydev, MV88E1111_SCR);
  72
  73         if (scr < 0)
  74                 return scr;
  75
  76         err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
  77
  78         if (err)
  79                 return err;
  80
  81         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  82
  83         if (err)
  84                 return err;
  85
  86         scr = phy_read(phydev, MV88E1111_SCR);
  87
  88         if (scr < 0)
  89                 return scr;
  90
  91         err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
  92
  93         return err;
  94 }
  95
  96 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
  97 {
  98         int temp;
  99         int err;
 100
 101         /* Errata */
 102         err = phy_write(phydev,29, 0x0006);
 103
 104         if (err)
 105                 return err;
 106
 107         temp = phy_read(phydev, 30);
 108
 109         if (temp < 0)
 110                 return temp;
 111
 112         temp = (temp & (~0x8000)) | 0x4000;
 113         err = phy_write(phydev,30, temp);
 114
 115         if (err)
 116                 return err;
 117
 118         err = phy_write(phydev,29, 0x000a);
 119
 120         if (err)
 121                 return err;
 122
 123         temp = phy_read(phydev, 30);
 124
 125         if (temp < 0)
 126                 return temp;
 127
 128         temp = phy_read(phydev, 30);
 129
 130         if (temp < 0)
 131                 return temp;
 132
 133         temp &= ~0x0020;
 134
 135         err = phy_write(phydev,30,temp);
 136
 137         if (err)
 138                 return err;
 139
 140         /* Disable automatic MDI/MDIX selection */
 141         temp = phy_read(phydev, 16);
 142
 143         if (temp < 0)
 144                 return temp;
 145
 146         temp &= ~0x0060;
 147         err = phy_write(phydev,16,temp);
 148
 149         return err;
 150 }
 151
 152 /* ************************************************************************
 153  *
 154  * Setup the architecture
 155  *
 156  */
 157 #ifdef CONFIG_SMP
 158 extern void __init mpc85xx_smp_init(void);
 159 #endif
 160
 161 #ifdef CONFIG_QUICC_ENGINE
 162 static struct of_device_id mpc85xx_qe_ids[] __initdata = {
 163         { .type = "qe", },
 164         { .compatible = "fsl,qe", },
 165         { },
 166 };
 167
 168 static void __init mpc85xx_publish_qe_devices(void)
 169 {
 170         struct device_node *np;
 171
 172         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 173         if (!of_device_is_available(np)) {
 174                 of_node_put(np);
 175                 return;
 176         }
 177
 178         of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
 179 }
 180 #else
 181 static void __init mpc85xx_publish_qe_devices(void) { }
 182 #endif /* CONFIG_QUICC_ENGINE */
 183
 184 static void __init mpc85xx_mds_setup_arch(void)
 185 {
 186         struct device_node *np;
 187         static u8 __iomem *bcsr_regs = NULL;
 188 #ifdef CONFIG_PCI
 189         struct pci_controller *hose;
 190 #endif
 191         dma_addr_t max = 0xffffffff;
 192
 193         if (ppc_md.progress)
 194                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
 195
 196         /* Map BCSR area */
 197         np = of_find_node_by_name(NULL, "bcsr");
 198         if (np != NULL) {
 199                 struct resource res;
 200
 201                 of_address_to_resource(np, 0, &res);
 202                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
 203                 of_node_put(np);
 204         }
 205
 206 #ifdef CONFIG_PCI
 207         for_each_node_by_type(np, "pci") {
 208                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 209                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 210                         struct resource rsrc;
 211                         of_address_to_resource(np, 0, &rsrc);
 212                         if ((rsrc.start & 0xfffff) == 0x8000)
 213                                 fsl_add_bridge(np, 1);
 214                         else
 215                                 fsl_add_bridge(np, 0);
 216
 217                         hose = pci_find_hose_for_OF_device(np);
 218                         max = min(max, hose->dma_window_base_cur +
 219                                         hose->dma_window_size);
 220                 }
 221         }
 222 #endif
 223
 224 #ifdef CONFIG_SMP
 225         mpc85xx_smp_init();
 226 #endif
 227
 228 #ifdef CONFIG_SWIOTLB
 229         if (lmb_end_of_DRAM() > max) {
 230                 ppc_swiotlb_enable = 1;
 231                 set_pci_dma_ops(&swiotlb_dma_ops);
 232                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
 233         }
 234 #endif
 235
 236 #ifdef CONFIG_QUICC_ENGINE
 237         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 238         if (!np) {
 239                 np = of_find_node_by_name(NULL, "qe");
 240                 if (!np)
 241                         return;
 242         }
 243
 244         if (!of_device_is_available(np)) {
 245                 of_node_put(np);
 246                 return;
 247         }
 248
 249         qe_reset();
 250         of_node_put(np);
 251
 252         np = of_find_node_by_name(NULL, "par_io");
 253         if (np) {
 254                 struct device_node *ucc;
 255
 256                 par_io_init(np);
 257                 of_node_put(np);
 258
 259                 for_each_node_by_name(ucc, "ucc")
 260                         par_io_of_config(ucc);
 261         }
 262
 263         if (bcsr_regs) {
 264                 if (machine_is(mpc8568_mds)) {
 265 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 266 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 267 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 268 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 269
 270                         /* Turn off UCC1 & UCC2 */
 271                         clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 272                         clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 273
 274                         /* Mode is RGMII, all bits clear */
 275                         clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
 276                                                  BCSR_UCC2_MODE_MSK);
 277
 278                         /* Turn UCC1 & UCC2 on */
 279                         setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 280                         setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 281                 } else if (machine_is(mpc8569_mds)) {
 282 #define BCSR7_UCC12_GETHnRST    (0x1 << 2)
 283 #define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
 284 #define BCSR_UCC_RGMII          (0x1 << 6)
 285 #define BCSR_UCC_RTBI           (0x1 << 5)
 286                         /*
 287                          * U-Boot mangles interrupt polarity for Marvell PHYs,
 288                          * so reset built-in and UEM Marvell PHYs, this puts
 289                          * the PHYs into their normal state.
 290                          */
 291                         clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 292                         setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 293
 294                         setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 295                         clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 296
 297                         for (np = NULL; (np = of_find_compatible_node(np,
 298                                                         "network",
 299                                                         "ucc_geth")) != NULL;) {
 300                                 const unsigned int *prop;
 301                                 int ucc_num;
 302
 303                                 prop = of_get_property(np, "cell-index", NULL);
 304                                 if (prop == NULL)
 305                                         continue;
 306
 307                                 ucc_num = *prop - 1;
 308
 309                                 prop = of_get_property(np, "phy-connection-type", NULL);
 310                                 if (prop == NULL)
 311                                         continue;
 312
 313                                 if (strcmp("rtbi", (const char *)prop) == 0)
 314                                         clrsetbits_8(&bcsr_regs[7 + ucc_num],
 315                                                 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
 316                         }
 317
 318                 } else if (machine_is(p1021_mds)) {
 319 #define BCSR11_ENET_MICRST     (0x1 << 5)
 320                         /* Reset Micrel PHY */
 321                         clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
 322                         setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
 323                 }
 324
 325                 iounmap(bcsr_regs);
 326         }
 327
 328         if (machine_is(p1021_mds)) {
 329 #define MPC85xx_PMUXCR_OFFSET           0x60
 330 #define MPC85xx_PMUXCR_QE0              0x00008000
 331 #define MPC85xx_PMUXCR_QE3              0x00001000
 332 #define MPC85xx_PMUXCR_QE9              0x00000040
 333 #define MPC85xx_PMUXCR_QE12             0x00000008
 334                 static __be32 __iomem *pmuxcr;
 335
 336                 np = of_find_node_by_name(NULL, "global-utilities");
 337
 338                 if (np) {
 339                         pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
 340
 341                         if (!pmuxcr)
 342                                 printk(KERN_EMERG "Error: Alternate function"
 343                                         " signal multiplex control register not"
 344                                         " mapped!\n");
 345                         else
 346                         /* P1021 has pins muxed for QE and other functions. To
 347                          * enable QE UEC mode, we need to set bit QE0 for UCC1
 348                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
 349                          * and QE12 for QE MII management singals in PMUXCR
 350                          * register.
 351                          */
 352                                 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
 353                                                   MPC85xx_PMUXCR_QE3 |
 354                                                   MPC85xx_PMUXCR_QE9 |
 355                                                   MPC85xx_PMUXCR_QE12);
 356
 357                         of_node_put(np);
 358                 }
 359
 360         }
 361 #endif  /* CONFIG_QUICC_ENGINE */
 362 }
 363
 364
 365 static int __init board_fixups(void)
 366 {
 367         char phy_id[20];
 368         char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
 369         struct device_node *mdio;
 370         struct resource res;
 371         int i;
 372
 373         for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
 374                 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
 375
 376                 of_address_to_resource(mdio, 0, &res);
 377                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 378                         (unsigned long long)res.start, 1);
 379
 380                 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
 381                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 382
 383                 /* Register a workaround for errata */
 384                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 385                         (unsigned long long)res.start, 7);
 386                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 387
 388                 of_node_put(mdio);
 389         }
 390
 391         return 0;
 392 }
 393 machine_arch_initcall(mpc8568_mds, board_fixups);
 394 machine_arch_initcall(mpc8569_mds, board_fixups);
 395
 396 static struct of_device_id mpc85xx_ids[] = {
 397         { .type = "soc", },
 398         { .compatible = "soc", },
 399         { .compatible = "simple-bus", },
 400         { .compatible = "gianfar", },
 401         { .compatible = "fsl,rapidio-delta", },
 402         { .compatible = "fsl,mpc8548-guts", },
 403         { .compatible = "gpio-leds", },
 404         {},
 405 };
 406
 407 static struct of_device_id p1021_ids[] = {
 408         { .type = "soc", },
 409         { .compatible = "soc", },
 410         { .compatible = "simple-bus", },
 411         { .compatible = "gianfar", },
 412         {},
 413 };
 414
 415 static int __init mpc85xx_publish_devices(void)
 416 {
 417         if (machine_is(mpc8568_mds))
 418                 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
 419         if (machine_is(mpc8569_mds))
 420                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 421
 422         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
 423         mpc85xx_publish_qe_devices();
 424
 425         return 0;
 426 }
 427
 428 static int __init p1021_publish_devices(void)
 429 {
 430         of_platform_bus_probe(NULL, p1021_ids, NULL);
 431         mpc85xx_publish_qe_devices();
 432
 433         return 0;
 434 }
 435
 436 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
 437 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
 438 machine_device_initcall(p1021_mds, p1021_publish_devices);
 439
 440 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
 441 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
 442 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 443
 444 static void __init mpc85xx_mds_pic_init(void)
 445 {
 446         struct mpic *mpic;
 447         struct resource r;
 448         struct device_node *np = NULL;
 449
 450         np = of_find_node_by_type(NULL, "open-pic");
 451         if (!np)
 452                 return;
 453
 454         if (of_address_to_resource(np, 0, &r)) {
 455                 printk(KERN_ERR "Failed to map mpic register space\n");
 456                 of_node_put(np);
 457                 return;
 458         }
 459
 460         mpic = mpic_alloc(np, r.start,
 461                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
 462                         MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
 463                         0, 256, " OpenPIC  ");
 464         BUG_ON(mpic == NULL);
 465         of_node_put(np);
 466
 467         mpic_init(mpic);
 468
 469 #ifdef CONFIG_QUICC_ENGINE
 470         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 471         if (!of_device_is_available(np)) {
 472                 of_node_put(np);
 473                 return;
 474         }
 475
 476         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 477         if (!np) {
 478                 np = of_find_node_by_type(NULL, "qeic");
 479                 if (!np)
 480                         return;
 481         }
 482
 483         if (machine_is(p1021_mds))
 484                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
 485                                 qe_ic_cascade_high_mpic);
 486         else
 487                 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 488         of_node_put(np);
 489 #endif                          /* CONFIG_QUICC_ENGINE */
 490 }
 491
 492 static int __init mpc85xx_mds_probe(void)
 493 {
 494         unsigned long root = of_get_flat_dt_root();
 495
 496         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 497 }
 498
 499 define_machine(mpc8568_mds) {
 500         .name           = "MPC8568 MDS",
 501         .probe          = mpc85xx_mds_probe,
 502         .setup_arch     = mpc85xx_mds_setup_arch,
 503         .init_IRQ       = mpc85xx_mds_pic_init,
 504         .get_irq        = mpic_get_irq,
 505         .restart        = fsl_rstcr_restart,
 506         .calibrate_decr = generic_calibrate_decr,
 507         .progress       = udbg_progress,
 508 #ifdef CONFIG_PCI
 509         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 510 #endif
 511 };
 512
 513 static int __init mpc8569_mds_probe(void)
 514 {
 515         unsigned long root = of_get_flat_dt_root();
 516
 517         return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
 518 }
 519
 520 define_machine(mpc8569_mds) {
 521         .name           = "MPC8569 MDS",
 522         .probe          = mpc8569_mds_probe,
 523         .setup_arch     = mpc85xx_mds_setup_arch,
 524         .init_IRQ       = mpc85xx_mds_pic_init,
 525         .get_irq        = mpic_get_irq,
 526         .restart        = fsl_rstcr_restart,
 527         .calibrate_decr = generic_calibrate_decr,
 528         .progress       = udbg_progress,
 529 #ifdef CONFIG_PCI
 530         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 531 #endif
 532 };
 533
 534 static int __init p1021_mds_probe(void)
 535 {
 536         unsigned long root = of_get_flat_dt_root();
 537
 538         return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
 539
 540 }
 541
 542 define_machine(p1021_mds) {
 543         .name           = "P1021 MDS",
 544         .probe          = p1021_mds_probe,
 545         .setup_arch     = mpc85xx_mds_setup_arch,
 546         .init_IRQ       = mpc85xx_mds_pic_init,
 547         .get_irq        = mpic_get_irq,
 548         .restart        = fsl_rstcr_restart,
 549         .calibrate_decr = generic_calibrate_decr,
 550         .progress       = udbg_progress,
 551 #ifdef CONFIG_PCI
 552         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 553 #endif
 554 };
 555