2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
4 * Author: Andy Fleming <afleming@freescale.com>
6 * Based on 83xx/mpc8360e_pb.c by:
7 * Li Yang <LeoLi@freescale.com>
8 * Yin Olivia <Hong-hua.Yin@freescale.com>
11 * MPC85xx MDS board specific routines.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/initrd.h>
31 #include <linux/fsl_devices.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_device.h>
34 #include <linux/phy.h>
35 #include <linux/memblock.h>
37 #include <asm/system.h>
38 #include <linux/atomic.h>
41 #include <asm/machdep.h>
42 #include <asm/pci-bridge.h>
44 #include <mm/mmu_decl.h>
47 #include <sysdev/fsl_soc.h>
48 #include <sysdev/fsl_pci.h>
49 #include <sysdev/simple_gpio.h>
51 #include <asm/qe_ic.h>
53 #include <asm/swiotlb.h>
60 #define DBG(fmt...) udbg_printf(fmt)
65 #define MV88E1111_SCR 0x10
66 #define MV88E1111_SCR_125CLK 0x0010
67 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
72 /* Workaround for the 125 CLK Toggle */
73 scr = phy_read(phydev, MV88E1111_SCR);
78 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
83 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
88 scr = phy_read(phydev, MV88E1111_SCR);
93 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
98 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
104 err = phy_write(phydev,29, 0x0006);
109 temp = phy_read(phydev, 30);
114 temp = (temp & (~0x8000)) | 0x4000;
115 err = phy_write(phydev,30, temp);
120 err = phy_write(phydev,29, 0x000a);
125 temp = phy_read(phydev, 30);
130 temp = phy_read(phydev, 30);
137 err = phy_write(phydev,30,temp);
142 /* Disable automatic MDI/MDIX selection */
143 temp = phy_read(phydev, 16);
149 err = phy_write(phydev,16,temp);
154 /* ************************************************************************
156 * Setup the architecture
159 #ifdef CONFIG_QUICC_ENGINE
160 static void __init mpc85xx_mds_reset_ucc_phys(void)
162 struct device_node *np;
163 static u8 __iomem *bcsr_regs;
166 np = of_find_node_by_name(NULL, "bcsr");
170 bcsr_regs = of_iomap(np, 0);
175 if (machine_is(mpc8568_mds)) {
176 #define BCSR_UCC1_GETH_EN (0x1 << 7)
177 #define BCSR_UCC2_GETH_EN (0x1 << 7)
178 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
179 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
181 /* Turn off UCC1 & UCC2 */
182 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
183 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
185 /* Mode is RGMII, all bits clear */
186 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
189 /* Turn UCC1 & UCC2 on */
190 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
191 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
192 } else if (machine_is(mpc8569_mds)) {
193 #define BCSR7_UCC12_GETHnRST (0x1 << 2)
194 #define BCSR8_UEM_MARVELL_RST (0x1 << 1)
195 #define BCSR_UCC_RGMII (0x1 << 6)
196 #define BCSR_UCC_RTBI (0x1 << 5)
198 * U-Boot mangles interrupt polarity for Marvell PHYs,
199 * so reset built-in and UEM Marvell PHYs, this puts
200 * the PHYs into their normal state.
202 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
203 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
205 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
206 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
208 for (np = NULL; (np = of_find_compatible_node(np,
210 "ucc_geth")) != NULL;) {
211 const unsigned int *prop;
214 prop = of_get_property(np, "cell-index", NULL);
220 prop = of_get_property(np, "phy-connection-type", NULL);
224 if (strcmp("rtbi", (const char *)prop) == 0)
225 clrsetbits_8(&bcsr_regs[7 + ucc_num],
226 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
228 } else if (machine_is(p1021_mds)) {
229 #define BCSR11_ENET_MICRST (0x1 << 5)
230 /* Reset Micrel PHY */
231 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
232 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
238 static void __init mpc85xx_mds_qe_init(void)
240 struct device_node *np;
242 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
244 np = of_find_node_by_name(NULL, "qe");
249 if (!of_device_is_available(np)) {
257 np = of_find_node_by_name(NULL, "par_io");
259 struct device_node *ucc;
264 for_each_node_by_name(ucc, "ucc")
265 par_io_of_config(ucc);
268 mpc85xx_mds_reset_ucc_phys();
270 if (machine_is(p1021_mds)) {
271 #define MPC85xx_PMUXCR_OFFSET 0x60
272 #define MPC85xx_PMUXCR_QE0 0x00008000
273 #define MPC85xx_PMUXCR_QE3 0x00001000
274 #define MPC85xx_PMUXCR_QE9 0x00000040
275 #define MPC85xx_PMUXCR_QE12 0x00000008
276 static __be32 __iomem *pmuxcr;
278 np = of_find_node_by_name(NULL, "global-utilities");
281 pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
284 printk(KERN_EMERG "Error: Alternate function"
285 " signal multiplex control register not"
288 /* P1021 has pins muxed for QE and other functions. To
289 * enable QE UEC mode, we need to set bit QE0 for UCC1
290 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
291 * and QE12 for QE MII management signals in PMUXCR
294 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
297 MPC85xx_PMUXCR_QE12);
305 static void __init mpc85xx_mds_qeic_init(void)
307 struct device_node *np;
309 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
310 if (!of_device_is_available(np)) {
315 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
317 np = of_find_node_by_type(NULL, "qeic");
322 if (machine_is(p1021_mds))
323 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
324 qe_ic_cascade_high_mpic);
326 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
330 static void __init mpc85xx_mds_qe_init(void) { }
331 static void __init mpc85xx_mds_qeic_init(void) { }
332 #endif /* CONFIG_QUICC_ENGINE */
334 static void __init mpc85xx_mds_setup_arch(void)
337 struct pci_controller *hose;
338 struct device_node *np;
340 dma_addr_t max = 0xffffffff;
343 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
346 for_each_node_by_type(np, "pci") {
347 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
348 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
349 struct resource rsrc;
350 of_address_to_resource(np, 0, &rsrc);
351 if ((rsrc.start & 0xfffff) == 0x8000)
352 fsl_add_bridge(np, 1);
354 fsl_add_bridge(np, 0);
356 hose = pci_find_hose_for_OF_device(np);
357 max = min(max, hose->dma_window_base_cur +
358 hose->dma_window_size);
365 mpc85xx_mds_qe_init();
367 #ifdef CONFIG_SWIOTLB
368 if (memblock_end_of_DRAM() > max) {
369 ppc_swiotlb_enable = 1;
370 set_pci_dma_ops(&swiotlb_dma_ops);
371 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
377 static int __init board_fixups(void)
380 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
381 struct device_node *mdio;
385 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
386 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
388 of_address_to_resource(mdio, 0, &res);
389 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
390 (unsigned long long)res.start, 1);
392 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
393 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
395 /* Register a workaround for errata */
396 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
397 (unsigned long long)res.start, 7);
398 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
405 machine_arch_initcall(mpc8568_mds, board_fixups);
406 machine_arch_initcall(mpc8569_mds, board_fixups);
408 static struct of_device_id mpc85xx_ids[] = {
409 { .compatible = "fsl,mpc8548-guts", },
410 { .compatible = "gpio-leds", },
414 static int __init mpc85xx_publish_devices(void)
416 if (machine_is(mpc8568_mds))
417 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
418 if (machine_is(mpc8569_mds))
419 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
421 mpc85xx_common_publish_devices();
422 of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
427 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
428 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
429 machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices);
431 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
432 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
433 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
435 static void __init mpc85xx_mds_pic_init(void)
437 struct mpic *mpic = mpic_alloc(NULL, 0,
438 MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
439 MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
440 0, 256, " OpenPIC ");
441 BUG_ON(mpic == NULL);
444 mpc85xx_mds_qeic_init();
447 static int __init mpc85xx_mds_probe(void)
449 unsigned long root = of_get_flat_dt_root();
451 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
454 define_machine(mpc8568_mds) {
455 .name = "MPC8568 MDS",
456 .probe = mpc85xx_mds_probe,
457 .setup_arch = mpc85xx_mds_setup_arch,
458 .init_IRQ = mpc85xx_mds_pic_init,
459 .get_irq = mpic_get_irq,
460 .restart = fsl_rstcr_restart,
461 .calibrate_decr = generic_calibrate_decr,
462 .progress = udbg_progress,
464 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
468 static int __init mpc8569_mds_probe(void)
470 unsigned long root = of_get_flat_dt_root();
472 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
475 define_machine(mpc8569_mds) {
476 .name = "MPC8569 MDS",
477 .probe = mpc8569_mds_probe,
478 .setup_arch = mpc85xx_mds_setup_arch,
479 .init_IRQ = mpc85xx_mds_pic_init,
480 .get_irq = mpic_get_irq,
481 .restart = fsl_rstcr_restart,
482 .calibrate_decr = generic_calibrate_decr,
483 .progress = udbg_progress,
485 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
489 static int __init p1021_mds_probe(void)
491 unsigned long root = of_get_flat_dt_root();
493 return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
497 define_machine(p1021_mds) {
499 .probe = p1021_mds_probe,
500 .setup_arch = mpc85xx_mds_setup_arch,
501 .init_IRQ = mpc85xx_mds_pic_init,
502 .get_irq = mpic_get_irq,
503 .restart = fsl_rstcr_restart,
504 .calibrate_decr = generic_calibrate_decr,
505 .progress = udbg_progress,
507 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,