2 * P1022DS board specific routines
4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
5 * Dave Liu <daveliu@freescale.com>
6 * Timur Tabi <timur@freescale.com>
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * This file is taken from the Freescale P1022DS BSP, with modifications:
12 * 3) No PCI endpoint support
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
19 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/memblock.h>
22 #include <asm/div64.h>
24 #include <asm/swiotlb.h>
26 #include <sysdev/fsl_soc.h>
27 #include <sysdev/fsl_pci.h>
28 #include <asm/fsl_guts.h>
33 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
36 * Board-specific initialization of the DIU. This code should probably be
37 * executed when the DIU is opened, rather than in arch code, but the DIU
38 * driver does not have a mechanism for this (yet).
40 * This is especially problematic on the P1022DS because the local bus (eLBC)
41 * and the DIU video signals share the same pins, which means that enabling the
42 * DIU will disable access to NOR flash.
45 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
46 #define CLKDVDR_PXCKEN 0x80000000
47 #define CLKDVDR_PXCKINV 0x10000000
48 #define CLKDVDR_PXCKDLY 0x06000000
49 #define CLKDVDR_PXCLK_MASK 0x00FF0000
51 /* Some ngPIXIS register definitions */
52 #define PX_BRDCFG1_DVIEN 0x80
53 #define PX_BRDCFG1_DFPEN 0x40
54 #define PX_BRDCFG1_BACKLIGHT 0x20
55 #define PX_BRDCFG1_DDCEN 0x10
60 * Note that we need to byte-swap the value before it's written to the AD
61 * register. So even though the registers don't look like they're in the same
62 * bit positions as they are on the MPC8610, the same value is written to the
63 * AD register on the MPC8610 and on the P1022.
65 #define AD_BYTE_F 0x10000000
66 #define AD_ALPHA_C_MASK 0x0E000000
67 #define AD_ALPHA_C_SHIFT 25
68 #define AD_BLUE_C_MASK 0x01800000
69 #define AD_BLUE_C_SHIFT 23
70 #define AD_GREEN_C_MASK 0x00600000
71 #define AD_GREEN_C_SHIFT 21
72 #define AD_RED_C_MASK 0x00180000
73 #define AD_RED_C_SHIFT 19
74 #define AD_PALETTE 0x00040000
75 #define AD_PIXEL_S_MASK 0x00030000
76 #define AD_PIXEL_S_SHIFT 16
77 #define AD_COMP_3_MASK 0x0000F000
78 #define AD_COMP_3_SHIFT 12
79 #define AD_COMP_2_MASK 0x00000F00
80 #define AD_COMP_2_SHIFT 8
81 #define AD_COMP_1_MASK 0x000000F0
82 #define AD_COMP_1_SHIFT 4
83 #define AD_COMP_0_MASK 0x0000000F
84 #define AD_COMP_0_SHIFT 0
86 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
87 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
88 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
89 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
90 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
91 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
94 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
96 * The Area Descriptor is a 32-bit value that determine which bits in each
97 * pixel are to be used for each color.
99 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
100 unsigned int bits_per_pixel)
102 switch (bits_per_pixel) {
105 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
108 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
111 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
113 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
119 * p1022ds_set_gamma_table: update the gamma table, if necessary
121 * On some boards, the gamma table for some ports may need to be modified.
122 * This is not the case on the P1022DS, so we do nothing.
124 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
125 char *gamma_table_base)
130 * p1022ds_set_monitor_port: switch the output to a different monitor port
133 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
135 struct device_node *np;
139 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
141 /* older device trees used "fsl,p1022ds-pixis" */
142 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
144 pr_err("p1022ds: missing ngPIXIS node\n");
148 pixis = of_iomap(np, 0);
150 pr_err("p1022ds: could not map ngPIXIS registers\n");
153 brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
156 case FSL_DIU_PORT_DVI:
157 printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
158 /* Enable the DVI port, disable the DFP and the backlight */
159 clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
162 case FSL_DIU_PORT_LVDS:
163 printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
164 /* Enable the DFP port, disable the DVI and the backlight */
165 clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
169 pr_err("p1022ds: unsupported monitor port %i\n", port);
176 * p1022ds_set_pixel_clock: program the DIU's clock
178 * @pixclock: the wavelength, in picoseconds, of the clock
180 void p1022ds_set_pixel_clock(unsigned int pixclock)
182 struct device_node *guts_np = NULL;
183 struct ccsr_guts_85xx __iomem *guts;
188 /* Map the global utilities registers. */
189 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
191 pr_err("p1022ds: missing global utilties device node\n");
195 guts = of_iomap(guts_np, 0);
196 of_node_put(guts_np);
198 pr_err("p1022ds: could not map global utilties device\n");
202 /* Convert pixclock from a wavelength to a frequency */
203 temp = 1000000000000ULL;
204 do_div(temp, pixclock);
208 * 'pxclk' is the ratio of the platform clock to the pixel clock.
209 * This number is programmed into the CLKDVDR register, and the valid
210 * range of values is 2-255.
212 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
213 pxclk = clamp_t(u32, pxclk, 2, 255);
215 /* Disable the pixel clock, and set it to non-inverted and no delay */
216 clrbits32(&guts->clkdvdr,
217 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
219 /* Enable the clock and set the pxclk */
220 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
226 * p1022ds_valid_monitor_port: set the monitor port for sysfs
228 enum fsl_diu_monitor_port
229 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
232 case FSL_DIU_PORT_DVI:
233 case FSL_DIU_PORT_LVDS:
236 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
242 void __init p1022_ds_pic_init(void)
244 struct mpic *mpic = mpic_alloc(NULL, 0,
246 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
247 MPIC_SINGLE_DEST_CPU,
248 0, 256, " OpenPIC ");
249 BUG_ON(mpic == NULL);
254 * Setup the architecture
256 static void __init p1022_ds_setup_arch(void)
259 struct device_node *np;
261 dma_addr_t max = 0xffffffff;
264 ppc_md.progress("p1022_ds_setup_arch()", 0);
267 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
268 struct resource rsrc;
269 struct pci_controller *hose;
271 of_address_to_resource(np, 0, &rsrc);
273 if ((rsrc.start & 0xfffff) == 0x8000)
274 fsl_add_bridge(np, 1);
276 fsl_add_bridge(np, 0);
278 hose = pci_find_hose_for_OF_device(np);
279 max = min(max, hose->dma_window_base_cur +
280 hose->dma_window_size);
284 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
285 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
286 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
287 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
288 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
289 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
294 #ifdef CONFIG_SWIOTLB
295 if (memblock_end_of_DRAM() > max) {
296 ppc_swiotlb_enable = 1;
297 set_pci_dma_ops(&swiotlb_dma_ops);
298 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
302 pr_info("Freescale P1022 DS reference board\n");
305 static struct of_device_id __initdata p1022_ds_ids[] = {
306 /* So that the DMA channel nodes can be probed individually: */
307 { .compatible = "fsl,eloplus-dma", },
311 static int __init p1022_ds_publish_devices(void)
313 mpc85xx_common_publish_devices();
314 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
316 machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
318 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
321 * Called very early, device-tree isn't unflattened
323 static int __init p1022_ds_probe(void)
325 unsigned long root = of_get_flat_dt_root();
327 return of_flat_dt_is_compatible(root, "fsl,p1022ds");
330 define_machine(p1022_ds) {
332 .probe = p1022_ds_probe,
333 .setup_arch = p1022_ds_setup_arch,
334 .init_IRQ = p1022_ds_pic_init,
336 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
338 .get_irq = mpic_get_irq,
339 .restart = fsl_rstcr_restart,
340 .calibrate_decr = generic_calibrate_decr,
341 .progress = udbg_progress,