2 * P1022DS board specific routines
4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
5 * Dave Liu <daveliu@freescale.com>
6 * Timur Tabi <timur@freescale.com>
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * This file is taken from the Freescale P1022DS BSP, with modifications:
12 * 3) No PCI endpoint support
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
19 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <asm/div64.h>
23 #include <asm/swiotlb.h>
25 #include <sysdev/fsl_soc.h>
26 #include <sysdev/fsl_pci.h>
28 #include <asm/fsl_guts.h>
29 #include <asm/fsl_lbc.h>
34 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
36 #define PMUXCR_ELBCDIU_MASK 0xc0000000
37 #define PMUXCR_ELBCDIU_NOR16 0x80000000
38 #define PMUXCR_ELBCDIU_DIU 0x40000000
41 * Board-specific initialization of the DIU. This code should probably be
42 * executed when the DIU is opened, rather than in arch code, but the DIU
43 * driver does not have a mechanism for this (yet).
45 * This is especially problematic on the P1022DS because the local bus (eLBC)
46 * and the DIU video signals share the same pins, which means that enabling the
47 * DIU will disable access to NOR flash.
50 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
51 #define CLKDVDR_PXCKEN 0x80000000
52 #define CLKDVDR_PXCKINV 0x10000000
53 #define CLKDVDR_PXCKDLY 0x06000000
54 #define CLKDVDR_PXCLK_MASK 0x00FF0000
56 /* Some ngPIXIS register definitions */
61 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
62 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
63 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
64 #define PX_BRDCFG0_ELBC_DIU 0x02
66 #define PX_BRDCFG1_DVIEN 0x80
67 #define PX_BRDCFG1_DFPEN 0x40
68 #define PX_BRDCFG1_BACKLIGHT 0x20
69 #define PX_BRDCFG1_DDCEN 0x10
71 #define PX_CTL_ALTACC 0x80
76 * Note that we need to byte-swap the value before it's written to the AD
77 * register. So even though the registers don't look like they're in the same
78 * bit positions as they are on the MPC8610, the same value is written to the
79 * AD register on the MPC8610 and on the P1022.
81 #define AD_BYTE_F 0x10000000
82 #define AD_ALPHA_C_MASK 0x0E000000
83 #define AD_ALPHA_C_SHIFT 25
84 #define AD_BLUE_C_MASK 0x01800000
85 #define AD_BLUE_C_SHIFT 23
86 #define AD_GREEN_C_MASK 0x00600000
87 #define AD_GREEN_C_SHIFT 21
88 #define AD_RED_C_MASK 0x00180000
89 #define AD_RED_C_SHIFT 19
90 #define AD_PALETTE 0x00040000
91 #define AD_PIXEL_S_MASK 0x00030000
92 #define AD_PIXEL_S_SHIFT 16
93 #define AD_COMP_3_MASK 0x0000F000
94 #define AD_COMP_3_SHIFT 12
95 #define AD_COMP_2_MASK 0x00000F00
96 #define AD_COMP_2_SHIFT 8
97 #define AD_COMP_1_MASK 0x000000F0
98 #define AD_COMP_1_SHIFT 4
99 #define AD_COMP_0_MASK 0x0000000F
100 #define AD_COMP_0_SHIFT 0
102 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
103 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
104 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
105 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
106 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
107 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
110 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
112 * The Area Descriptor is a 32-bit value that determine which bits in each
113 * pixel are to be used for each color.
115 static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
116 unsigned int bits_per_pixel)
118 switch (bits_per_pixel) {
121 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
124 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
127 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
129 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
135 * p1022ds_set_gamma_table: update the gamma table, if necessary
137 * On some boards, the gamma table for some ports may need to be modified.
138 * This is not the case on the P1022DS, so we do nothing.
140 static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
141 char *gamma_table_base)
152 #define LAWBAR_MASK 0x00F00000
153 #define LAWBAR_SHIFT 12
155 #define LAWAR_EN 0x80000000
156 #define LAWAR_TGT_MASK 0x01F00000
157 #define LAW_TRGT_IF_LBC (0x04 << 20)
159 #define LAWAR_MASK (LAWAR_EN | LAWAR_TGT_MASK)
160 #define LAWAR_MATCH (LAWAR_EN | LAW_TRGT_IF_LBC)
162 #define BR_BA 0xFFFF8000
165 * Map a BRx value to a physical address
167 * The localbus BRx registers only store the lower 32 bits of the address. To
168 * obtain the upper four bits, we need to scan the LAW table. The entry which
169 * maps to the localbus will contain the upper four bits.
171 static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
173 #ifndef CONFIG_PHYS_64BIT
175 * If we only have 32-bit addressing, then the BRx address *is* the
180 const struct fsl_law *law = ecm + 0xc08;
183 for (i = 0; i < count; i++) {
184 u64 lawbar = in_be32(&law[i].lawbar);
185 u32 lawar = in_be32(&law[i].lawar);
187 if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
188 /* Extract the upper four bits */
189 return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
197 * p1022ds_set_monitor_port: switch the output to a different monitor port
199 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
201 struct device_node *guts_node;
202 struct device_node *lbc_node = NULL;
203 struct device_node *law_node = NULL;
204 struct ccsr_guts __iomem *guts;
205 struct fsl_lbc_regs *lbc = NULL;
207 u8 __iomem *lbc_lcs0_ba = NULL;
208 u8 __iomem *lbc_lcs1_ba = NULL;
209 phys_addr_t cs0_addr, cs1_addr;
210 u32 br0, or0, br1, or1;
212 unsigned int num_laws;
215 /* Map the global utilities registers. */
216 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
218 pr_err("p1022ds: missing global utilties device node\n");
222 guts = of_iomap(guts_node, 0);
224 pr_err("p1022ds: could not map global utilties device\n");
228 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
230 pr_err("p1022ds: missing localbus node\n");
234 lbc = of_iomap(lbc_node, 0);
236 pr_err("p1022ds: could not map localbus node\n");
240 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
242 pr_err("p1022ds: missing local access window node\n");
246 ecm = of_iomap(law_node, 0);
248 pr_err("p1022ds: could not map local access window node\n");
252 iprop = of_get_property(law_node, "fsl,num-laws", 0);
254 pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
257 num_laws = be32_to_cpup(iprop);
260 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
261 * otherwise writes to these addresses won't actually appear on the
262 * local bus, and so the PIXIS won't see them.
264 * In FCM mode, writes go to the NAND controller, which does not pass
265 * them to the localbus directly. So we force BR0 and BR1 into GPCM
266 * mode, since we don't care about what's behind the localbus any
269 br0 = in_be32(&lbc->bank[0].br);
270 br1 = in_be32(&lbc->bank[1].br);
271 or0 = in_be32(&lbc->bank[0].or);
272 or1 = in_be32(&lbc->bank[1].or);
274 /* Make sure CS0 and CS1 are programmed */
275 if (!(br0 & BR_V) || !(br1 & BR_V)) {
276 pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
281 * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
282 * force the values to simple 32KB GPCM windows with the most
283 * conservative timing.
285 if ((br0 & BR_MSEL) != BR_MS_GPCM) {
286 br0 = (br0 & BR_BA) | BR_V;
287 or0 = 0xFFFF8000 | 0xFF7;
288 out_be32(&lbc->bank[0].br, br0);
289 out_be32(&lbc->bank[0].or, or0);
291 if ((br1 & BR_MSEL) != BR_MS_GPCM) {
292 br1 = (br1 & BR_BA) | BR_V;
293 or1 = 0xFFFF8000 | 0xFF7;
294 out_be32(&lbc->bank[1].br, br1);
295 out_be32(&lbc->bank[1].or, or1);
298 cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
300 pr_err("p1022ds: could not determine physical address for CS0"
301 " (BR0=%08x)\n", br0);
304 cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
306 pr_err("p1022ds: could not determine physical address for CS1"
307 " (BR1=%08x)\n", br1);
311 lbc_lcs0_ba = ioremap(cs0_addr, 1);
313 pr_err("p1022ds: could not ioremap CS0 address %llx\n",
314 (unsigned long long)cs0_addr);
317 lbc_lcs1_ba = ioremap(cs1_addr, 1);
319 pr_err("p1022ds: could not ioremap CS1 address %llx\n",
320 (unsigned long long)cs1_addr);
324 /* Make sure we're in indirect mode first. */
325 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
326 PMUXCR_ELBCDIU_DIU) {
327 struct device_node *pixis_node;
331 of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
333 pr_err("p1022ds: missing pixis node\n");
337 pixis = of_iomap(pixis_node, 0);
338 of_node_put(pixis_node);
340 pr_err("p1022ds: could not map pixis registers\n");
344 /* Enable indirect PIXIS mode. */
345 setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
348 /* Switch the board mux to the DIU */
349 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
350 b = in_8(lbc_lcs1_ba);
351 b |= PX_BRDCFG0_ELBC_DIU;
352 out_8(lbc_lcs1_ba, b);
354 /* Set the chip mux to DIU mode. */
355 clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
357 in_be32(&guts->pmuxcr);
362 case FSL_DIU_PORT_DVI:
363 /* Enable the DVI port, disable the DFP and the backlight */
364 out_8(lbc_lcs0_ba, PX_BRDCFG1);
365 b = in_8(lbc_lcs1_ba);
366 b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
367 b |= PX_BRDCFG1_DVIEN;
368 out_8(lbc_lcs1_ba, b);
370 case FSL_DIU_PORT_LVDS:
372 * LVDS also needs backlight enabled, otherwise the display
375 /* Enable the DFP port, disable the DVI and the backlight */
376 out_8(lbc_lcs0_ba, PX_BRDCFG1);
377 b = in_8(lbc_lcs1_ba);
378 b &= ~PX_BRDCFG1_DVIEN;
379 b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
380 out_8(lbc_lcs1_ba, b);
383 pr_err("p1022ds: unsupported monitor port %i\n", port);
388 iounmap(lbc_lcs1_ba);
390 iounmap(lbc_lcs0_ba);
398 of_node_put(law_node);
399 of_node_put(lbc_node);
400 of_node_put(guts_node);
404 * p1022ds_set_pixel_clock: program the DIU's clock
406 * @pixclock: the wavelength, in picoseconds, of the clock
408 void p1022ds_set_pixel_clock(unsigned int pixclock)
410 struct device_node *guts_np = NULL;
411 struct ccsr_guts __iomem *guts;
416 /* Map the global utilities registers. */
417 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
419 pr_err("p1022ds: missing global utilties device node\n");
423 guts = of_iomap(guts_np, 0);
424 of_node_put(guts_np);
426 pr_err("p1022ds: could not map global utilties device\n");
430 /* Convert pixclock from a wavelength to a frequency */
431 temp = 1000000000000ULL;
432 do_div(temp, pixclock);
436 * 'pxclk' is the ratio of the platform clock to the pixel clock.
437 * This number is programmed into the CLKDVDR register, and the valid
438 * range of values is 2-255.
440 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
441 pxclk = clamp_t(u32, pxclk, 2, 255);
443 /* Disable the pixel clock, and set it to non-inverted and no delay */
444 clrbits32(&guts->clkdvdr,
445 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
447 /* Enable the clock and set the pxclk */
448 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
454 * p1022ds_valid_monitor_port: set the monitor port for sysfs
456 enum fsl_diu_monitor_port
457 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
460 case FSL_DIU_PORT_DVI:
461 case FSL_DIU_PORT_LVDS:
464 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
470 void __init p1022_ds_pic_init(void)
472 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
473 MPIC_SINGLE_DEST_CPU,
474 0, 256, " OpenPIC ");
475 BUG_ON(mpic == NULL);
479 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
481 /* TRUE if there is a "video=fslfb" command-line parameter. */
485 * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
486 * true if we find it.
488 * We need to use early_param() instead of __setup() because the normal
489 * __setup() gets called to late. However, early_param() gets called very
490 * early, before the device tree is unflattened, so all we can do now is set a
491 * global variable. Later on, p1022_ds_setup_arch() will use that variable
492 * to determine if we need to update the device tree.
494 static int __init early_video_setup(char *options)
496 fslfb = (strncmp(options, "fslfb:", 6) == 0);
500 early_param("video", early_video_setup);
505 * Setup the architecture
507 static void __init p1022_ds_setup_arch(void)
510 ppc_md.progress("p1022_ds_setup_arch()", 0);
512 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
513 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
514 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
515 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
516 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
517 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
520 * Disable the NOR and NAND flash nodes if there is video=fslfb...
521 * command-line parameter. When the DIU is active, the localbus is
522 * unavailable, so we have to disable these nodes before the MTD
526 struct device_node *np =
527 of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
530 struct device_node *np2;
533 np2 = of_find_compatible_node(np, NULL, "cfi-flash");
535 static struct property nor_status = {
538 .length = sizeof("disabled"),
542 * prom_update_property() is called before
543 * kmalloc() is available, so the 'new' object
544 * should be allocated in the global area.
545 * The easiest way is to do that is to
546 * allocate one static local variable for each
547 * call to this function.
549 pr_info("p1022ds: disabling %s node",
551 prom_update_property(np2, &nor_status);
556 np2 = of_find_compatible_node(np, NULL,
557 "fsl,elbc-fcm-nand");
559 static struct property nand_status = {
562 .length = sizeof("disabled"),
565 pr_info("p1022ds: disabling %s node",
567 prom_update_property(np2, &nand_status);
580 fsl_pci_assign_primary();
584 pr_info("Freescale P1022 DS reference board\n");
587 machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
589 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
592 * Called very early, device-tree isn't unflattened
594 static int __init p1022_ds_probe(void)
596 unsigned long root = of_get_flat_dt_root();
598 return of_flat_dt_is_compatible(root, "fsl,p1022ds");
601 define_machine(p1022_ds) {
603 .probe = p1022_ds_probe,
604 .setup_arch = p1022_ds_setup_arch,
605 .init_IRQ = p1022_ds_pic_init,
607 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
609 .get_irq = mpic_get_irq,
610 .restart = fsl_rstcr_restart,
611 .calibrate_decr = generic_calibrate_decr,
612 .progress = udbg_progress,