2 * Author: Andy Fleming <afleming@freescale.com>
3 * Kumar Gala <galak@kernel.crashing.org>
5 * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/of_address.h>
19 #include <linux/kexec.h>
20 #include <linux/highmem.h>
21 #include <linux/cpu.h>
23 #include <asm/machdep.h>
24 #include <asm/pgtable.h>
27 #include <asm/cacheflush.h>
28 #include <asm/dbell.h>
29 #include <asm/fsl_guts.h>
30 #include <asm/code-patching.h>
31 #include <asm/cputhreads.h>
33 #include <sysdev/fsl_soc.h>
34 #include <sysdev/mpic.h>
37 struct epapr_spin_table {
46 static struct ccsr_guts __iomem *guts;
51 static void mpc85xx_timebase_freeze(int freeze)
55 mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
57 setbits32(&guts->devdisr, mask);
59 clrbits32(&guts->devdisr, mask);
61 in_be32(&guts->devdisr);
64 static void mpc85xx_give_timebase(void)
68 local_irq_save(flags);
74 mpc85xx_timebase_freeze(1);
77 * e5500/e6500 have a workaround for erratum A-006958 in place
78 * that will reread the timebase until TBL is non-zero.
79 * That would be a bad thing when the timebase is frozen.
81 * Thus, we read it manually, and instead of checking that
82 * TBL is non-zero, we ensure that TB does not change. We don't
83 * do that for the main mftb implementation, because it requires
89 asm volatile("mfspr %0, %1" : "=r" (timebase) :
94 asm volatile("mfspr %0, %1" : "=r" (timebase) :
96 } while (prev != timebase);
107 mpc85xx_timebase_freeze(0);
109 local_irq_restore(flags);
112 static void mpc85xx_take_timebase(void)
116 local_irq_save(flags);
122 set_tb(timebase >> 32, timebase & 0xffffffff);
126 local_irq_restore(flags);
129 #ifdef CONFIG_HOTPLUG_CPU
130 static void smp_85xx_mach_cpu_die(void)
132 unsigned int cpu = smp_processor_id();
137 generic_set_cpu_dead(cpu);
142 __flush_disable_L1();
143 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
144 mtspr(SPRN_HID0, tmp);
147 /* Enter NAP mode. */
159 static inline void flush_spin_table(void *spin_table)
161 flush_dcache_range((ulong)spin_table,
162 (ulong)spin_table + sizeof(struct epapr_spin_table));
165 static inline u32 read_spin_table_addr_l(void *spin_table)
167 flush_dcache_range((ulong)spin_table,
168 (ulong)spin_table + sizeof(struct epapr_spin_table));
169 return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
173 static void wake_hw_thread(void *info)
175 void fsl_secondary_thread_init(void);
176 unsigned long imsr1, inia1;
177 int nr = *(const int *)info;
180 inia1 = *(unsigned long *)fsl_secondary_thread_init;
182 mttmr(TMRN_IMSR1, imsr1);
183 mttmr(TMRN_INIA1, inia1);
184 mtspr(SPRN_TENS, TEN_THREAD(1));
186 smp_generic_kick_cpu(nr);
190 static int smp_85xx_kick_cpu(int nr)
193 const u64 *cpu_rel_addr;
194 __iomem struct epapr_spin_table *spin_table;
195 struct device_node *np;
196 int hw_cpu = get_hard_smp_processor_id(nr);
200 WARN_ON(nr < 0 || nr >= NR_CPUS);
201 WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
203 pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
206 /* Threads don't use the spin table */
207 if (cpu_thread_in_core(nr) != 0) {
208 int primary = cpu_first_thread_sibling(nr);
210 if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
213 if (cpu_thread_in_core(nr) != 1) {
214 pr_err("%s: cpu %d: invalid hw thread %d\n",
215 __func__, nr, cpu_thread_in_core(nr));
219 if (!cpu_online(primary)) {
220 pr_err("%s: cpu %d: primary %d not online\n",
221 __func__, nr, primary);
225 smp_call_function_single(primary, wake_hw_thread, &nr, 0);
230 np = of_get_cpu_node(nr, NULL);
231 cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
233 if (cpu_rel_addr == NULL) {
234 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
239 * A secondary core could be in a spinloop in the bootpage
240 * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
241 * The bootpage and highmem can be accessed via ioremap(), but
242 * we need to directly access the spinloop if its in lowmem.
244 ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
246 /* Map the spin table */
248 spin_table = ioremap_prot(*cpu_rel_addr,
249 sizeof(struct epapr_spin_table), _PAGE_COHERENT);
251 spin_table = phys_to_virt(*cpu_rel_addr);
253 local_irq_save(flags);
255 #ifdef CONFIG_HOTPLUG_CPU
256 /* Corresponding to generic_set_cpu_dead() */
257 generic_set_cpu_up(nr);
259 if (system_state == SYSTEM_RUNNING) {
261 * To keep it compatible with old boot program which uses
262 * cache-inhibit spin table, we need to flush the cache
263 * before accessing spin table to invalidate any staled data.
264 * We also need to flush the cache after writing to spin
265 * table to push data out.
267 flush_spin_table(spin_table);
268 out_be32(&spin_table->addr_l, 0);
269 flush_spin_table(spin_table);
272 * We don't set the BPTR register here since it already points
273 * to the boot page properly.
278 * wait until core is ready...
279 * We need to invalidate the stale data, in case the boot
280 * loader uses a cache-inhibited spin table.
282 if (!spin_event_timeout(
283 read_spin_table_addr_l(spin_table) == 1,
285 pr_err("%s: timeout waiting for core %d to reset\n",
291 /* clear the acknowledge status */
292 __secondary_hold_acknowledge = -1;
295 flush_spin_table(spin_table);
296 out_be32(&spin_table->pir, hw_cpu);
297 out_be32(&spin_table->addr_l, __pa(__early_start));
298 flush_spin_table(spin_table);
300 /* Wait a bit for the CPU to ack. */
301 if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
303 pr_err("%s: timeout waiting for core %d to ack\n",
310 smp_generic_kick_cpu(nr);
312 flush_spin_table(spin_table);
313 out_be32(&spin_table->pir, hw_cpu);
314 out_be64((u64 *)(&spin_table->addr_h),
315 __pa(ppc_function_entry(generic_secondary_smp_init)));
316 flush_spin_table(spin_table);
319 local_irq_restore(flags);
327 struct smp_ops_t smp_85xx_ops = {
328 .kick_cpu = smp_85xx_kick_cpu,
329 .cpu_bootable = smp_generic_cpu_bootable,
330 #ifdef CONFIG_HOTPLUG_CPU
331 .cpu_disable = generic_cpu_disable,
332 .cpu_die = generic_cpu_die,
335 .give_timebase = smp_generic_give_timebase,
336 .take_timebase = smp_generic_take_timebase,
341 atomic_t kexec_down_cpus = ATOMIC_INIT(0);
343 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
348 __flush_disable_L1();
349 atomic_inc(&kexec_down_cpus);
355 static void mpc85xx_smp_kexec_down(void *arg)
357 if (ppc_md.kexec_cpu_down)
358 ppc_md.kexec_cpu_down(0,1);
361 static void mpc85xx_smp_machine_kexec(struct kimage *image)
363 int timeout = INT_MAX;
364 int i, num_cpus = num_present_cpus();
366 if (image->type == KEXEC_TYPE_DEFAULT)
367 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
369 while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
376 printk(KERN_ERR "Unable to bring down secondary cpu(s)");
378 for_each_online_cpu(i)
380 if ( i == smp_processor_id() ) continue;
384 default_machine_kexec(image);
386 #endif /* CONFIG_KEXEC */
388 static void smp_85xx_basic_setup(int cpu_nr)
390 if (cpu_has_feature(CPU_FTR_DBELL))
391 doorbell_setup_this_cpu();
394 static void smp_85xx_setup_cpu(int cpu_nr)
396 mpic_setup_this_cpu();
397 smp_85xx_basic_setup(cpu_nr);
400 static const struct of_device_id mpc85xx_smp_guts_ids[] = {
401 { .compatible = "fsl,mpc8572-guts", },
402 { .compatible = "fsl,p1020-guts", },
403 { .compatible = "fsl,p1021-guts", },
404 { .compatible = "fsl,p1022-guts", },
405 { .compatible = "fsl,p1023-guts", },
406 { .compatible = "fsl,p2020-guts", },
410 void __init mpc85xx_smp_init(void)
412 struct device_node *np;
415 np = of_find_node_by_type(NULL, "open-pic");
417 smp_85xx_ops.probe = smp_mpic_probe;
418 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
419 smp_85xx_ops.message_pass = smp_mpic_message_pass;
421 smp_85xx_ops.setup_cpu = smp_85xx_basic_setup;
423 if (cpu_has_feature(CPU_FTR_DBELL)) {
425 * If left NULL, .message_pass defaults to
426 * smp_muxed_ipi_message_pass
428 smp_85xx_ops.message_pass = NULL;
429 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
430 smp_85xx_ops.probe = NULL;
433 np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
435 guts = of_iomap(np, 0);
438 pr_err("%s: Could not map guts node address\n",
442 smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
443 smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
444 #ifdef CONFIG_HOTPLUG_CPU
445 ppc_md.cpu_die = smp_85xx_mach_cpu_die;
449 smp_ops = &smp_85xx_ops;
452 ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
453 ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;