arch/powerpc/platforms/85xx/xes_mpc85xx.c

   1 /*
   2  * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
   3  *
   4  * X-ES board-specific functionality
   5  *
   6  * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
   7  *
   8  * Author: Nate Case <ncase@xes-inc.com>
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of_platform.h>
  23
  24 #include <asm/system.h>
  25 #include <asm/time.h>
  26 #include <asm/machdep.h>
  27 #include <asm/pci-bridge.h>
  28 #include <mm/mmu_decl.h>
  29 #include <asm/prom.h>
  30 #include <asm/udbg.h>
  31 #include <asm/mpic.h>
  32
  33 #include <sysdev/fsl_soc.h>
  34 #include <sysdev/fsl_pci.h>
  35 #include "smp.h"
  36
  37 #include "mpc85xx.h"
  38
  39 /* A few bit definitions needed for fixups on some boards */
  40 #define MPC85xx_L2CTL_L2E               0x80000000 /* L2 enable */
  41 #define MPC85xx_L2CTL_L2I               0x40000000 /* L2 flash invalidate */
  42 #define MPC85xx_L2CTL_L2SIZ_MASK        0x30000000 /* L2 SRAM size (R/O) */
  43
  44 void __init xes_mpc85xx_pic_init(void)
  45 {
  46         struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
  47                         0, 256, " OpenPIC  ");
  48         BUG_ON(mpic == NULL);
  49         mpic_init(mpic);
  50 }
  51
  52 static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
  53 {
  54         volatile uint32_t ctl, tmp;
  55
  56         asm volatile("msync; isync");
  57         tmp = in_be32(l2_base);
  58
  59         /*
  60          * xMon may have enabled part of L2 as SRAM, so we need to set it
  61          * up for all cache mode just to be safe.
  62          */
  63         printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
  64
  65         ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
  66         if (of_machine_is_compatible("MPC8540") ||
  67             of_machine_is_compatible("MPC8560"))
  68                 /*
  69                  * Assume L2 SRAM is used fully for cache, so set
  70                  * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
  71                  */
  72                 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
  73
  74         asm volatile("msync; isync");
  75         out_be32(l2_base, ctl);
  76         asm volatile("msync; isync");
  77 }
  78
  79 static void xes_mpc85xx_fixups(void)
  80 {
  81         struct device_node *np;
  82         int err;
  83
  84         /*
  85          * Legacy xMon firmware on some X-ES boards does not enable L2
  86          * as cache.  We must ensure that they get enabled here.
  87          */
  88         for_each_node_by_name(np, "l2-cache-controller") {
  89                 struct resource r[2];
  90                 void __iomem *l2_base;
  91
  92                 /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
  93                 if (!of_device_is_compatible(np,
  94                                     "fsl,mpc8548-l2-cache-controller") &&
  95                     !of_device_is_compatible(np,
  96                                     "fsl,mpc8540-l2-cache-controller") &&
  97                     !of_device_is_compatible(np,
  98                                     "fsl,mpc8560-l2-cache-controller"))
  99                         continue;
 100
 101                 err = of_address_to_resource(np, 0, &r[0]);
 102                 if (err) {
 103                         printk(KERN_WARNING "xes_mpc85xx: Could not get "
 104                                "resource for device tree node '%s'",
 105                                np->full_name);
 106                         continue;
 107                 }
 108
 109                 l2_base = ioremap(r[0].start, resource_size(&r[0]));
 110
 111                 xes_mpc85xx_configure_l2(l2_base);
 112         }
 113 }
 114
 115 #ifdef CONFIG_PCI
 116 static int primary_phb_addr;
 117 #endif
 118
 119 /*
 120  * Setup the architecture
 121  */
 122 static void __init xes_mpc85xx_setup_arch(void)
 123 {
 124 #ifdef CONFIG_PCI
 125         struct device_node *np;
 126 #endif
 127         struct device_node *root;
 128         const char *model = "Unknown";
 129
 130         root = of_find_node_by_path("/");
 131         if (root == NULL)
 132                 return;
 133
 134         model = of_get_property(root, "model", NULL);
 135
 136         printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
 137                model + strlen("xes,"));
 138
 139         xes_mpc85xx_fixups();
 140
 141 #ifdef CONFIG_PCI
 142         for_each_node_by_type(np, "pci") {
 143                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 144                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 145                         struct resource rsrc;
 146                         of_address_to_resource(np, 0, &rsrc);
 147                         if ((rsrc.start & 0xfffff) == primary_phb_addr)
 148                                 fsl_add_bridge(np, 1);
 149                         else
 150                                 fsl_add_bridge(np, 0);
 151                 }
 152         }
 153 #endif
 154
 155         mpc85xx_smp_init();
 156 }
 157
 158 machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
 159 machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
 160 machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
 161
 162 /*
 163  * Called very early, device-tree isn't unflattened
 164  */
 165 static int __init xes_mpc8572_probe(void)
 166 {
 167         unsigned long root = of_get_flat_dt_root();
 168
 169         if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
 170 #ifdef CONFIG_PCI
 171                 primary_phb_addr = 0x8000;
 172 #endif
 173                 return 1;
 174         } else {
 175                 return 0;
 176         }
 177 }
 178
 179 static int __init xes_mpc8548_probe(void)
 180 {
 181         unsigned long root = of_get_flat_dt_root();
 182
 183         if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
 184 #ifdef CONFIG_PCI
 185                 primary_phb_addr = 0xb000;
 186 #endif
 187                 return 1;
 188         } else {
 189                 return 0;
 190         }
 191 }
 192
 193 static int __init xes_mpc8540_probe(void)
 194 {
 195         unsigned long root = of_get_flat_dt_root();
 196
 197         if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
 198 #ifdef CONFIG_PCI
 199                 primary_phb_addr = 0xb000;
 200 #endif
 201                 return 1;
 202         } else {
 203                 return 0;
 204         }
 205 }
 206
 207 define_machine(xes_mpc8572) {
 208         .name                   = "X-ES MPC8572",
 209         .probe                  = xes_mpc8572_probe,
 210         .setup_arch             = xes_mpc85xx_setup_arch,
 211         .init_IRQ               = xes_mpc85xx_pic_init,
 212 #ifdef CONFIG_PCI
 213         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 214 #endif
 215         .get_irq                = mpic_get_irq,
 216         .restart                = fsl_rstcr_restart,
 217         .calibrate_decr         = generic_calibrate_decr,
 218         .progress               = udbg_progress,
 219 };
 220
 221 define_machine(xes_mpc8548) {
 222         .name                   = "X-ES MPC8548",
 223         .probe                  = xes_mpc8548_probe,
 224         .setup_arch             = xes_mpc85xx_setup_arch,
 225         .init_IRQ               = xes_mpc85xx_pic_init,
 226 #ifdef CONFIG_PCI
 227         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 228 #endif
 229         .get_irq                = mpic_get_irq,
 230         .restart                = fsl_rstcr_restart,
 231         .calibrate_decr         = generic_calibrate_decr,
 232         .progress               = udbg_progress,
 233 };
 234
 235 define_machine(xes_mpc8540) {
 236         .name                   = "X-ES MPC8540",
 237         .probe                  = xes_mpc8540_probe,
 238         .setup_arch             = xes_mpc85xx_setup_arch,
 239         .init_IRQ               = xes_mpc85xx_pic_init,
 240 #ifdef CONFIG_PCI
 241         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 242 #endif
 243         .get_irq                = mpic_get_irq,
 244         .restart                = fsl_rstcr_restart,
 245         .calibrate_decr         = generic_calibrate_decr,
 246         .progress               = udbg_progress,
 247 };