2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/iommu.h>
26 #include <asm/ppc-pci.h>
31 #define DBG(x...) printk(x)
36 static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;
38 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
40 for (; node != 0;node = node->sibling) {
42 const unsigned int *class_code;
45 /* For PCI<->PCI bridges or CardBus bridges, we go down */
46 class_code = of_get_property(node, "class-code", NULL);
47 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
48 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
50 bus_range = of_get_property(node, "bus-range", &len);
51 if (bus_range != NULL && len > 2 * sizeof(int)) {
52 if (bus_range[1] > higher)
53 higher = bus_range[1];
55 higher = fixup_one_level_bus_range(node->child, higher);
60 /* This routine fixes the "bus-range" property of all bridges in the
61 * system since they tend to have their "last" member wrong on macs
63 * Note that the bus numbers manipulated here are OF bus numbers, they
64 * are not Linux bus numbers.
66 static void __init fixup_bus_range(struct device_node *bridge)
69 struct property *prop;
72 /* Lookup the "bus-range" property for the hose */
73 prop = of_find_property(bridge, "bus-range", &len);
74 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) {
75 printk(KERN_WARNING "Can't get bus-range for %s\n",
79 bus_range = prop->value;
80 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
84 static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
86 return (1 << (unsigned long)PCI_SLOT(devfn)) |
87 ((unsigned long)PCI_FUNC(devfn) << 8) |
88 ((unsigned long)off & 0xFCUL);
91 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
93 return ((unsigned long)bus << 16) |
94 ((unsigned long)devfn << 8) |
95 ((unsigned long)off & 0xFCUL) |
99 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
100 u8 bus, u8 dev_fn, u8 offset)
104 if (bus == hose->first_busno) {
105 if (dev_fn < (11 << 3))
107 caddr = u3_agp_cfa0(dev_fn, offset);
109 caddr = u3_agp_cfa1(bus, dev_fn, offset);
111 /* Uninorth will return garbage if we don't read back the value ! */
113 out_le32(hose->cfg_addr, caddr);
114 } while (in_le32(hose->cfg_addr) != caddr);
117 return hose->cfg_data + offset;
120 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
121 int offset, int len, u32 *val)
123 struct pci_controller *hose;
124 volatile void __iomem *addr;
126 hose = pci_bus_to_host(bus);
128 return PCIBIOS_DEVICE_NOT_FOUND;
130 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
132 return PCIBIOS_DEVICE_NOT_FOUND;
134 * Note: the caller has already checked that offset is
135 * suitably aligned and that len is 1, 2 or 4.
142 *val = in_le16(addr);
145 *val = in_le32(addr);
148 return PCIBIOS_SUCCESSFUL;
151 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
152 int offset, int len, u32 val)
154 struct pci_controller *hose;
155 volatile void __iomem *addr;
157 hose = pci_bus_to_host(bus);
159 return PCIBIOS_DEVICE_NOT_FOUND;
161 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
163 return PCIBIOS_DEVICE_NOT_FOUND;
165 * Note: the caller has already checked that offset is
166 * suitably aligned and that len is 1, 2 or 4.
179 return PCIBIOS_SUCCESSFUL;
182 static struct pci_ops u3_agp_pci_ops =
184 .read = u3_agp_read_config,
185 .write = u3_agp_write_config,
188 static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
190 return (devfn << 8) | off;
193 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
195 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
198 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
199 u8 bus, u8 devfn, u8 offset)
201 if (bus == hose->first_busno) {
202 if (PCI_SLOT(devfn) == 0)
204 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
206 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
209 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
212 volatile void __iomem *addr;
214 addr = hose->cfg_addr;
215 addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
222 *val = in_be16(addr);
225 *val = in_be32(addr);
229 return PCIBIOS_SUCCESSFUL;
232 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
235 volatile void __iomem *addr;
237 addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
239 if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
240 return PCIBIOS_SUCCESSFUL;
254 return PCIBIOS_SUCCESSFUL;
257 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
258 int offset, int len, u32 *val)
260 struct pci_controller *hose;
261 volatile void __iomem *addr;
263 hose = pci_bus_to_host(bus);
265 return PCIBIOS_DEVICE_NOT_FOUND;
267 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
268 return u3_ht_root_read_config(hose, offset, len, val);
271 return PCIBIOS_BAD_REGISTER_NUMBER;
273 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
275 return PCIBIOS_DEVICE_NOT_FOUND;
278 * Note: the caller has already checked that offset is
279 * suitably aligned and that len is 1, 2 or 4.
286 *val = in_le16(addr);
289 *val = in_le32(addr);
292 return PCIBIOS_SUCCESSFUL;
295 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
296 int offset, int len, u32 val)
298 struct pci_controller *hose;
299 volatile void __iomem *addr;
301 hose = pci_bus_to_host(bus);
303 return PCIBIOS_DEVICE_NOT_FOUND;
305 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
306 return u3_ht_root_write_config(hose, offset, len, val);
309 return PCIBIOS_BAD_REGISTER_NUMBER;
311 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
313 return PCIBIOS_DEVICE_NOT_FOUND;
315 * Note: the caller has already checked that offset is
316 * suitably aligned and that len is 1, 2 or 4.
329 return PCIBIOS_SUCCESSFUL;
332 static struct pci_ops u3_ht_pci_ops =
334 .read = u3_ht_read_config,
335 .write = u3_ht_write_config,
338 static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
340 return (1 << PCI_SLOT(devfn)) |
341 (PCI_FUNC(devfn) << 8) |
346 static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
355 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
356 u8 bus, u8 dev_fn, int offset)
360 if (bus == hose->first_busno)
361 caddr = u4_pcie_cfa0(dev_fn, offset);
363 caddr = u4_pcie_cfa1(bus, dev_fn, offset);
365 /* Uninorth will return garbage if we don't read back the value ! */
367 out_le32(hose->cfg_addr, caddr);
368 } while (in_le32(hose->cfg_addr) != caddr);
371 return hose->cfg_data + offset;
374 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
375 int offset, int len, u32 *val)
377 struct pci_controller *hose;
378 volatile void __iomem *addr;
380 hose = pci_bus_to_host(bus);
382 return PCIBIOS_DEVICE_NOT_FOUND;
383 if (offset >= 0x1000)
384 return PCIBIOS_BAD_REGISTER_NUMBER;
385 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
387 return PCIBIOS_DEVICE_NOT_FOUND;
389 * Note: the caller has already checked that offset is
390 * suitably aligned and that len is 1, 2 or 4.
397 *val = in_le16(addr);
400 *val = in_le32(addr);
403 return PCIBIOS_SUCCESSFUL;
405 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
406 int offset, int len, u32 val)
408 struct pci_controller *hose;
409 volatile void __iomem *addr;
411 hose = pci_bus_to_host(bus);
413 return PCIBIOS_DEVICE_NOT_FOUND;
414 if (offset >= 0x1000)
415 return PCIBIOS_BAD_REGISTER_NUMBER;
416 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
418 return PCIBIOS_DEVICE_NOT_FOUND;
420 * Note: the caller has already checked that offset is
421 * suitably aligned and that len is 1, 2 or 4.
434 return PCIBIOS_SUCCESSFUL;
437 static struct pci_ops u4_pcie_pci_ops =
439 .read = u4_pcie_read_config,
440 .write = u4_pcie_write_config,
443 static void __init setup_u3_agp(struct pci_controller* hose)
445 /* On G5, we move AGP up to high bus number so we don't need
446 * to reassign bus numbers for HT. If we ever have P2P bridges
447 * on AGP, we'll have to move pci_assign_all_buses to the
448 * pci_controller structure so we enable it for AGP and not for
450 * We hard code the address because of the different size of
451 * the reg address cell, we shall fix that by killing struct
452 * reg_property and using some accessor functions instead
454 hose->first_busno = 0xf0;
455 hose->last_busno = 0xff;
456 hose->ops = &u3_agp_pci_ops;
457 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
458 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
463 static void __init setup_u4_pcie(struct pci_controller* hose)
465 /* We currently only implement the "non-atomic" config space, to
466 * be optimised later.
468 hose->ops = &u4_pcie_pci_ops;
469 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
470 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
475 static void __init setup_u3_ht(struct pci_controller* hose)
477 hose->ops = &u3_ht_pci_ops;
479 /* We hard code the address because of the different size of
480 * the reg address cell, we shall fix that by killing struct
481 * reg_property and using some accessor functions instead
483 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
484 hose->cfg_addr = ioremap(0xf8070000, 0x1000);
486 hose->first_busno = 0;
487 hose->last_busno = 0xef;
492 static int __init maple_add_bridge(struct device_node *dev)
495 struct pci_controller *hose;
497 const int *bus_range;
500 DBG("Adding PCI host bridge %s\n", dev->full_name);
502 bus_range = of_get_property(dev, "bus-range", &len);
503 if (bus_range == NULL || len < 2 * sizeof(int)) {
504 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
508 hose = pcibios_alloc_controller(dev);
511 hose->first_busno = bus_range ? bus_range[0] : 0;
512 hose->last_busno = bus_range ? bus_range[1] : 0xff;
515 if (of_device_is_compatible(dev, "u3-agp")) {
517 disp_name = "U3-AGP";
519 } else if (of_device_is_compatible(dev, "u3-ht")) {
523 } else if (of_device_is_compatible(dev, "u4-pcie")) {
525 disp_name = "U4-PCIE";
528 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
529 disp_name, hose->first_busno, hose->last_busno);
531 /* Interpret the "ranges" property */
532 /* This also maps the I/O region and sets isa_io/mem_base */
533 pci_process_bridge_OF_ranges(hose, dev, primary);
535 /* Fixup "bus-range" OF property */
536 fixup_bus_range(dev);
538 /* Check for legacy IOs */
539 isa_bridge_find_early(hose);
545 void maple_pci_irq_fixup(struct pci_dev *dev)
547 DBG(" -> maple_pci_irq_fixup\n");
549 /* Fixup IRQ for PCIe host */
550 if (u4_pcie != NULL && dev->bus->number == 0 &&
551 pci_bus_to_host(dev->bus) == u4_pcie) {
552 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
553 dev->irq = irq_create_mapping(NULL, 1);
554 if (dev->irq != NO_IRQ)
555 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
558 /* Hide AMD8111 IDE interrupt when in legacy mode so
559 * the driver calls pci_get_legacy_ide_irq()
561 if (dev->vendor == PCI_VENDOR_ID_AMD &&
562 dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
563 (dev->class & 5) != 5) {
567 DBG(" <- maple_pci_irq_fixup\n");
570 void __init maple_pci_init(void)
572 struct device_node *np, *root;
573 struct device_node *ht = NULL;
575 /* Probe root PCI hosts, that is on U3 the AGP host and the
576 * HyperTransport host. That one is actually "kept" around
577 * and actually added last as it's resource management relies
578 * on the AGP resources to have been setup first
580 root = of_find_node_by_path("/");
582 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
585 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
588 if (strcmp(np->type, "pci") && strcmp(np->type, "ht"))
590 if ((of_device_is_compatible(np, "u4-pcie") ||
591 of_device_is_compatible(np, "u3-agp")) &&
592 maple_add_bridge(np) == 0)
595 if (of_device_is_compatible(np, "u3-ht")) {
602 /* Now setup the HyperTransport host if we found any
604 if (ht && maple_add_bridge(ht) != 0)
607 /* Setup the linkage between OF nodes and PHBs */
610 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
611 * assume there is no P2P bridge on the AGP bus, which should be a
612 * safe assumptions hopefully.
615 struct device_node *np = u3_agp->dn;
616 PCI_DN(np)->busno = 0xf0;
617 for (np = np->child; np; np = np->sibling)
618 PCI_DN(np)->busno = 0xf0;
621 /* Tell pci.c to not change any resource allocations. */
622 pci_add_flags(PCI_PROBE_ONLY);
625 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
627 struct device_node *np;
628 unsigned int defirq = channel ? 15 : 14;
631 if (pdev->vendor != PCI_VENDOR_ID_AMD ||
632 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
635 np = pci_device_to_OF_node(pdev);
637 printk("Failed to locate OF node for IDE %s\n",
641 irq = irq_of_parse_and_map(np, channel & 0x1);
643 printk("Failed to map onboard IDE interrupt for channel %d\n",
650 static void quirk_ipr_msi(struct pci_dev *dev)
652 /* Something prevents MSIs from the IPR from working on Bimini,
653 * and the driver has no smarts to recover. So disable MSI
656 if (machine_is(maple)) {
658 dev_info(&dev->dev, "Quirk disabled MSI\n");
661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,