2 * The file intends to implement the platform dependent EEH operations on
3 * powernv platform. Actually, the powernv was created in order to fully
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/atomic.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/msi.h>
21 #include <linux/pci.h>
22 #include <linux/proc_fs.h>
23 #include <linux/rbtree.h>
24 #include <linux/sched.h>
25 #include <linux/seq_file.h>
26 #include <linux/spinlock.h>
29 #include <asm/eeh_event.h>
30 #include <asm/firmware.h>
32 #include <asm/iommu.h>
33 #include <asm/machdep.h>
34 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
42 * powernv_eeh_init - EEH platform dependent initialization
44 * EEH platform dependent initialization on powernv
46 static int powernv_eeh_init(void)
48 struct pci_controller *hose;
51 /* We require OPALv3 */
52 if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
53 pr_warn("%s: OPALv3 is required !\n",
59 eeh_add_flag(EEH_PROBE_MODE_DEV);
62 * P7IOC blocks PCI config access to frozen PE, but PHB3
63 * doesn't do that. So we have to selectively enable I/O
64 * prior to collecting error log.
66 list_for_each_entry(hose, &hose_list, list_node) {
67 phb = hose->private_data;
69 if (phb->model == PNV_PHB_MODEL_P7IOC)
70 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
78 * powernv_eeh_post_init - EEH platform dependent post initialization
80 * EEH platform dependent post initialization on powernv. When
81 * the function is called, the EEH PEs and devices should have
82 * been built. If the I/O cache staff has been built, EEH is
83 * ready to supply service.
85 static int powernv_eeh_post_init(void)
87 struct pci_controller *hose;
91 list_for_each_entry(hose, &hose_list, list_node) {
92 phb = hose->private_data;
94 if (phb->eeh_ops && phb->eeh_ops->post_init) {
95 ret = phb->eeh_ops->post_init(hose);
105 * powernv_eeh_dev_probe - Do probe on PCI device
109 * When EEH module is installed during system boot, all PCI devices
110 * are checked one by one to see if it supports EEH. The function
111 * is introduced for the purpose. By default, EEH has been enabled
112 * on all PCI devices. That's to say, we only need do necessary
113 * initialization on the corresponding eeh device and create PE
116 * It's notable that's unsafe to retrieve the EEH device through
117 * the corresponding PCI device. During the PCI device hotplug, which
118 * was possiblly triggered by EEH core, the binding between EEH device
119 * and the PCI device isn't built yet.
121 static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
123 struct pci_controller *hose = pci_bus_to_host(dev->bus);
124 struct pnv_phb *phb = hose->private_data;
125 struct device_node *dn = pci_device_to_OF_node(dev);
126 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
130 * When probing the root bridge, which doesn't have any
131 * subordinate PCI devices. We don't have OF node for
132 * the root bridge. So it's not reasonable to continue
135 if (!dn || !edev || edev->pe)
138 /* Skip for PCI-ISA bridge */
139 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
142 /* Initialize eeh device */
143 edev->class_code = dev->class;
144 edev->mode &= 0xFFFFFF00;
145 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
146 edev->mode |= EEH_DEV_BRIDGE;
147 edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
148 if (pci_is_pcie(dev)) {
149 edev->pcie_cap = pci_pcie_cap(dev);
151 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
152 edev->mode |= EEH_DEV_ROOT_PORT;
153 else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
154 edev->mode |= EEH_DEV_DS_PORT;
156 edev->aer_cap = pci_find_ext_capability(dev,
160 edev->config_addr = ((dev->bus->number << 8) | dev->devfn);
161 edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff);
164 ret = eeh_add_to_parent_pe(edev);
166 pr_warn("%s: Can't add PCI dev %s to parent PE (%d)\n",
167 __func__, pci_name(dev), ret);
172 * If the PE contains any one of following adapters, the
173 * PCI config space can't be accessed when dumping EEH log.
174 * Otherwise, we will run into fenced PHB caused by shortage
175 * of outbound credits in the adapter. The PCI config access
176 * should be blocked until PE reset. MMIO access is dropped
177 * by hardware certainly. In order to drop PCI config requests,
178 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
179 * will be checked in the backend for PE state retrival. If
180 * the PE becomes frozen for the first time and the flag has
181 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
182 * that PE to block its config space.
184 * Broadcom Austin 4-ports NICs (14e4:1657)
185 * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
187 if ((dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x1657) ||
188 (dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x168e))
189 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
192 * Cache the PE primary bus, which can't be fetched when
193 * full hotplug is in progress. In that case, all child
194 * PCI devices of the PE are expected to be removed prior
198 edev->pe->bus = dev->bus;
201 * Enable EEH explicitly so that we will do EEH check
202 * while accessing I/O stuff
204 eeh_add_flag(EEH_ENABLED);
206 /* Save memory bars */
213 * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
215 * @option: operation to be issued
217 * The function is used to control the EEH functionality globally.
218 * Currently, following options are support according to PAPR:
219 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
221 static int powernv_eeh_set_option(struct eeh_pe *pe, int option)
223 struct pci_controller *hose = pe->phb;
224 struct pnv_phb *phb = hose->private_data;
228 * What we need do is pass it down for hardware
229 * implementation to handle it.
231 if (phb->eeh_ops && phb->eeh_ops->set_option)
232 ret = phb->eeh_ops->set_option(pe, option);
238 * powernv_eeh_get_pe_addr - Retrieve PE address
241 * Retrieve the PE address according to the given tranditional
242 * PCI BDF (Bus/Device/Function) address.
244 static int powernv_eeh_get_pe_addr(struct eeh_pe *pe)
250 * powernv_eeh_get_state - Retrieve PE state
252 * @delay: delay while PE state is temporarily unavailable
254 * Retrieve the state of the specified PE. For IODA-compitable
255 * platform, it should be retrieved from IODA table. Therefore,
256 * we prefer passing down to hardware implementation to handle
259 static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay)
261 struct pci_controller *hose = pe->phb;
262 struct pnv_phb *phb = hose->private_data;
263 int ret = EEH_STATE_NOT_SUPPORT;
265 if (phb->eeh_ops && phb->eeh_ops->get_state) {
266 ret = phb->eeh_ops->get_state(pe);
269 * If the PE state is temporarily unavailable,
270 * to inform the EEH core delay for default
275 if (ret & EEH_STATE_UNAVAILABLE)
284 * powernv_eeh_reset - Reset the specified PE
286 * @option: reset option
288 * Reset the specified PE
290 static int powernv_eeh_reset(struct eeh_pe *pe, int option)
292 struct pci_controller *hose = pe->phb;
293 struct pnv_phb *phb = hose->private_data;
296 if (phb->eeh_ops && phb->eeh_ops->reset)
297 ret = phb->eeh_ops->reset(pe, option);
303 * powernv_eeh_wait_state - Wait for PE state
305 * @max_wait: maximal period in microsecond
307 * Wait for the state of associated PE. It might take some time
308 * to retrieve the PE's state.
310 static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
316 ret = powernv_eeh_get_state(pe, &mwait);
319 * If the PE's state is temporarily unavailable,
320 * we have to wait for the specified time. Otherwise,
321 * the PE's state will be returned immediately.
323 if (ret != EEH_STATE_UNAVAILABLE)
328 pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
329 __func__, pe->addr, max_wait);
330 return EEH_STATE_NOT_SUPPORT;
336 return EEH_STATE_NOT_SUPPORT;
340 * powernv_eeh_get_log - Retrieve error log
342 * @severity: temporary or permanent error log
343 * @drv_log: driver log to be combined with retrieved error log
344 * @len: length of driver log
346 * Retrieve the temporary or permanent error from the PE.
348 static int powernv_eeh_get_log(struct eeh_pe *pe, int severity,
349 char *drv_log, unsigned long len)
351 struct pci_controller *hose = pe->phb;
352 struct pnv_phb *phb = hose->private_data;
355 if (phb->eeh_ops && phb->eeh_ops->get_log)
356 ret = phb->eeh_ops->get_log(pe, severity, drv_log, len);
362 * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
365 * The function will be called to reconfigure the bridges included
366 * in the specified PE so that the mulfunctional PE would be recovered
369 static int powernv_eeh_configure_bridge(struct eeh_pe *pe)
371 struct pci_controller *hose = pe->phb;
372 struct pnv_phb *phb = hose->private_data;
375 if (phb->eeh_ops && phb->eeh_ops->configure_bridge)
376 ret = phb->eeh_ops->configure_bridge(pe);
382 * powernv_pe_err_inject - Inject specified error to the indicated PE
383 * @pe: the indicated PE
385 * @func: specific error type
387 * @mask: address mask
389 * The routine is called to inject specified error, which is
390 * determined by @type and @func, to the indicated PE for
393 static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
394 unsigned long addr, unsigned long mask)
396 struct pci_controller *hose = pe->phb;
397 struct pnv_phb *phb = hose->private_data;
400 if (phb->eeh_ops && phb->eeh_ops->err_inject)
401 ret = phb->eeh_ops->err_inject(pe, type, func, addr, mask);
406 static inline bool powernv_eeh_cfg_blocked(struct device_node *dn)
408 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
410 if (!edev || !edev->pe)
413 if (edev->pe->state & EEH_PE_CFG_BLOCKED)
419 static int powernv_eeh_read_config(struct device_node *dn,
420 int where, int size, u32 *val)
422 if (powernv_eeh_cfg_blocked(dn)) {
424 return PCIBIOS_SET_FAILED;
427 return pnv_pci_cfg_read(dn, where, size, val);
430 static int powernv_eeh_write_config(struct device_node *dn,
431 int where, int size, u32 val)
433 if (powernv_eeh_cfg_blocked(dn))
434 return PCIBIOS_SET_FAILED;
436 return pnv_pci_cfg_write(dn, where, size, val);
440 * powernv_eeh_next_error - Retrieve next EEH error to handle
443 * Using OPAL API, to retrieve next EEH error for EEH core to handle
445 static int powernv_eeh_next_error(struct eeh_pe **pe)
447 struct pci_controller *hose;
448 struct pnv_phb *phb = NULL;
450 list_for_each_entry(hose, &hose_list, list_node) {
451 phb = hose->private_data;
455 if (phb && phb->eeh_ops->next_error)
456 return phb->eeh_ops->next_error(pe);
461 static int powernv_eeh_restore_config(struct device_node *dn)
463 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
470 phb = edev->phb->private_data;
471 ret = opal_pci_reinit(phb->opal_id,
472 OPAL_REINIT_PCI_DEV, edev->config_addr);
474 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
475 __func__, edev->config_addr, ret);
482 static struct eeh_ops powernv_eeh_ops = {
484 .init = powernv_eeh_init,
485 .post_init = powernv_eeh_post_init,
487 .dev_probe = powernv_eeh_dev_probe,
488 .set_option = powernv_eeh_set_option,
489 .get_pe_addr = powernv_eeh_get_pe_addr,
490 .get_state = powernv_eeh_get_state,
491 .reset = powernv_eeh_reset,
492 .wait_state = powernv_eeh_wait_state,
493 .get_log = powernv_eeh_get_log,
494 .configure_bridge = powernv_eeh_configure_bridge,
495 .err_inject = powernv_eeh_err_inject,
496 .read_config = powernv_eeh_read_config,
497 .write_config = powernv_eeh_write_config,
498 .next_error = powernv_eeh_next_error,
499 .restore_config = powernv_eeh_restore_config
503 * eeh_powernv_init - Register platform dependent EEH operations
505 * EEH initialization on powernv platform. This function should be
506 * called before any EEH related functions.
508 static int __init eeh_powernv_init(void)
512 eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
513 ret = eeh_ops_register(&powernv_eeh_ops);
515 pr_info("EEH: PowerNV platform initialized\n");
517 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
521 machine_early_initcall(powernv, eeh_powernv_init);