2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21 #include <linux/irq.h>
23 #include <linux/msi.h>
25 #include <asm/sections.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/machdep.h>
30 #include <asm/msi_bitmap.h>
31 #include <asm/ppc-pci.h>
33 #include <asm/iommu.h>
36 #include <asm/debug.h>
41 #define define_pe_printk_level(func, kern_level) \
42 static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \
44 struct va_format vaf; \
49 va_start(args, fmt); \
55 strlcpy(pfix, dev_name(&pe->pdev->dev), \
58 sprintf(pfix, "%04x:%02x ", \
59 pci_domain_nr(pe->pbus), \
61 r = printk(kern_level "pci %s: [PE# %.3d] %pV", \
62 pfix, pe->pe_number, &vaf); \
69 define_pe_printk_level(pe_err, KERN_ERR);
70 define_pe_printk_level(pe_warn, KERN_WARNING);
71 define_pe_printk_level(pe_info, KERN_INFO);
74 * stdcix is only supposed to be used in hypervisor real mode as per
75 * the architecture spec
77 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
79 __asm__ __volatile__("stdcix %0,0,%1"
80 : : "r" (val), "r" (paddr) : "memory");
83 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
88 pe = find_next_zero_bit(phb->ioda.pe_alloc,
89 phb->ioda.total_pe, 0);
90 if (pe >= phb->ioda.total_pe)
91 return IODA_INVALID_PE;
92 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
94 phb->ioda.pe_array[pe].phb = phb;
95 phb->ioda.pe_array[pe].pe_number = pe;
99 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
101 WARN_ON(phb->ioda.pe_array[pe].pdev);
103 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
104 clear_bit(pe, phb->ioda.pe_alloc);
107 /* Currently those 2 are only used when MSIs are enabled, this will change
108 * but in the meantime, we need to protect them to avoid warnings
110 #ifdef CONFIG_PCI_MSI
111 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
113 struct pci_controller *hose = pci_bus_to_host(dev->bus);
114 struct pnv_phb *phb = hose->private_data;
115 struct pci_dn *pdn = pci_get_pdn(dev);
119 if (pdn->pe_number == IODA_INVALID_PE)
121 return &phb->ioda.pe_array[pdn->pe_number];
123 #endif /* CONFIG_PCI_MSI */
125 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
127 struct pci_dev *parent;
128 uint8_t bcomp, dcomp, fcomp;
129 long rc, rid_end, rid;
131 /* Bus validation ? */
135 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
136 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
137 parent = pe->pbus->self;
138 if (pe->flags & PNV_IODA_PE_BUS_ALL)
139 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
144 case 1: bcomp = OpalPciBusAll; break;
145 case 2: bcomp = OpalPciBus7Bits; break;
146 case 4: bcomp = OpalPciBus6Bits; break;
147 case 8: bcomp = OpalPciBus5Bits; break;
148 case 16: bcomp = OpalPciBus4Bits; break;
149 case 32: bcomp = OpalPciBus3Bits; break;
151 pr_err("%s: Number of subordinate busses %d"
153 pci_name(pe->pbus->self), count);
154 /* Do an exact match only */
155 bcomp = OpalPciBusAll;
157 rid_end = pe->rid + (count << 8);
159 parent = pe->pdev->bus->self;
160 bcomp = OpalPciBusAll;
161 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
162 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
163 rid_end = pe->rid + 1;
167 * Associate PE in PELT. We need add the PE into the
168 * corresponding PELT-V as well. Otherwise, the error
169 * originated from the PE might contribute to other
172 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
173 bcomp, dcomp, fcomp, OPAL_MAP_PE);
175 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
179 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
180 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
182 pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc);
183 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
184 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
186 /* Add to all parents PELT-V */
188 struct pci_dn *pdn = pci_get_pdn(parent);
189 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
190 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
191 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
192 /* XXX What to do in case of error ? */
194 parent = parent->bus->self;
196 /* Setup reverse map */
197 for (rid = pe->rid; rid < rid_end; rid++)
198 phb->ioda.pe_rmap[rid] = pe->pe_number;
200 /* Setup one MVTs on IODA1 */
201 if (phb->type == PNV_PHB_IODA1) {
202 pe->mve_number = pe->pe_number;
203 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
206 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
210 rc = opal_pci_set_mve_enable(phb->opal_id,
211 pe->mve_number, OPAL_ENABLE_MVE);
213 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
218 } else if (phb->type == PNV_PHB_IODA2)
224 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
225 struct pnv_ioda_pe *pe)
227 struct pnv_ioda_pe *lpe;
229 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
230 if (lpe->dma_weight < pe->dma_weight) {
231 list_add_tail(&pe->dma_link, &lpe->dma_link);
235 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
238 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
240 /* This is quite simplistic. The "base" weight of a device
241 * is 10. 0 means no DMA is to be accounted for it.
244 /* If it's a bridge, no DMA */
245 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
248 /* Reduce the weight of slow USB controllers */
249 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
250 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
251 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
254 /* Increase the weight of RAID (includes Obsidian) */
255 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
263 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
265 struct pci_controller *hose = pci_bus_to_host(dev->bus);
266 struct pnv_phb *phb = hose->private_data;
267 struct pci_dn *pdn = pci_get_pdn(dev);
268 struct pnv_ioda_pe *pe;
272 pr_err("%s: Device tree node not associated properly\n",
276 if (pdn->pe_number != IODA_INVALID_PE)
279 /* PE#0 has been pre-set */
280 if (dev->bus->number == 0)
283 pe_num = pnv_ioda_alloc_pe(phb);
284 if (pe_num == IODA_INVALID_PE) {
285 pr_warning("%s: Not enough PE# available, disabling device\n",
290 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
291 * pointer in the PE data structure, both should be destroyed at the
292 * same time. However, this needs to be looked at more closely again
293 * once we actually start removing things (Hotplug, SR-IOV, ...)
295 * At some point we want to remove the PDN completely anyways
297 pe = &phb->ioda.pe_array[pe_num];
300 pdn->pe_number = pe_num;
305 pe->rid = dev->bus->number << 8 | pdn->devfn;
307 pe_info(pe, "Associated device to PE\n");
309 if (pnv_ioda_configure_pe(phb, pe)) {
310 /* XXX What do we do here ? */
312 pnv_ioda_free_pe(phb, pe_num);
313 pdn->pe_number = IODA_INVALID_PE;
319 /* Assign a DMA weight to the device */
320 pe->dma_weight = pnv_ioda_dma_weight(dev);
321 if (pe->dma_weight != 0) {
322 phb->ioda.dma_weight += pe->dma_weight;
323 phb->ioda.dma_pe_count++;
327 pnv_ioda_link_pe_by_weight(phb, pe);
331 #endif /* Useful for SRIOV case */
333 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
337 list_for_each_entry(dev, &bus->devices, bus_list) {
338 struct pci_dn *pdn = pci_get_pdn(dev);
341 pr_warn("%s: No device node associated with device !\n",
347 pdn->pe_number = pe->pe_number;
348 pe->dma_weight += pnv_ioda_dma_weight(dev);
349 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
350 pnv_ioda_setup_same_PE(dev->subordinate, pe);
355 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
356 * single PCI bus. Another one that contains the primary PCI bus and its
357 * subordinate PCI devices and buses. The second type of PE is normally
358 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
360 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
362 struct pci_controller *hose = pci_bus_to_host(bus);
363 struct pnv_phb *phb = hose->private_data;
364 struct pnv_ioda_pe *pe;
367 pe_num = pnv_ioda_alloc_pe(phb);
368 if (pe_num == IODA_INVALID_PE) {
369 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
370 __func__, pci_domain_nr(bus), bus->number);
374 pe = &phb->ioda.pe_array[pe_num];
375 pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
380 pe->rid = bus->busn_res.start << 8;
384 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
385 bus->busn_res.start, bus->busn_res.end, pe_num);
387 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
388 bus->busn_res.start, pe_num);
390 if (pnv_ioda_configure_pe(phb, pe)) {
391 /* XXX What do we do here ? */
393 pnv_ioda_free_pe(phb, pe_num);
398 /* Associate it with all child devices */
399 pnv_ioda_setup_same_PE(bus, pe);
401 /* Put PE to the list */
402 list_add_tail(&pe->list, &phb->ioda.pe_list);
404 /* Account for one DMA PE if at least one DMA capable device exist
407 if (pe->dma_weight != 0) {
408 phb->ioda.dma_weight += pe->dma_weight;
409 phb->ioda.dma_pe_count++;
413 pnv_ioda_link_pe_by_weight(phb, pe);
416 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
420 pnv_ioda_setup_bus_PE(bus, 0);
422 list_for_each_entry(dev, &bus->devices, bus_list) {
423 if (dev->subordinate) {
424 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
425 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
427 pnv_ioda_setup_PEs(dev->subordinate);
433 * Configure PEs so that the downstream PCI buses and devices
434 * could have their associated PE#. Unfortunately, we didn't
435 * figure out the way to identify the PLX bridge yet. So we
436 * simply put the PCI bus and the subordinate behind the root
437 * port to PE# here. The game rule here is expected to be changed
438 * as soon as we can detected PLX bridge correctly.
440 static void pnv_pci_ioda_setup_PEs(void)
442 struct pci_controller *hose, *tmp;
444 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
445 pnv_ioda_setup_PEs(hose->bus);
449 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
451 struct pci_dn *pdn = pci_get_pdn(pdev);
452 struct pnv_ioda_pe *pe;
455 * The function can be called while the PE#
456 * hasn't been assigned. Do nothing for the
459 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
462 pe = &phb->ioda.pe_array[pdn->pe_number];
463 set_iommu_table_base(&pdev->dev, &pe->tce32_table);
466 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
470 list_for_each_entry(dev, &bus->devices, bus_list) {
471 set_iommu_table_base(&dev->dev, &pe->tce32_table);
472 if (dev->subordinate)
473 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
477 static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe,
478 struct iommu_table *tbl,
479 __be64 *startp, __be64 *endp, bool rm)
481 __be64 __iomem *invalidate = rm ?
482 (__be64 __iomem *)pe->tce_inval_reg_phys :
483 (__be64 __iomem *)tbl->it_index;
484 unsigned long start, end, inc;
486 start = __pa(startp);
489 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
494 start |= tbl->it_busno;
495 end |= tbl->it_busno;
496 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
497 /* p7ioc-style invalidation, 2 TCEs per write */
498 start |= (1ull << 63);
502 /* Default (older HW) */
506 end |= inc - 1; /* round up end to be different than start */
508 mb(); /* Ensure above stores are visible */
509 while (start <= end) {
511 __raw_rm_writeq(cpu_to_be64(start), invalidate);
513 __raw_writeq(cpu_to_be64(start), invalidate);
518 * The iommu layer will do another mb() for us on build()
519 * and we don't care on free()
523 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
524 struct iommu_table *tbl,
525 __be64 *startp, __be64 *endp, bool rm)
527 unsigned long start, end, inc;
528 __be64 __iomem *invalidate = rm ?
529 (__be64 __iomem *)pe->tce_inval_reg_phys :
530 (__be64 __iomem *)tbl->it_index;
532 /* We'll invalidate DMA address in PE scope */
534 start |= (pe->pe_number & 0xFF);
537 /* Figure out the start, end and step */
538 inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
539 start |= (inc << 12);
540 inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
545 while (start <= end) {
547 __raw_rm_writeq(cpu_to_be64(start), invalidate);
549 __raw_writeq(cpu_to_be64(start), invalidate);
554 void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
555 __be64 *startp, __be64 *endp, bool rm)
557 struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
559 struct pnv_phb *phb = pe->phb;
561 if (phb->type == PNV_PHB_IODA1)
562 pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm);
564 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm);
567 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
568 struct pnv_ioda_pe *pe, unsigned int base,
572 struct page *tce_mem = NULL;
573 const __be64 *swinvp;
574 struct iommu_table *tbl;
579 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
580 #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
582 /* XXX FIXME: Handle 64-bit only DMA devices */
583 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
584 /* XXX FIXME: Allocate multi-level tables on PHB3 */
586 /* We shouldn't already have a 32-bit DMA associated */
587 if (WARN_ON(pe->tce32_seg >= 0))
590 /* Grab a 32-bit TCE table */
591 pe->tce32_seg = base;
592 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
593 (base << 28), ((base + segs) << 28) - 1);
595 /* XXX Currently, we allocate one big contiguous table for the
596 * TCEs. We only really need one chunk per 256M of TCE space
597 * (ie per segment) but that's an optimization for later, it
598 * requires some added smarts with our get/put_tce implementation
600 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
601 get_order(TCE32_TABLE_SIZE * segs));
603 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
606 addr = page_address(tce_mem);
607 memset(addr, 0, TCE32_TABLE_SIZE * segs);
610 for (i = 0; i < segs; i++) {
611 rc = opal_pci_map_pe_dma_window(phb->opal_id,
614 __pa(addr) + TCE32_TABLE_SIZE * i,
615 TCE32_TABLE_SIZE, 0x1000);
617 pe_err(pe, " Failed to configure 32-bit TCE table,"
623 /* Setup linux iommu table */
624 tbl = &pe->tce32_table;
625 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
628 /* OPAL variant of P7IOC SW invalidated TCEs */
629 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
631 /* We need a couple more fields -- an address and a data
632 * to or. Since the bus is only printed out on table free
633 * errors, and on the first pass the data will be a relative
634 * bus number, print that out instead.
637 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
638 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
640 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE |
643 iommu_init_table(tbl, phb->hose->node);
644 iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
647 set_iommu_table_base(&pe->pdev->dev, tbl);
649 pnv_ioda_setup_bus_dma(pe, pe->pbus);
653 /* XXX Failure: Try to fallback to 64-bit only ? */
654 if (pe->tce32_seg >= 0)
657 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
660 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
661 struct pnv_ioda_pe *pe)
663 struct page *tce_mem = NULL;
665 const __be64 *swinvp;
666 struct iommu_table *tbl;
667 unsigned int tce_table_size, end;
670 /* We shouldn't already have a 32-bit DMA associated */
671 if (WARN_ON(pe->tce32_seg >= 0))
674 /* The PE will reserve all possible 32-bits space */
676 end = (1 << ilog2(phb->ioda.m32_pci_base));
677 tce_table_size = (end / 0x1000) * 8;
678 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
681 /* Allocate TCE table */
682 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
683 get_order(tce_table_size));
685 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
688 addr = page_address(tce_mem);
689 memset(addr, 0, tce_table_size);
692 * Map TCE table through TVT. The TVE index is the PE number
693 * shifted by 1 bit for 32-bits DMA space.
695 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
696 pe->pe_number << 1, 1, __pa(addr),
697 tce_table_size, 0x1000);
699 pe_err(pe, "Failed to configure 32-bit TCE table,"
704 /* Setup linux iommu table */
705 tbl = &pe->tce32_table;
706 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0);
708 /* OPAL variant of PHB3 invalidated TCEs */
709 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
711 /* We need a couple more fields -- an address and a data
712 * to or. Since the bus is only printed out on table free
713 * errors, and on the first pass the data will be a relative
714 * bus number, print that out instead.
717 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
718 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
720 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
722 iommu_init_table(tbl, phb->hose->node);
725 set_iommu_table_base(&pe->pdev->dev, tbl);
727 pnv_ioda_setup_bus_dma(pe, pe->pbus);
731 if (pe->tce32_seg >= 0)
734 __free_pages(tce_mem, get_order(tce_table_size));
737 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
739 struct pci_controller *hose = phb->hose;
740 unsigned int residual, remaining, segs, tw, base;
741 struct pnv_ioda_pe *pe;
743 /* If we have more PE# than segments available, hand out one
744 * per PE until we run out and let the rest fail. If not,
745 * then we assign at least one segment per PE, plus more based
746 * on the amount of devices under that PE
748 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
751 residual = phb->ioda.tce32_count -
752 phb->ioda.dma_pe_count;
754 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
755 hose->global_number, phb->ioda.tce32_count);
756 pr_info("PCI: %d PE# for a total weight of %d\n",
757 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
759 /* Walk our PE list and configure their DMA segments, hand them
760 * out one base segment plus any residual segments based on
763 remaining = phb->ioda.tce32_count;
764 tw = phb->ioda.dma_weight;
766 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
770 pe_warn(pe, "No DMA32 resources available\n");
775 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
776 if (segs > remaining)
781 * For IODA2 compliant PHB3, we needn't care about the weight.
782 * The all available 32-bits DMA space will be assigned to
785 if (phb->type == PNV_PHB_IODA1) {
786 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
787 pe->dma_weight, segs);
788 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
790 pe_info(pe, "Assign DMA32 space\n");
792 pnv_pci_ioda2_setup_dma_pe(phb, pe);
800 #ifdef CONFIG_PCI_MSI
801 static void pnv_ioda2_msi_eoi(struct irq_data *d)
803 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
804 struct irq_chip *chip = irq_data_get_irq_chip(d);
805 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
809 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
815 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
816 unsigned int hwirq, unsigned int virq,
817 unsigned int is_64, struct msi_msg *msg)
819 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
820 struct pci_dn *pdn = pci_get_pdn(dev);
821 struct irq_data *idata;
822 struct irq_chip *ichip;
823 unsigned int xive_num = hwirq - phb->msi_base;
827 /* No PE assigned ? bail out ... no MSI for you ! */
831 /* Check if we have an MVE */
832 if (pe->mve_number < 0)
835 /* Force 32-bit MSI on some broken devices */
836 if (pdn && pdn->force_32bit_msi)
839 /* Assign XIVE to PE */
840 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
842 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
843 pci_name(dev), rc, xive_num);
850 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
853 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
857 msg->address_hi = be64_to_cpu(addr64) >> 32;
858 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
862 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
865 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
870 msg->address_lo = be32_to_cpu(addr32);
872 msg->data = be32_to_cpu(data);
875 * Change the IRQ chip for the MSI interrupts on PHB3.
876 * The corresponding IRQ chip should be populated for
879 if (phb->type == PNV_PHB_IODA2) {
880 if (!phb->ioda.irq_chip_init) {
881 idata = irq_get_irq_data(virq);
882 ichip = irq_data_get_irq_chip(idata);
883 phb->ioda.irq_chip_init = 1;
884 phb->ioda.irq_chip = *ichip;
885 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
888 irq_set_chip(virq, &phb->ioda.irq_chip);
891 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
892 " address=%x_%08x data=%x PE# %d\n",
893 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
894 msg->address_hi, msg->address_lo, data, pe->pe_number);
899 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
902 const __be32 *prop = of_get_property(phb->hose->dn,
903 "ibm,opal-msi-ranges", NULL);
906 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
911 phb->msi_base = be32_to_cpup(prop);
912 count = be32_to_cpup(prop + 1);
913 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
914 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
915 phb->hose->global_number);
919 phb->msi_setup = pnv_pci_ioda_msi_setup;
920 phb->msi32_support = 1;
921 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
922 count, phb->msi_base);
925 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
926 #endif /* CONFIG_PCI_MSI */
929 * This function is supposed to be called on basis of PE from top
930 * to bottom style. So the the I/O or MMIO segment assigned to
931 * parent PE could be overrided by its child PEs if necessary.
933 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
934 struct pnv_ioda_pe *pe)
936 struct pnv_phb *phb = hose->private_data;
937 struct pci_bus_region region;
938 struct resource *res;
943 * NOTE: We only care PCI bus based PE for now. For PCI
944 * device based PE, for example SRIOV sensitive VF should
945 * be figured out later.
947 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
949 pci_bus_for_each_resource(pe->pbus, res, i) {
950 if (!res || !res->flags ||
951 res->start > res->end)
954 if (res->flags & IORESOURCE_IO) {
955 region.start = res->start - phb->ioda.io_pci_base;
956 region.end = res->end - phb->ioda.io_pci_base;
957 index = region.start / phb->ioda.io_segsize;
959 while (index < phb->ioda.total_pe &&
960 region.start <= region.end) {
961 phb->ioda.io_segmap[index] = pe->pe_number;
962 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
963 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
964 if (rc != OPAL_SUCCESS) {
965 pr_err("%s: OPAL error %d when mapping IO "
966 "segment #%d to PE#%d\n",
967 __func__, rc, index, pe->pe_number);
971 region.start += phb->ioda.io_segsize;
974 } else if (res->flags & IORESOURCE_MEM) {
975 /* WARNING: Assumes M32 is mem region 0 in PHB. We need to
976 * harden that algorithm when we start supporting M64
978 region.start = res->start -
979 hose->mem_offset[0] -
980 phb->ioda.m32_pci_base;
981 region.end = res->end -
982 hose->mem_offset[0] -
983 phb->ioda.m32_pci_base;
984 index = region.start / phb->ioda.m32_segsize;
986 while (index < phb->ioda.total_pe &&
987 region.start <= region.end) {
988 phb->ioda.m32_segmap[index] = pe->pe_number;
989 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
990 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
991 if (rc != OPAL_SUCCESS) {
992 pr_err("%s: OPAL error %d when mapping M32 "
993 "segment#%d to PE#%d",
994 __func__, rc, index, pe->pe_number);
998 region.start += phb->ioda.m32_segsize;
1005 static void pnv_pci_ioda_setup_seg(void)
1007 struct pci_controller *tmp, *hose;
1008 struct pnv_phb *phb;
1009 struct pnv_ioda_pe *pe;
1011 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1012 phb = hose->private_data;
1013 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
1014 pnv_ioda_setup_pe_seg(hose, pe);
1019 static void pnv_pci_ioda_setup_DMA(void)
1021 struct pci_controller *hose, *tmp;
1022 struct pnv_phb *phb;
1024 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1025 pnv_ioda_setup_dma(hose->private_data);
1027 /* Mark the PHB initialization done */
1028 phb = hose->private_data;
1029 phb->initialized = 1;
1033 static void pnv_pci_ioda_create_dbgfs(void)
1035 #ifdef CONFIG_DEBUG_FS
1036 struct pci_controller *hose, *tmp;
1037 struct pnv_phb *phb;
1040 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1041 phb = hose->private_data;
1043 sprintf(name, "PCI%04x", hose->global_number);
1044 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
1046 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
1047 __func__, hose->global_number);
1049 #endif /* CONFIG_DEBUG_FS */
1052 static void pnv_pci_ioda_fixup(void)
1054 pnv_pci_ioda_setup_PEs();
1055 pnv_pci_ioda_setup_seg();
1056 pnv_pci_ioda_setup_DMA();
1058 pnv_pci_ioda_create_dbgfs();
1061 eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
1062 eeh_addr_cache_build();
1068 * Returns the alignment for I/O or memory windows for P2P
1069 * bridges. That actually depends on how PEs are segmented.
1070 * For now, we return I/O or M32 segment size for PE sensitive
1071 * P2P bridges. Otherwise, the default values (4KiB for I/O,
1072 * 1MiB for memory) will be returned.
1074 * The current PCI bus might be put into one PE, which was
1075 * create against the parent PCI bridge. For that case, we
1076 * needn't enlarge the alignment so that we can save some
1079 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
1082 struct pci_dev *bridge;
1083 struct pci_controller *hose = pci_bus_to_host(bus);
1084 struct pnv_phb *phb = hose->private_data;
1085 int num_pci_bridges = 0;
1089 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
1091 if (num_pci_bridges >= 2)
1095 bridge = bridge->bus->self;
1098 /* We need support prefetchable memory window later */
1099 if (type & IORESOURCE_MEM)
1100 return phb->ioda.m32_segsize;
1102 return phb->ioda.io_segsize;
1105 /* Prevent enabling devices for which we couldn't properly
1108 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
1110 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1111 struct pnv_phb *phb = hose->private_data;
1114 /* The function is probably called while the PEs have
1115 * not be created yet. For example, resource reassignment
1116 * during PCI probe period. We just skip the check if
1119 if (!phb->initialized)
1122 pdn = pci_get_pdn(dev);
1123 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1129 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
1132 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
1135 static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
1137 opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET,
1141 void __init pnv_pci_init_ioda_phb(struct device_node *np,
1142 u64 hub_id, int ioda_type)
1144 struct pci_controller *hose;
1145 struct pnv_phb *phb;
1146 unsigned long size, m32map_off, iomap_off, pemap_off;
1147 const __be64 *prop64;
1148 const __be32 *prop32;
1154 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
1156 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
1158 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
1161 phb_id = be64_to_cpup(prop64);
1162 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
1164 phb = alloc_bootmem(sizeof(struct pnv_phb));
1166 pr_err(" Out of memory !\n");
1170 /* Allocate PCI controller */
1171 memset(phb, 0, sizeof(struct pnv_phb));
1172 phb->hose = hose = pcibios_alloc_controller(np);
1174 pr_err(" Can't allocate PCI controller for %s\n",
1176 free_bootmem((unsigned long)phb, sizeof(struct pnv_phb));
1180 spin_lock_init(&phb->lock);
1181 prop32 = of_get_property(np, "bus-range", &len);
1182 if (prop32 && len == 8) {
1183 hose->first_busno = be32_to_cpu(prop32[0]);
1184 hose->last_busno = be32_to_cpu(prop32[1]);
1186 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
1187 hose->first_busno = 0;
1188 hose->last_busno = 0xff;
1190 hose->private_data = phb;
1191 phb->hub_id = hub_id;
1192 phb->opal_id = phb_id;
1193 phb->type = ioda_type;
1195 /* Detect specific models for error handling */
1196 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
1197 phb->model = PNV_PHB_MODEL_P7IOC;
1198 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
1199 phb->model = PNV_PHB_MODEL_PHB3;
1201 phb->model = PNV_PHB_MODEL_UNKNOWN;
1203 /* Parse 32-bit and IO ranges (if any) */
1204 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
1207 phb->regs = of_iomap(np, 0);
1208 if (phb->regs == NULL)
1209 pr_err(" Failed to map registers !\n");
1211 /* Initialize more IODA stuff */
1212 phb->ioda.total_pe = 1;
1213 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
1215 phb->ioda.total_pe = be32_to_cpup(prop32);
1216 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
1218 phb->ioda.reserved_pe = be32_to_cpup(prop32);
1219 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
1220 /* FW Has already off top 64k of M32 space (MSI space) */
1221 phb->ioda.m32_size += 0x10000;
1223 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
1224 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
1225 phb->ioda.io_size = hose->pci_io_size;
1226 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
1227 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
1229 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
1230 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
1232 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
1234 if (phb->type == PNV_PHB_IODA1) {
1236 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
1239 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
1240 aux = alloc_bootmem(size);
1241 memset(aux, 0, size);
1242 phb->ioda.pe_alloc = aux;
1243 phb->ioda.m32_segmap = aux + m32map_off;
1244 if (phb->type == PNV_PHB_IODA1)
1245 phb->ioda.io_segmap = aux + iomap_off;
1246 phb->ioda.pe_array = aux + pemap_off;
1247 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
1249 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
1250 INIT_LIST_HEAD(&phb->ioda.pe_list);
1252 /* Calculate how many 32-bit TCE segments we have */
1253 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
1255 /* Clear unusable m64 */
1256 hose->mem_resources[1].flags = 0;
1257 hose->mem_resources[1].start = 0;
1258 hose->mem_resources[1].end = 0;
1259 hose->mem_resources[2].flags = 0;
1260 hose->mem_resources[2].start = 0;
1261 hose->mem_resources[2].end = 0;
1263 #if 0 /* We should really do that ... */
1264 rc = opal_pci_set_phb_mem_window(opal->phb_id,
1267 starting_real_address,
1268 starting_pci_address,
1272 pr_info(" %d (%d) PE's M32: 0x%x [segment=0x%x]"
1273 " IO: 0x%x [segment=0x%x]\n",
1275 phb->ioda.reserved_pe,
1276 phb->ioda.m32_size, phb->ioda.m32_segsize,
1277 phb->ioda.io_size, phb->ioda.io_segsize);
1279 phb->hose->ops = &pnv_pci_ops;
1281 phb->eeh_ops = &ioda_eeh_ops;
1284 /* Setup RID -> PE mapping function */
1285 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
1288 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
1290 /* Setup shutdown function for kexec */
1291 phb->shutdown = pnv_pci_ioda_shutdown;
1293 /* Setup MSI support */
1294 pnv_pci_init_ioda_msis(phb);
1297 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
1298 * to let the PCI core do resource assignment. It's supposed
1299 * that the PCI core will do correct I/O and MMIO alignment
1300 * for the P2P bridge bars so that each PCI bus (excluding
1301 * the child P2P bridges) can form individual PE.
1303 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
1304 ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1305 ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
1306 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1308 /* Reset IODA tables to a clean state */
1309 rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1311 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
1314 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
1316 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
1319 void __init pnv_pci_init_ioda_hub(struct device_node *np)
1321 struct device_node *phbn;
1322 const __be64 *prop64;
1325 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1327 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1329 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1332 hub_id = be64_to_cpup(prop64);
1333 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1335 /* Count child PHBs */
1336 for_each_child_of_node(np, phbn) {
1337 /* Look for IODA1 PHBs */
1338 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1339 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);