arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26
  27 #include <asm/sections.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/machdep.h>
  32 #include <asm/msi_bitmap.h>
  33 #include <asm/ppc-pci.h>
  34 #include <asm/opal.h>
  35 #include <asm/iommu.h>
  36 #include <asm/tce.h>
  37 #include <asm/xics.h>
  38 #include <asm/debug.h>
  39 #include <asm/firmware.h>
  40 #include <asm/pnv-pci.h>
  41
  42 #include <misc/cxl.h>
  43
  44 #include "powernv.h"
  45 #include "pci.h"
  46
  47 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
  48 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
  49
  50 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  51                             const char *fmt, ...)
  52 {
  53         struct va_format vaf;
  54         va_list args;
  55         char pfix[32];
  56
  57         va_start(args, fmt);
  58
  59         vaf.fmt = fmt;
  60         vaf.va = &args;
  61
  62         if (pe->flags & PNV_IODA_PE_DEV)
  63                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  64         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  65                 sprintf(pfix, "%04x:%02x     ",
  66                         pci_domain_nr(pe->pbus), pe->pbus->number);
  67 #ifdef CONFIG_PCI_IOV
  68         else if (pe->flags & PNV_IODA_PE_VF)
  69                 sprintf(pfix, "%04x:%02x:%2x.%d",
  70                         pci_domain_nr(pe->parent_dev->bus),
  71                         (pe->rid & 0xff00) >> 8,
  72                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  73 #endif /* CONFIG_PCI_IOV*/
  74
  75         printk("%spci %s: [PE# %.3d] %pV",
  76                level, pfix, pe->pe_number, &vaf);
  77
  78         va_end(args);
  79 }
  80
  81 #define pe_err(pe, fmt, ...)                                    \
  82         pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
  83 #define pe_warn(pe, fmt, ...)                                   \
  84         pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
  85 #define pe_info(pe, fmt, ...)                                   \
  86         pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
  87
  88 static bool pnv_iommu_bypass_disabled __read_mostly;
  89
  90 static int __init iommu_setup(char *str)
  91 {
  92         if (!str)
  93                 return -EINVAL;
  94
  95         while (*str) {
  96                 if (!strncmp(str, "nobypass", 8)) {
  97                         pnv_iommu_bypass_disabled = true;
  98                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
  99                         break;
 100                 }
 101                 str += strcspn(str, ",");
 102                 if (*str == ',')
 103                         str++;
 104         }
 105
 106         return 0;
 107 }
 108 early_param("iommu", iommu_setup);
 109
 110 /*
 111  * stdcix is only supposed to be used in hypervisor real mode as per
 112  * the architecture spec
 113  */
 114 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 115 {
 116         __asm__ __volatile__("stdcix %0,0,%1"
 117                 : : "r" (val), "r" (paddr) : "memory");
 118 }
 119
 120 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 121 {
 122         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 123                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 124 }
 125
 126 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 127 {
 128         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
 129                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 130                         __func__, pe_no, phb->hose->global_number);
 131                 return;
 132         }
 133
 134         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) {
 135                 pr_warn("%s: PE %d was assigned on PHB#%x\n",
 136                         __func__, pe_no, phb->hose->global_number);
 137                 return;
 138         }
 139
 140         phb->ioda.pe_array[pe_no].phb = phb;
 141         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 142 }
 143
 144 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
 145 {
 146         unsigned long pe;
 147
 148         do {
 149                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
 150                                         phb->ioda.total_pe, 0);
 151                 if (pe >= phb->ioda.total_pe)
 152                         return IODA_INVALID_PE;
 153         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 154
 155         phb->ioda.pe_array[pe].phb = phb;
 156         phb->ioda.pe_array[pe].pe_number = pe;
 157         return pe;
 158 }
 159
 160 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
 161 {
 162         WARN_ON(phb->ioda.pe_array[pe].pdev);
 163
 164         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
 165         clear_bit(pe, phb->ioda.pe_alloc);
 166 }
 167
 168 /* The default M64 BAR is shared by all PEs */
 169 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 170 {
 171         const char *desc;
 172         struct resource *r;
 173         s64 rc;
 174
 175         /* Configure the default M64 BAR */
 176         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 177                                          OPAL_M64_WINDOW_TYPE,
 178                                          phb->ioda.m64_bar_idx,
 179                                          phb->ioda.m64_base,
 180                                          0, /* unused */
 181                                          phb->ioda.m64_size);
 182         if (rc != OPAL_SUCCESS) {
 183                 desc = "configuring";
 184                 goto fail;
 185         }
 186
 187         /* Enable the default M64 BAR */
 188         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 189                                       OPAL_M64_WINDOW_TYPE,
 190                                       phb->ioda.m64_bar_idx,
 191                                       OPAL_ENABLE_M64_SPLIT);
 192         if (rc != OPAL_SUCCESS) {
 193                 desc = "enabling";
 194                 goto fail;
 195         }
 196
 197         /* Mark the M64 BAR assigned */
 198         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 199
 200         /*
 201          * Strip off the segment used by the reserved PE, which is
 202          * expected to be 0 or last one of PE capabicity.
 203          */
 204         r = &phb->hose->mem_resources[1];
 205         if (phb->ioda.reserved_pe == 0)
 206                 r->start += phb->ioda.m64_segsize;
 207         else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
 208                 r->end -= phb->ioda.m64_segsize;
 209         else
 210                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 211                         phb->ioda.reserved_pe);
 212
 213         return 0;
 214
 215 fail:
 216         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 217                 rc, desc, phb->ioda.m64_bar_idx);
 218         opal_pci_phb_mmio_enable(phb->opal_id,
 219                                  OPAL_M64_WINDOW_TYPE,
 220                                  phb->ioda.m64_bar_idx,
 221                                  OPAL_DISABLE_M64);
 222         return -EIO;
 223 }
 224
 225 static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb)
 226 {
 227         resource_size_t sgsz = phb->ioda.m64_segsize;
 228         struct pci_dev *pdev;
 229         struct resource *r;
 230         int base, step, i;
 231
 232         /*
 233          * Root bus always has full M64 range and root port has
 234          * M64 range used in reality. So we're checking root port
 235          * instead of root bus.
 236          */
 237         list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) {
 238                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 239                         r = &pdev->resource[PCI_BRIDGE_RESOURCES + i];
 240                         if (!r->parent ||
 241                             !pnv_pci_is_mem_pref_64(r->flags))
 242                                 continue;
 243
 244                         base = (r->start - phb->ioda.m64_base) / sgsz;
 245                         for (step = 0; step < resource_size(r) / sgsz; step++)
 246                                 pnv_ioda_reserve_pe(phb, base + step);
 247                 }
 248         }
 249 }
 250
 251 static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb,
 252                                  struct pci_bus *bus, int all)
 253 {
 254         resource_size_t segsz = phb->ioda.m64_segsize;
 255         struct pci_dev *pdev;
 256         struct resource *r;
 257         struct pnv_ioda_pe *master_pe, *pe;
 258         unsigned long size, *pe_alloc;
 259         bool found;
 260         int start, i, j;
 261
 262         /* Root bus shouldn't use M64 */
 263         if (pci_is_root_bus(bus))
 264                 return IODA_INVALID_PE;
 265
 266         /* We support only one M64 window on each bus */
 267         found = false;
 268         pci_bus_for_each_resource(bus, r, i) {
 269                 if (r && r->parent &&
 270                     pnv_pci_is_mem_pref_64(r->flags)) {
 271                         found = true;
 272                         break;
 273                 }
 274         }
 275
 276         /* No M64 window found ? */
 277         if (!found)
 278                 return IODA_INVALID_PE;
 279
 280         /* Allocate bitmap */
 281         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
 282         pe_alloc = kzalloc(size, GFP_KERNEL);
 283         if (!pe_alloc) {
 284                 pr_warn("%s: Out of memory !\n",
 285                         __func__);
 286                 return IODA_INVALID_PE;
 287         }
 288
 289         /*
 290          * Figure out reserved PE numbers by the PE
 291          * the its child PEs.
 292          */
 293         start = (r->start - phb->ioda.m64_base) / segsz;
 294         for (i = 0; i < resource_size(r) / segsz; i++)
 295                 set_bit(start + i, pe_alloc);
 296
 297         if (all)
 298                 goto done;
 299
 300         /*
 301          * If the PE doesn't cover all subordinate buses,
 302          * we need subtract from reserved PEs for children.
 303          */
 304         list_for_each_entry(pdev, &bus->devices, bus_list) {
 305                 if (!pdev->subordinate)
 306                         continue;
 307
 308                 pci_bus_for_each_resource(pdev->subordinate, r, i) {
 309                         if (!r || !r->parent ||
 310                             !pnv_pci_is_mem_pref_64(r->flags))
 311                                 continue;
 312
 313                         start = (r->start - phb->ioda.m64_base) / segsz;
 314                         for (j = 0; j < resource_size(r) / segsz ; j++)
 315                                 clear_bit(start + j, pe_alloc);
 316                 }
 317         }
 318
 319         /*
 320          * the current bus might not own M64 window and that's all
 321          * contributed by its child buses. For the case, we needn't
 322          * pick M64 dependent PE#.
 323          */
 324         if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
 325                 kfree(pe_alloc);
 326                 return IODA_INVALID_PE;
 327         }
 328
 329         /*
 330          * Figure out the master PE and put all slave PEs to master
 331          * PE's list to form compound PE.
 332          */
 333 done:
 334         master_pe = NULL;
 335         i = -1;
 336         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
 337                 phb->ioda.total_pe) {
 338                 pe = &phb->ioda.pe_array[i];
 339
 340                 if (!master_pe) {
 341                         pe->flags |= PNV_IODA_PE_MASTER;
 342                         INIT_LIST_HEAD(&pe->slaves);
 343                         master_pe = pe;
 344                 } else {
 345                         pe->flags |= PNV_IODA_PE_SLAVE;
 346                         pe->master = master_pe;
 347                         list_add_tail(&pe->list, &master_pe->slaves);
 348                 }
 349         }
 350
 351         kfree(pe_alloc);
 352         return master_pe->pe_number;
 353 }
 354
 355 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 356 {
 357         struct pci_controller *hose = phb->hose;
 358         struct device_node *dn = hose->dn;
 359         struct resource *res;
 360         const u32 *r;
 361         u64 pci_addr;
 362
 363         /* FIXME: Support M64 for P7IOC */
 364         if (phb->type != PNV_PHB_IODA2) {
 365                 pr_info("  Not support M64 window\n");
 366                 return;
 367         }
 368
 369         if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
 370                 pr_info("  Firmware too old to support M64 window\n");
 371                 return;
 372         }
 373
 374         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 375         if (!r) {
 376                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 377                         dn->full_name);
 378                 return;
 379         }
 380
 381         res = &hose->mem_resources[1];
 382         res->start = of_translate_address(dn, r + 2);
 383         res->end = res->start + of_read_number(r + 4, 2) - 1;
 384         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 385         pci_addr = of_read_number(r, 2);
 386         hose->mem_offset[1] = res->start - pci_addr;
 387
 388         phb->ioda.m64_size = resource_size(res);
 389         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
 390         phb->ioda.m64_base = pci_addr;
 391
 392         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 393                         res->start, res->end, pci_addr);
 394
 395         /* Use last M64 BAR to cover M64 window */
 396         phb->ioda.m64_bar_idx = 15;
 397         phb->init_m64 = pnv_ioda2_init_m64;
 398         phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
 399         phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
 400 }
 401
 402 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 403 {
 404         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 405         struct pnv_ioda_pe *slave;
 406         s64 rc;
 407
 408         /* Fetch master PE */
 409         if (pe->flags & PNV_IODA_PE_SLAVE) {
 410                 pe = pe->master;
 411                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 412                         return;
 413
 414                 pe_no = pe->pe_number;
 415         }
 416
 417         /* Freeze master PE */
 418         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 419                                      pe_no,
 420                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 421         if (rc != OPAL_SUCCESS) {
 422                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 423                         __func__, rc, phb->hose->global_number, pe_no);
 424                 return;
 425         }
 426
 427         /* Freeze slave PEs */
 428         if (!(pe->flags & PNV_IODA_PE_MASTER))
 429                 return;
 430
 431         list_for_each_entry(slave, &pe->slaves, list) {
 432                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 433                                              slave->pe_number,
 434                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 435                 if (rc != OPAL_SUCCESS)
 436                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 437                                 __func__, rc, phb->hose->global_number,
 438                                 slave->pe_number);
 439         }
 440 }
 441
 442 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 443 {
 444         struct pnv_ioda_pe *pe, *slave;
 445         s64 rc;
 446
 447         /* Find master PE */
 448         pe = &phb->ioda.pe_array[pe_no];
 449         if (pe->flags & PNV_IODA_PE_SLAVE) {
 450                 pe = pe->master;
 451                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 452                 pe_no = pe->pe_number;
 453         }
 454
 455         /* Clear frozen state for master PE */
 456         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 457         if (rc != OPAL_SUCCESS) {
 458                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 459                         __func__, rc, opt, phb->hose->global_number, pe_no);
 460                 return -EIO;
 461         }
 462
 463         if (!(pe->flags & PNV_IODA_PE_MASTER))
 464                 return 0;
 465
 466         /* Clear frozen state for slave PEs */
 467         list_for_each_entry(slave, &pe->slaves, list) {
 468                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 469                                              slave->pe_number,
 470                                              opt);
 471                 if (rc != OPAL_SUCCESS) {
 472                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 473                                 __func__, rc, opt, phb->hose->global_number,
 474                                 slave->pe_number);
 475                         return -EIO;
 476                 }
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 483 {
 484         struct pnv_ioda_pe *slave, *pe;
 485         u8 fstate, state;
 486         __be16 pcierr;
 487         s64 rc;
 488
 489         /* Sanity check on PE number */
 490         if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
 491                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 492
 493         /*
 494          * Fetch the master PE and the PE instance might be
 495          * not initialized yet.
 496          */
 497         pe = &phb->ioda.pe_array[pe_no];
 498         if (pe->flags & PNV_IODA_PE_SLAVE) {
 499                 pe = pe->master;
 500                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 501                 pe_no = pe->pe_number;
 502         }
 503
 504         /* Check the master PE */
 505         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 506                                         &state, &pcierr, NULL);
 507         if (rc != OPAL_SUCCESS) {
 508                 pr_warn("%s: Failure %lld getting "
 509                         "PHB#%x-PE#%x state\n",
 510                         __func__, rc,
 511                         phb->hose->global_number, pe_no);
 512                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 513         }
 514
 515         /* Check the slave PE */
 516         if (!(pe->flags & PNV_IODA_PE_MASTER))
 517                 return state;
 518
 519         list_for_each_entry(slave, &pe->slaves, list) {
 520                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 521                                                 slave->pe_number,
 522                                                 &fstate,
 523                                                 &pcierr,
 524                                                 NULL);
 525                 if (rc != OPAL_SUCCESS) {
 526                         pr_warn("%s: Failure %lld getting "
 527                                 "PHB#%x-PE#%x state\n",
 528                                 __func__, rc,
 529                                 phb->hose->global_number, slave->pe_number);
 530                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 531                 }
 532
 533                 /*
 534                  * Override the result based on the ascending
 535                  * priority.
 536                  */
 537                 if (fstate > state)
 538                         state = fstate;
 539         }
 540
 541         return state;
 542 }
 543
 544 /* Currently those 2 are only used when MSIs are enabled, this will change
 545  * but in the meantime, we need to protect them to avoid warnings
 546  */
 547 #ifdef CONFIG_PCI_MSI
 548 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 549 {
 550         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 551         struct pnv_phb *phb = hose->private_data;
 552         struct pci_dn *pdn = pci_get_pdn(dev);
 553
 554         if (!pdn)
 555                 return NULL;
 556         if (pdn->pe_number == IODA_INVALID_PE)
 557                 return NULL;
 558         return &phb->ioda.pe_array[pdn->pe_number];
 559 }
 560 #endif /* CONFIG_PCI_MSI */
 561
 562 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 563                                   struct pnv_ioda_pe *parent,
 564                                   struct pnv_ioda_pe *child,
 565                                   bool is_add)
 566 {
 567         const char *desc = is_add ? "adding" : "removing";
 568         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 569                               OPAL_REMOVE_PE_FROM_DOMAIN;
 570         struct pnv_ioda_pe *slave;
 571         long rc;
 572
 573         /* Parent PE affects child PE */
 574         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 575                                 child->pe_number, op);
 576         if (rc != OPAL_SUCCESS) {
 577                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 578                         rc, desc);
 579                 return -ENXIO;
 580         }
 581
 582         if (!(child->flags & PNV_IODA_PE_MASTER))
 583                 return 0;
 584
 585         /* Compound case: parent PE affects slave PEs */
 586         list_for_each_entry(slave, &child->slaves, list) {
 587                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 588                                         slave->pe_number, op);
 589                 if (rc != OPAL_SUCCESS) {
 590                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 591                                 rc, desc);
 592                         return -ENXIO;
 593                 }
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 600                               struct pnv_ioda_pe *pe,
 601                               bool is_add)
 602 {
 603         struct pnv_ioda_pe *slave;
 604         struct pci_dev *pdev = NULL;
 605         int ret;
 606
 607         /*
 608          * Clear PE frozen state. If it's master PE, we need
 609          * clear slave PE frozen state as well.
 610          */
 611         if (is_add) {
 612                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 613                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 614                 if (pe->flags & PNV_IODA_PE_MASTER) {
 615                         list_for_each_entry(slave, &pe->slaves, list)
 616                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 617                                                           slave->pe_number,
 618                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 619                 }
 620         }
 621
 622         /*
 623          * Associate PE in PELT. We need add the PE into the
 624          * corresponding PELT-V as well. Otherwise, the error
 625          * originated from the PE might contribute to other
 626          * PEs.
 627          */
 628         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 629         if (ret)
 630                 return ret;
 631
 632         /* For compound PEs, any one affects all of them */
 633         if (pe->flags & PNV_IODA_PE_MASTER) {
 634                 list_for_each_entry(slave, &pe->slaves, list) {
 635                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 636                         if (ret)
 637                                 return ret;
 638                 }
 639         }
 640
 641         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 642                 pdev = pe->pbus->self;
 643         else if (pe->flags & PNV_IODA_PE_DEV)
 644                 pdev = pe->pdev->bus->self;
 645 #ifdef CONFIG_PCI_IOV
 646         else if (pe->flags & PNV_IODA_PE_VF)
 647                 pdev = pe->parent_dev->bus->self;
 648 #endif /* CONFIG_PCI_IOV */
 649         while (pdev) {
 650                 struct pci_dn *pdn = pci_get_pdn(pdev);
 651                 struct pnv_ioda_pe *parent;
 652
 653                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 654                         parent = &phb->ioda.pe_array[pdn->pe_number];
 655                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 656                         if (ret)
 657                                 return ret;
 658                 }
 659
 660                 pdev = pdev->bus->self;
 661         }
 662
 663         return 0;
 664 }
 665
 666 #ifdef CONFIG_PCI_IOV
 667 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 668 {
 669         struct pci_dev *parent;
 670         uint8_t bcomp, dcomp, fcomp;
 671         int64_t rc;
 672         long rid_end, rid;
 673
 674         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 675         if (pe->pbus) {
 676                 int count;
 677
 678                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 679                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 680                 parent = pe->pbus->self;
 681                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 682                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 683                 else
 684                         count = 1;
 685
 686                 switch(count) {
 687                 case  1: bcomp = OpalPciBusAll;         break;
 688                 case  2: bcomp = OpalPciBus7Bits;       break;
 689                 case  4: bcomp = OpalPciBus6Bits;       break;
 690                 case  8: bcomp = OpalPciBus5Bits;       break;
 691                 case 16: bcomp = OpalPciBus4Bits;       break;
 692                 case 32: bcomp = OpalPciBus3Bits;       break;
 693                 default:
 694                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 695                                 count);
 696                         /* Do an exact match only */
 697                         bcomp = OpalPciBusAll;
 698                 }
 699                 rid_end = pe->rid + (count << 8);
 700         } else {
 701                 if (pe->flags & PNV_IODA_PE_VF)
 702                         parent = pe->parent_dev;
 703                 else
 704                         parent = pe->pdev->bus->self;
 705                 bcomp = OpalPciBusAll;
 706                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 707                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 708                 rid_end = pe->rid + 1;
 709         }
 710
 711         /* Clear the reverse map */
 712         for (rid = pe->rid; rid < rid_end; rid++)
 713                 phb->ioda.pe_rmap[rid] = 0;
 714
 715         /* Release from all parents PELT-V */
 716         while (parent) {
 717                 struct pci_dn *pdn = pci_get_pdn(parent);
 718                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 719                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 720                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 721                         /* XXX What to do in case of error ? */
 722                 }
 723                 parent = parent->bus->self;
 724         }
 725
 726         opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number,
 727                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 728
 729         /* Disassociate PE in PELT */
 730         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 731                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 732         if (rc)
 733                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 734         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 735                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 736         if (rc)
 737                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 738
 739         pe->pbus = NULL;
 740         pe->pdev = NULL;
 741         pe->parent_dev = NULL;
 742
 743         return 0;
 744 }
 745 #endif /* CONFIG_PCI_IOV */
 746
 747 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 748 {
 749         struct pci_dev *parent;
 750         uint8_t bcomp, dcomp, fcomp;
 751         long rc, rid_end, rid;
 752
 753         /* Bus validation ? */
 754         if (pe->pbus) {
 755                 int count;
 756
 757                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 758                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 759                 parent = pe->pbus->self;
 760                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 761                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 762                 else
 763                         count = 1;
 764
 765                 switch(count) {
 766                 case  1: bcomp = OpalPciBusAll;         break;
 767                 case  2: bcomp = OpalPciBus7Bits;       break;
 768                 case  4: bcomp = OpalPciBus6Bits;       break;
 769                 case  8: bcomp = OpalPciBus5Bits;       break;
 770                 case 16: bcomp = OpalPciBus4Bits;       break;
 771                 case 32: bcomp = OpalPciBus3Bits;       break;
 772                 default:
 773                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 774                                 count);
 775                         /* Do an exact match only */
 776                         bcomp = OpalPciBusAll;
 777                 }
 778                 rid_end = pe->rid + (count << 8);
 779         } else {
 780 #ifdef CONFIG_PCI_IOV
 781                 if (pe->flags & PNV_IODA_PE_VF)
 782                         parent = pe->parent_dev;
 783                 else
 784 #endif /* CONFIG_PCI_IOV */
 785                         parent = pe->pdev->bus->self;
 786                 bcomp = OpalPciBusAll;
 787                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 788                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 789                 rid_end = pe->rid + 1;
 790         }
 791
 792         /*
 793          * Associate PE in PELT. We need add the PE into the
 794          * corresponding PELT-V as well. Otherwise, the error
 795          * originated from the PE might contribute to other
 796          * PEs.
 797          */
 798         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 799                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 800         if (rc) {
 801                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 802                 return -ENXIO;
 803         }
 804
 805         /* Configure PELTV */
 806         pnv_ioda_set_peltv(phb, pe, true);
 807
 808         /* Setup reverse map */
 809         for (rid = pe->rid; rid < rid_end; rid++)
 810                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 811
 812         /* Setup one MVTs on IODA1 */
 813         if (phb->type != PNV_PHB_IODA1) {
 814                 pe->mve_number = 0;
 815                 goto out;
 816         }
 817
 818         pe->mve_number = pe->pe_number;
 819         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 820         if (rc != OPAL_SUCCESS) {
 821                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 822                        rc, pe->mve_number);
 823                 pe->mve_number = -1;
 824         } else {
 825                 rc = opal_pci_set_mve_enable(phb->opal_id,
 826                                              pe->mve_number, OPAL_ENABLE_MVE);
 827                 if (rc) {
 828                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 829                                rc, pe->mve_number);
 830                         pe->mve_number = -1;
 831                 }
 832         }
 833
 834 out:
 835         return 0;
 836 }
 837
 838 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 839                                        struct pnv_ioda_pe *pe)
 840 {
 841         struct pnv_ioda_pe *lpe;
 842
 843         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 844                 if (lpe->dma_weight < pe->dma_weight) {
 845                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 846                         return;
 847                 }
 848         }
 849         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 850 }
 851
 852 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 853 {
 854         /* This is quite simplistic. The "base" weight of a device
 855          * is 10. 0 means no DMA is to be accounted for it.
 856          */
 857
 858         /* If it's a bridge, no DMA */
 859         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 860                 return 0;
 861
 862         /* Reduce the weight of slow USB controllers */
 863         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 864             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 865             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 866                 return 3;
 867
 868         /* Increase the weight of RAID (includes Obsidian) */
 869         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 870                 return 15;
 871
 872         /* Default */
 873         return 10;
 874 }
 875
 876 #ifdef CONFIG_PCI_IOV
 877 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 878 {
 879         struct pci_dn *pdn = pci_get_pdn(dev);
 880         int i;
 881         struct resource *res, res2;
 882         resource_size_t size;
 883         u16 num_vfs;
 884
 885         if (!dev->is_physfn)
 886                 return -EINVAL;
 887
 888         /*
 889          * "offset" is in VFs.  The M64 windows are sized so that when they
 890          * are segmented, each segment is the same size as the IOV BAR.
 891          * Each segment is in a separate PE, and the high order bits of the
 892          * address are the PE number.  Therefore, each VF's BAR is in a
 893          * separate PE, and changing the IOV BAR start address changes the
 894          * range of PEs the VFs are in.
 895          */
 896         num_vfs = pdn->num_vfs;
 897         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 898                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 899                 if (!res->flags || !res->parent)
 900                         continue;
 901
 902                 if (!pnv_pci_is_mem_pref_64(res->flags))
 903                         continue;
 904
 905                 /*
 906                  * The actual IOV BAR range is determined by the start address
 907                  * and the actual size for num_vfs VFs BAR.  This check is to
 908                  * make sure that after shifting, the range will not overlap
 909                  * with another device.
 910                  */
 911                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 912                 res2.flags = res->flags;
 913                 res2.start = res->start + (size * offset);
 914                 res2.end = res2.start + (size * num_vfs) - 1;
 915
 916                 if (res2.end > res->end) {
 917                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 918                                 i, &res2, res, num_vfs, offset);
 919                         return -EBUSY;
 920                 }
 921         }
 922
 923         /*
 924          * After doing so, there would be a "hole" in the /proc/iomem when
 925          * offset is a positive value. It looks like the device return some
 926          * mmio back to the system, which actually no one could use it.
 927          */
 928         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 929                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 930                 if (!res->flags || !res->parent)
 931                         continue;
 932
 933                 if (!pnv_pci_is_mem_pref_64(res->flags))
 934                         continue;
 935
 936                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 937                 res2 = *res;
 938                 res->start += size * offset;
 939
 940                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
 941                          i, &res2, res, num_vfs, offset);
 942                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 943         }
 944         return 0;
 945 }
 946 #endif /* CONFIG_PCI_IOV */
 947
 948 #if 0
 949 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 950 {
 951         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 952         struct pnv_phb *phb = hose->private_data;
 953         struct pci_dn *pdn = pci_get_pdn(dev);
 954         struct pnv_ioda_pe *pe;
 955         int pe_num;
 956
 957         if (!pdn) {
 958                 pr_err("%s: Device tree node not associated properly\n",
 959                            pci_name(dev));
 960                 return NULL;
 961         }
 962         if (pdn->pe_number != IODA_INVALID_PE)
 963                 return NULL;
 964
 965         /* PE#0 has been pre-set */
 966         if (dev->bus->number == 0)
 967                 pe_num = 0;
 968         else
 969                 pe_num = pnv_ioda_alloc_pe(phb);
 970         if (pe_num == IODA_INVALID_PE) {
 971                 pr_warning("%s: Not enough PE# available, disabling device\n",
 972                            pci_name(dev));
 973                 return NULL;
 974         }
 975
 976         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 977          * pointer in the PE data structure, both should be destroyed at the
 978          * same time. However, this needs to be looked at more closely again
 979          * once we actually start removing things (Hotplug, SR-IOV, ...)
 980          *
 981          * At some point we want to remove the PDN completely anyways
 982          */
 983         pe = &phb->ioda.pe_array[pe_num];
 984         pci_dev_get(dev);
 985         pdn->pcidev = dev;
 986         pdn->pe_number = pe_num;
 987         pe->pdev = dev;
 988         pe->pbus = NULL;
 989         pe->tce32_seg = -1;
 990         pe->mve_number = -1;
 991         pe->rid = dev->bus->number << 8 | pdn->devfn;
 992
 993         pe_info(pe, "Associated device to PE\n");
 994
 995         if (pnv_ioda_configure_pe(phb, pe)) {
 996                 /* XXX What do we do here ? */
 997                 if (pe_num)
 998                         pnv_ioda_free_pe(phb, pe_num);
 999                 pdn->pe_number = IODA_INVALID_PE;
1000                 pe->pdev = NULL;
1001                 pci_dev_put(dev);
1002                 return NULL;
1003         }
1004
1005         /* Assign a DMA weight to the device */
1006         pe->dma_weight = pnv_ioda_dma_weight(dev);
1007         if (pe->dma_weight != 0) {
1008                 phb->ioda.dma_weight += pe->dma_weight;
1009                 phb->ioda.dma_pe_count++;
1010         }
1011
1012         /* Link the PE */
1013         pnv_ioda_link_pe_by_weight(phb, pe);
1014
1015         return pe;
1016 }
1017 #endif /* Useful for SRIOV case */
1018
1019 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1020 {
1021         struct pci_dev *dev;
1022
1023         list_for_each_entry(dev, &bus->devices, bus_list) {
1024                 struct pci_dn *pdn = pci_get_pdn(dev);
1025
1026                 if (pdn == NULL) {
1027                         pr_warn("%s: No device node associated with device !\n",
1028                                 pci_name(dev));
1029                         continue;
1030                 }
1031                 pdn->pcidev = dev;
1032                 pdn->pe_number = pe->pe_number;
1033                 pe->dma_weight += pnv_ioda_dma_weight(dev);
1034                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1035                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1036         }
1037 }
1038
1039 /*
1040  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1041  * single PCI bus. Another one that contains the primary PCI bus and its
1042  * subordinate PCI devices and buses. The second type of PE is normally
1043  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1044  */
1045 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
1046 {
1047         struct pci_controller *hose = pci_bus_to_host(bus);
1048         struct pnv_phb *phb = hose->private_data;
1049         struct pnv_ioda_pe *pe;
1050         int pe_num = IODA_INVALID_PE;
1051
1052         /* Check if PE is determined by M64 */
1053         if (phb->pick_m64_pe)
1054                 pe_num = phb->pick_m64_pe(phb, bus, all);
1055
1056         /* The PE number isn't pinned by M64 */
1057         if (pe_num == IODA_INVALID_PE)
1058                 pe_num = pnv_ioda_alloc_pe(phb);
1059
1060         if (pe_num == IODA_INVALID_PE) {
1061                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1062                         __func__, pci_domain_nr(bus), bus->number);
1063                 return;
1064         }
1065
1066         pe = &phb->ioda.pe_array[pe_num];
1067         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1068         pe->pbus = bus;
1069         pe->pdev = NULL;
1070         pe->tce32_seg = -1;
1071         pe->mve_number = -1;
1072         pe->rid = bus->busn_res.start << 8;
1073         pe->dma_weight = 0;
1074
1075         if (all)
1076                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1077                         bus->busn_res.start, bus->busn_res.end, pe_num);
1078         else
1079                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1080                         bus->busn_res.start, pe_num);
1081
1082         if (pnv_ioda_configure_pe(phb, pe)) {
1083                 /* XXX What do we do here ? */
1084                 if (pe_num)
1085                         pnv_ioda_free_pe(phb, pe_num);
1086                 pe->pbus = NULL;
1087                 return;
1088         }
1089
1090         pe->tce32_table = kzalloc_node(sizeof(struct iommu_table),
1091                         GFP_KERNEL, hose->node);
1092         pe->tce32_table->data = pe;
1093
1094         /* Associate it with all child devices */
1095         pnv_ioda_setup_same_PE(bus, pe);
1096
1097         /* Put PE to the list */
1098         list_add_tail(&pe->list, &phb->ioda.pe_list);
1099
1100         /* Account for one DMA PE if at least one DMA capable device exist
1101          * below the bridge
1102          */
1103         if (pe->dma_weight != 0) {
1104                 phb->ioda.dma_weight += pe->dma_weight;
1105                 phb->ioda.dma_pe_count++;
1106         }
1107
1108         /* Link the PE */
1109         pnv_ioda_link_pe_by_weight(phb, pe);
1110 }
1111
1112 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1113 {
1114         struct pci_dev *dev;
1115
1116         pnv_ioda_setup_bus_PE(bus, 0);
1117
1118         list_for_each_entry(dev, &bus->devices, bus_list) {
1119                 if (dev->subordinate) {
1120                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1121                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
1122                         else
1123                                 pnv_ioda_setup_PEs(dev->subordinate);
1124                 }
1125         }
1126 }
1127
1128 /*
1129  * Configure PEs so that the downstream PCI buses and devices
1130  * could have their associated PE#. Unfortunately, we didn't
1131  * figure out the way to identify the PLX bridge yet. So we
1132  * simply put the PCI bus and the subordinate behind the root
1133  * port to PE# here. The game rule here is expected to be changed
1134  * as soon as we can detected PLX bridge correctly.
1135  */
1136 static void pnv_pci_ioda_setup_PEs(void)
1137 {
1138         struct pci_controller *hose, *tmp;
1139         struct pnv_phb *phb;
1140
1141         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1142                 phb = hose->private_data;
1143
1144                 /* M64 layout might affect PE allocation */
1145                 if (phb->reserve_m64_pe)
1146                         phb->reserve_m64_pe(phb);
1147
1148                 pnv_ioda_setup_PEs(hose->bus);
1149         }
1150 }
1151
1152 #ifdef CONFIG_PCI_IOV
1153 static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1154 {
1155         struct pci_bus        *bus;
1156         struct pci_controller *hose;
1157         struct pnv_phb        *phb;
1158         struct pci_dn         *pdn;
1159         int                    i;
1160
1161         bus = pdev->bus;
1162         hose = pci_bus_to_host(bus);
1163         phb = hose->private_data;
1164         pdn = pci_get_pdn(pdev);
1165
1166         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1167                 if (pdn->m64_wins[i] == IODA_INVALID_M64)
1168                         continue;
1169                 opal_pci_phb_mmio_enable(phb->opal_id,
1170                                 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i], 0);
1171                 clear_bit(pdn->m64_wins[i], &phb->ioda.m64_bar_alloc);
1172                 pdn->m64_wins[i] = IODA_INVALID_M64;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev)
1179 {
1180         struct pci_bus        *bus;
1181         struct pci_controller *hose;
1182         struct pnv_phb        *phb;
1183         struct pci_dn         *pdn;
1184         unsigned int           win;
1185         struct resource       *res;
1186         int                    i;
1187         int64_t                rc;
1188
1189         bus = pdev->bus;
1190         hose = pci_bus_to_host(bus);
1191         phb = hose->private_data;
1192         pdn = pci_get_pdn(pdev);
1193
1194         /* Initialize the m64_wins to IODA_INVALID_M64 */
1195         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1196                 pdn->m64_wins[i] = IODA_INVALID_M64;
1197
1198         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1199                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1200                 if (!res->flags || !res->parent)
1201                         continue;
1202
1203                 if (!pnv_pci_is_mem_pref_64(res->flags))
1204                         continue;
1205
1206                 do {
1207                         win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1208                                         phb->ioda.m64_bar_idx + 1, 0);
1209
1210                         if (win >= phb->ioda.m64_bar_idx + 1)
1211                                 goto m64_failed;
1212                 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1213
1214                 pdn->m64_wins[i] = win;
1215
1216                 /* Map the M64 here */
1217                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1218                                                  OPAL_M64_WINDOW_TYPE,
1219                                                  pdn->m64_wins[i],
1220                                                  res->start,
1221                                                  0, /* unused */
1222                                                  resource_size(res));
1223                 if (rc != OPAL_SUCCESS) {
1224                         dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1225                                 win, rc);
1226                         goto m64_failed;
1227                 }
1228
1229                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1230                                 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i], 1);
1231                 if (rc != OPAL_SUCCESS) {
1232                         dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1233                                 win, rc);
1234                         goto m64_failed;
1235                 }
1236         }
1237         return 0;
1238
1239 m64_failed:
1240         pnv_pci_vf_release_m64(pdev);
1241         return -EBUSY;
1242 }
1243
1244 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1245 {
1246         struct pci_bus        *bus;
1247         struct pci_controller *hose;
1248         struct pnv_phb        *phb;
1249         struct iommu_table    *tbl;
1250         unsigned long         addr;
1251         int64_t               rc;
1252
1253         bus = dev->bus;
1254         hose = pci_bus_to_host(bus);
1255         phb = hose->private_data;
1256         tbl = pe->tce32_table;
1257         addr = tbl->it_base;
1258
1259         opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1260                                    pe->pe_number << 1, 1, __pa(addr),
1261                                    0, 0x1000);
1262
1263         rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1264                                         pe->pe_number,
1265                                         (pe->pe_number << 1) + 1,
1266                                         pe->tce_bypass_base,
1267                                         0);
1268         if (rc)
1269                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1270
1271         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1272         free_pages(addr, get_order(TCE32_TABLE_SIZE));
1273         pe->tce32_table = NULL;
1274 }
1275
1276 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1277 {
1278         struct pci_bus        *bus;
1279         struct pci_controller *hose;
1280         struct pnv_phb        *phb;
1281         struct pnv_ioda_pe    *pe, *pe_n;
1282         struct pci_dn         *pdn;
1283
1284         bus = pdev->bus;
1285         hose = pci_bus_to_host(bus);
1286         phb = hose->private_data;
1287
1288         if (!pdev->is_physfn)
1289                 return;
1290
1291         pdn = pci_get_pdn(pdev);
1292         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1293                 if (pe->parent_dev != pdev)
1294                         continue;
1295
1296                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1297
1298                 /* Remove from list */
1299                 mutex_lock(&phb->ioda.pe_list_mutex);
1300                 list_del(&pe->list);
1301                 mutex_unlock(&phb->ioda.pe_list_mutex);
1302
1303                 pnv_ioda_deconfigure_pe(phb, pe);
1304
1305                 pnv_ioda_free_pe(phb, pe->pe_number);
1306         }
1307 }
1308
1309 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1310 {
1311         struct pci_bus        *bus;
1312         struct pci_controller *hose;
1313         struct pnv_phb        *phb;
1314         struct pci_dn         *pdn;
1315         struct pci_sriov      *iov;
1316         u16 num_vfs;
1317
1318         bus = pdev->bus;
1319         hose = pci_bus_to_host(bus);
1320         phb = hose->private_data;
1321         pdn = pci_get_pdn(pdev);
1322         iov = pdev->sriov;
1323         num_vfs = pdn->num_vfs;
1324
1325         /* Release VF PEs */
1326         pnv_ioda_release_vf_PE(pdev);
1327
1328         if (phb->type == PNV_PHB_IODA2) {
1329                 pnv_pci_vf_resource_shift(pdev, -pdn->offset);
1330
1331                 /* Release M64 windows */
1332                 pnv_pci_vf_release_m64(pdev);
1333
1334                 /* Release PE numbers */
1335                 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1336                 pdn->offset = 0;
1337         }
1338 }
1339
1340 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1341                                        struct pnv_ioda_pe *pe);
1342 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1343 {
1344         struct pci_bus        *bus;
1345         struct pci_controller *hose;
1346         struct pnv_phb        *phb;
1347         struct pnv_ioda_pe    *pe;
1348         int                    pe_num;
1349         u16                    vf_index;
1350         struct pci_dn         *pdn;
1351
1352         bus = pdev->bus;
1353         hose = pci_bus_to_host(bus);
1354         phb = hose->private_data;
1355         pdn = pci_get_pdn(pdev);
1356
1357         if (!pdev->is_physfn)
1358                 return;
1359
1360         /* Reserve PE for each VF */
1361         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1362                 pe_num = pdn->offset + vf_index;
1363
1364                 pe = &phb->ioda.pe_array[pe_num];
1365                 pe->pe_number = pe_num;
1366                 pe->phb = phb;
1367                 pe->flags = PNV_IODA_PE_VF;
1368                 pe->pbus = NULL;
1369                 pe->parent_dev = pdev;
1370                 pe->tce32_seg = -1;
1371                 pe->mve_number = -1;
1372                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1373                            pci_iov_virtfn_devfn(pdev, vf_index);
1374
1375                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1376                         hose->global_number, pdev->bus->number,
1377                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1378                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1379
1380                 if (pnv_ioda_configure_pe(phb, pe)) {
1381                         /* XXX What do we do here ? */
1382                         if (pe_num)
1383                                 pnv_ioda_free_pe(phb, pe_num);
1384                         pe->pdev = NULL;
1385                         continue;
1386                 }
1387
1388                 pe->tce32_table = kzalloc_node(sizeof(struct iommu_table),
1389                                 GFP_KERNEL, hose->node);
1390                 pe->tce32_table->data = pe;
1391
1392                 /* Put PE to the list */
1393                 mutex_lock(&phb->ioda.pe_list_mutex);
1394                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1395                 mutex_unlock(&phb->ioda.pe_list_mutex);
1396
1397                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1398         }
1399 }
1400
1401 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1402 {
1403         struct pci_bus        *bus;
1404         struct pci_controller *hose;
1405         struct pnv_phb        *phb;
1406         struct pci_dn         *pdn;
1407         int                    ret;
1408
1409         bus = pdev->bus;
1410         hose = pci_bus_to_host(bus);
1411         phb = hose->private_data;
1412         pdn = pci_get_pdn(pdev);
1413
1414         if (phb->type == PNV_PHB_IODA2) {
1415                 /* Calculate available PE for required VFs */
1416                 mutex_lock(&phb->ioda.pe_alloc_mutex);
1417                 pdn->offset = bitmap_find_next_zero_area(
1418                         phb->ioda.pe_alloc, phb->ioda.total_pe,
1419                         0, num_vfs, 0);
1420                 if (pdn->offset >= phb->ioda.total_pe) {
1421                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1422                         dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1423                         pdn->offset = 0;
1424                         return -EBUSY;
1425                 }
1426                 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1427                 pdn->num_vfs = num_vfs;
1428                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1429
1430                 /* Assign M64 window accordingly */
1431                 ret = pnv_pci_vf_assign_m64(pdev);
1432                 if (ret) {
1433                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1434                         goto m64_failed;
1435                 }
1436
1437                 /*
1438                  * When using one M64 BAR to map one IOV BAR, we need to shift
1439                  * the IOV BAR according to the PE# allocated to the VFs.
1440                  * Otherwise, the PE# for the VF will conflict with others.
1441                  */
1442                 ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1443                 if (ret)
1444                         goto m64_failed;
1445         }
1446
1447         /* Setup VF PEs */
1448         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1449
1450         return 0;
1451
1452 m64_failed:
1453         bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1454         pdn->offset = 0;
1455
1456         return ret;
1457 }
1458
1459 int pcibios_sriov_disable(struct pci_dev *pdev)
1460 {
1461         pnv_pci_sriov_disable(pdev);
1462
1463         /* Release PCI data */
1464         remove_dev_pci_data(pdev);
1465         return 0;
1466 }
1467
1468 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1469 {
1470         /* Allocate PCI data */
1471         add_dev_pci_data(pdev);
1472
1473         pnv_pci_sriov_enable(pdev, num_vfs);
1474         return 0;
1475 }
1476 #endif /* CONFIG_PCI_IOV */
1477
1478 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1479 {
1480         struct pci_dn *pdn = pci_get_pdn(pdev);
1481         struct pnv_ioda_pe *pe;
1482
1483         /*
1484          * The function can be called while the PE#
1485          * hasn't been assigned. Do nothing for the
1486          * case.
1487          */
1488         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1489                 return;
1490
1491         pe = &phb->ioda.pe_array[pdn->pe_number];
1492         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1493         set_iommu_table_base_and_group(&pdev->dev, pe->tce32_table);
1494 }
1495
1496 static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
1497                                      struct pci_dev *pdev, u64 dma_mask)
1498 {
1499         struct pci_dn *pdn = pci_get_pdn(pdev);
1500         struct pnv_ioda_pe *pe;
1501         uint64_t top;
1502         bool bypass = false;
1503
1504         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1505                 return -ENODEV;;
1506
1507         pe = &phb->ioda.pe_array[pdn->pe_number];
1508         if (pe->tce_bypass_enabled) {
1509                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1510                 bypass = (dma_mask >= top);
1511         }
1512
1513         if (bypass) {
1514                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1515                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1516                 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1517         } else {
1518                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1519                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1520                 set_iommu_table_base(&pdev->dev, pe->tce32_table);
1521         }
1522         *pdev->dev.dma_mask = dma_mask;
1523         return 0;
1524 }
1525
1526 static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb,
1527                                               struct pci_dev *pdev)
1528 {
1529         struct pci_dn *pdn = pci_get_pdn(pdev);
1530         struct pnv_ioda_pe *pe;
1531         u64 end, mask;
1532
1533         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1534                 return 0;
1535
1536         pe = &phb->ioda.pe_array[pdn->pe_number];
1537         if (!pe->tce_bypass_enabled)
1538                 return __dma_get_required_mask(&pdev->dev);
1539
1540
1541         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1542         mask = 1ULL << (fls64(end) - 1);
1543         mask += mask - 1;
1544
1545         return mask;
1546 }
1547
1548 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1549                                    struct pci_bus *bus,
1550                                    bool add_to_iommu_group)
1551 {
1552         struct pci_dev *dev;
1553
1554         list_for_each_entry(dev, &bus->devices, bus_list) {
1555                 if (add_to_iommu_group)
1556                         set_iommu_table_base_and_group(&dev->dev,
1557                                                        pe->tce32_table);
1558                 else
1559                         set_iommu_table_base(&dev->dev, pe->tce32_table);
1560
1561                 if (dev->subordinate)
1562                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1563                                                add_to_iommu_group);
1564         }
1565 }
1566
1567 static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe,
1568                                          struct iommu_table *tbl,
1569                                          __be64 *startp, __be64 *endp, bool rm)
1570 {
1571         __be64 __iomem *invalidate = rm ?
1572                 (__be64 __iomem *)pe->tce_inval_reg_phys :
1573                 (__be64 __iomem *)tbl->it_index;
1574         unsigned long start, end, inc;
1575         const unsigned shift = tbl->it_page_shift;
1576
1577         start = __pa(startp);
1578         end = __pa(endp);
1579
1580         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1581         if (tbl->it_busno) {
1582                 start <<= shift;
1583                 end <<= shift;
1584                 inc = 128ull << shift;
1585                 start |= tbl->it_busno;
1586                 end |= tbl->it_busno;
1587         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1588                 /* p7ioc-style invalidation, 2 TCEs per write */
1589                 start |= (1ull << 63);
1590                 end |= (1ull << 63);
1591                 inc = 16;
1592         } else {
1593                 /* Default (older HW) */
1594                 inc = 128;
1595         }
1596
1597         end |= inc - 1; /* round up end to be different than start */
1598
1599         mb(); /* Ensure above stores are visible */
1600         while (start <= end) {
1601                 if (rm)
1602                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1603                 else
1604                         __raw_writeq(cpu_to_be64(start), invalidate);
1605                 start += inc;
1606         }
1607
1608         /*
1609          * The iommu layer will do another mb() for us on build()
1610          * and we don't care on free()
1611          */
1612 }
1613
1614 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
1615                                          struct iommu_table *tbl,
1616                                          __be64 *startp, __be64 *endp, bool rm)
1617 {
1618         unsigned long start, end, inc;
1619         __be64 __iomem *invalidate = rm ?
1620                 (__be64 __iomem *)pe->tce_inval_reg_phys :
1621                 (__be64 __iomem *)tbl->it_index;
1622         const unsigned shift = tbl->it_page_shift;
1623
1624         /* We'll invalidate DMA address in PE scope */
1625         start = 0x2ull << 60;
1626         start |= (pe->pe_number & 0xFF);
1627         end = start;
1628
1629         /* Figure out the start, end and step */
1630         inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
1631         start |= (inc << shift);
1632         inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
1633         end |= (inc << shift);
1634         inc = (0x1ull << shift);
1635         mb();
1636
1637         while (start <= end) {
1638                 if (rm)
1639                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1640                 else
1641                         __raw_writeq(cpu_to_be64(start), invalidate);
1642                 start += inc;
1643         }
1644 }
1645
1646 void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
1647                                  __be64 *startp, __be64 *endp, bool rm)
1648 {
1649         struct pnv_ioda_pe *pe = tbl->data;
1650         struct pnv_phb *phb = pe->phb;
1651
1652         if (phb->type == PNV_PHB_IODA1)
1653                 pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm);
1654         else
1655                 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm);
1656 }
1657
1658 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1659                                       struct pnv_ioda_pe *pe, unsigned int base,
1660                                       unsigned int segs)
1661 {
1662
1663         struct page *tce_mem = NULL;
1664         const __be64 *swinvp;
1665         struct iommu_table *tbl;
1666         unsigned int i;
1667         int64_t rc;
1668         void *addr;
1669
1670         /* XXX FIXME: Handle 64-bit only DMA devices */
1671         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1672         /* XXX FIXME: Allocate multi-level tables on PHB3 */
1673
1674         /* We shouldn't already have a 32-bit DMA associated */
1675         if (WARN_ON(pe->tce32_seg >= 0))
1676                 return;
1677
1678         /* Grab a 32-bit TCE table */
1679         pe->tce32_seg = base;
1680         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1681                 (base << 28), ((base + segs) << 28) - 1);
1682
1683         /* XXX Currently, we allocate one big contiguous table for the
1684          * TCEs. We only really need one chunk per 256M of TCE space
1685          * (ie per segment) but that's an optimization for later, it
1686          * requires some added smarts with our get/put_tce implementation
1687          */
1688         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1689                                    get_order(TCE32_TABLE_SIZE * segs));
1690         if (!tce_mem) {
1691                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1692                 goto fail;
1693         }
1694         addr = page_address(tce_mem);
1695         memset(addr, 0, TCE32_TABLE_SIZE * segs);
1696
1697         /* Configure HW */
1698         for (i = 0; i < segs; i++) {
1699                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1700                                               pe->pe_number,
1701                                               base + i, 1,
1702                                               __pa(addr) + TCE32_TABLE_SIZE * i,
1703                                               TCE32_TABLE_SIZE, 0x1000);
1704                 if (rc) {
1705                         pe_err(pe, " Failed to configure 32-bit TCE table,"
1706                                " err %ld\n", rc);
1707                         goto fail;
1708                 }
1709         }
1710
1711         /* Setup linux iommu table */
1712         tbl = pe->tce32_table;
1713         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
1714                                   base << 28, IOMMU_PAGE_SHIFT_4K);
1715
1716         /* OPAL variant of P7IOC SW invalidated TCEs */
1717         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
1718         if (swinvp) {
1719                 /* We need a couple more fields -- an address and a data
1720                  * to or.  Since the bus is only printed out on table free
1721                  * errors, and on the first pass the data will be a relative
1722                  * bus number, print that out instead.
1723                  */
1724                 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
1725                 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
1726                                 8);
1727                 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
1728                                  TCE_PCI_SWINV_FREE   |
1729                                  TCE_PCI_SWINV_PAIR);
1730         }
1731         iommu_init_table(tbl, phb->hose->node);
1732
1733         if (pe->flags & PNV_IODA_PE_DEV) {
1734                 iommu_register_group(tbl, phb->hose->global_number,
1735                                      pe->pe_number);
1736                 set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
1737         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) {
1738                 iommu_register_group(tbl, phb->hose->global_number,
1739                                      pe->pe_number);
1740                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
1741         } else if (pe->flags & PNV_IODA_PE_VF) {
1742                 iommu_register_group(tbl, phb->hose->global_number,
1743                                      pe->pe_number);
1744         }
1745
1746         return;
1747  fail:
1748         /* XXX Failure: Try to fallback to 64-bit only ? */
1749         if (pe->tce32_seg >= 0)
1750                 pe->tce32_seg = -1;
1751         if (tce_mem)
1752                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
1753 }
1754
1755 static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
1756 {
1757         struct pnv_ioda_pe *pe = tbl->data;
1758         uint16_t window_id = (pe->pe_number << 1 ) + 1;
1759         int64_t rc;
1760
1761         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1762         if (enable) {
1763                 phys_addr_t top = memblock_end_of_DRAM();
1764
1765                 top = roundup_pow_of_two(top);
1766                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1767                                                      pe->pe_number,
1768                                                      window_id,
1769                                                      pe->tce_bypass_base,
1770                                                      top);
1771         } else {
1772                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1773                                                      pe->pe_number,
1774                                                      window_id,
1775                                                      pe->tce_bypass_base,
1776                                                      0);
1777
1778                 /*
1779                  * EEH needs the mapping between IOMMU table and group
1780                  * of those VFIO/KVM pass-through devices. We can postpone
1781                  * resetting DMA ops until the DMA mask is configured in
1782                  * host side.
1783                  */
1784                 if (pe->pdev)
1785                         set_iommu_table_base(&pe->pdev->dev, tbl);
1786                 else
1787                         pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
1788         }
1789         if (rc)
1790                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1791         else
1792                 pe->tce_bypass_enabled = enable;
1793 }
1794
1795 static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
1796                                           struct pnv_ioda_pe *pe)
1797 {
1798         /* TVE #1 is selected by PCI address bit 59 */
1799         pe->tce_bypass_base = 1ull << 59;
1800
1801         /* Install set_bypass callback for VFIO */
1802         pe->tce32_table->set_bypass = pnv_pci_ioda2_set_bypass;
1803
1804         /* Enable bypass by default */
1805         pnv_pci_ioda2_set_bypass(pe->tce32_table, true);
1806 }
1807
1808 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1809                                        struct pnv_ioda_pe *pe)
1810 {
1811         struct page *tce_mem = NULL;
1812         void *addr;
1813         const __be64 *swinvp;
1814         struct iommu_table *tbl;
1815         unsigned int tce_table_size, end;
1816         int64_t rc;
1817
1818         /* We shouldn't already have a 32-bit DMA associated */
1819         if (WARN_ON(pe->tce32_seg >= 0))
1820                 return;
1821
1822         /* The PE will reserve all possible 32-bits space */
1823         pe->tce32_seg = 0;
1824         end = (1 << ilog2(phb->ioda.m32_pci_base));
1825         tce_table_size = (end / 0x1000) * 8;
1826         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
1827                 end);
1828
1829         /* Allocate TCE table */
1830         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1831                                    get_order(tce_table_size));
1832         if (!tce_mem) {
1833                 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
1834                 goto fail;
1835         }
1836         addr = page_address(tce_mem);
1837         memset(addr, 0, tce_table_size);
1838
1839         /*
1840          * Map TCE table through TVT. The TVE index is the PE number
1841          * shifted by 1 bit for 32-bits DMA space.
1842          */
1843         rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1844                                         pe->pe_number << 1, 1, __pa(addr),
1845                                         tce_table_size, 0x1000);
1846         if (rc) {
1847                 pe_err(pe, "Failed to configure 32-bit TCE table,"
1848                        " err %ld\n", rc);
1849                 goto fail;
1850         }
1851
1852         /* Setup linux iommu table */
1853         tbl = pe->tce32_table;
1854         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
1855                         IOMMU_PAGE_SHIFT_4K);
1856
1857         /* OPAL variant of PHB3 invalidated TCEs */
1858         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
1859         if (swinvp) {
1860                 /* We need a couple more fields -- an address and a data
1861                  * to or.  Since the bus is only printed out on table free
1862                  * errors, and on the first pass the data will be a relative
1863                  * bus number, print that out instead.
1864                  */
1865                 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
1866                 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
1867                                 8);
1868                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
1869         }
1870         iommu_init_table(tbl, phb->hose->node);
1871
1872         if (pe->flags & PNV_IODA_PE_DEV) {
1873                 iommu_register_group(tbl, phb->hose->global_number,
1874                                      pe->pe_number);
1875                 set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
1876         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) {
1877                 iommu_register_group(tbl, phb->hose->global_number,
1878                                      pe->pe_number);
1879                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
1880         } else if (pe->flags & PNV_IODA_PE_VF) {
1881                 iommu_register_group(tbl, phb->hose->global_number,
1882                                      pe->pe_number);
1883         }
1884
1885         /* Also create a bypass window */
1886         if (!pnv_iommu_bypass_disabled)
1887                 pnv_pci_ioda2_setup_bypass_pe(phb, pe);
1888
1889         return;
1890 fail:
1891         if (pe->tce32_seg >= 0)
1892                 pe->tce32_seg = -1;
1893         if (tce_mem)
1894                 __free_pages(tce_mem, get_order(tce_table_size));
1895 }
1896
1897 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
1898 {
1899         struct pci_controller *hose = phb->hose;
1900         unsigned int residual, remaining, segs, tw, base;
1901         struct pnv_ioda_pe *pe;
1902
1903         /* If we have more PE# than segments available, hand out one
1904          * per PE until we run out and let the rest fail. If not,
1905          * then we assign at least one segment per PE, plus more based
1906          * on the amount of devices under that PE
1907          */
1908         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
1909                 residual = 0;
1910         else
1911                 residual = phb->ioda.tce32_count -
1912                         phb->ioda.dma_pe_count;
1913
1914         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
1915                 hose->global_number, phb->ioda.tce32_count);
1916         pr_info("PCI: %d PE# for a total weight of %d\n",
1917                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
1918
1919         /* Walk our PE list and configure their DMA segments, hand them
1920          * out one base segment plus any residual segments based on
1921          * weight
1922          */
1923         remaining = phb->ioda.tce32_count;
1924         tw = phb->ioda.dma_weight;
1925         base = 0;
1926         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
1927                 if (!pe->dma_weight)
1928                         continue;
1929                 if (!remaining) {
1930                         pe_warn(pe, "No DMA32 resources available\n");
1931                         continue;
1932                 }
1933                 segs = 1;
1934                 if (residual) {
1935                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
1936                         if (segs > remaining)
1937                                 segs = remaining;
1938                 }
1939
1940                 /*
1941                  * For IODA2 compliant PHB3, we needn't care about the weight.
1942                  * The all available 32-bits DMA space will be assigned to
1943                  * the specific PE.
1944                  */
1945                 if (phb->type == PNV_PHB_IODA1) {
1946                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
1947                                 pe->dma_weight, segs);
1948                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
1949                 } else {
1950                         pe_info(pe, "Assign DMA32 space\n");
1951                         segs = 0;
1952                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
1953                 }
1954
1955                 remaining -= segs;
1956                 base += segs;
1957         }
1958 }
1959
1960 #ifdef CONFIG_PCI_MSI
1961 static void pnv_ioda2_msi_eoi(struct irq_data *d)
1962 {
1963         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1964         struct irq_chip *chip = irq_data_get_irq_chip(d);
1965         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
1966                                            ioda.irq_chip);
1967         int64_t rc;
1968
1969         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
1970         WARN_ON_ONCE(rc);
1971
1972         icp_native_eoi(d);
1973 }
1974
1975
1976 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
1977 {
1978         struct irq_data *idata;
1979         struct irq_chip *ichip;
1980
1981         if (phb->type != PNV_PHB_IODA2)
1982                 return;
1983
1984         if (!phb->ioda.irq_chip_init) {
1985                 /*
1986                  * First time we setup an MSI IRQ, we need to setup the
1987                  * corresponding IRQ chip to route correctly.
1988                  */
1989                 idata = irq_get_irq_data(virq);
1990                 ichip = irq_data_get_irq_chip(idata);
1991                 phb->ioda.irq_chip_init = 1;
1992                 phb->ioda.irq_chip = *ichip;
1993                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
1994         }
1995         irq_set_chip(virq, &phb->ioda.irq_chip);
1996 }
1997
1998 #ifdef CONFIG_CXL_BASE
1999
2000 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2001 {
2002         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2003
2004         return of_node_get(hose->dn);
2005 }
2006 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2007
2008 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2009 {
2010         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2011         struct pnv_phb *phb = hose->private_data;
2012         struct pnv_ioda_pe *pe;
2013         int rc;
2014
2015         pe = pnv_ioda_get_pe(dev);
2016         if (!pe)
2017                 return -ENODEV;
2018
2019         pe_info(pe, "Switching PHB to CXL\n");
2020
2021         rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2022         if (rc)
2023                 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2024
2025         return rc;
2026 }
2027 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2028
2029 /* Find PHB for cxl dev and allocate MSI hwirqs?
2030  * Returns the absolute hardware IRQ number
2031  */
2032 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2033 {
2034         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2035         struct pnv_phb *phb = hose->private_data;
2036         int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2037
2038         if (hwirq < 0) {
2039                 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2040                 return -ENOSPC;
2041         }
2042
2043         return phb->msi_base + hwirq;
2044 }
2045 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2046
2047 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2048 {
2049         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2050         struct pnv_phb *phb = hose->private_data;
2051
2052         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2053 }
2054 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2055
2056 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2057                                   struct pci_dev *dev)
2058 {
2059         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2060         struct pnv_phb *phb = hose->private_data;
2061         int i, hwirq;
2062
2063         for (i = 1; i < CXL_IRQ_RANGES; i++) {
2064                 if (!irqs->range[i])
2065                         continue;
2066                 pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
2067                          i, irqs->offset[i],
2068                          irqs->range[i]);
2069                 hwirq = irqs->offset[i] - phb->msi_base;
2070                 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2071                                        irqs->range[i]);
2072         }
2073 }
2074 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2075
2076 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2077                                struct pci_dev *dev, int num)
2078 {
2079         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2080         struct pnv_phb *phb = hose->private_data;
2081         int i, hwirq, try;
2082
2083         memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2084
2085         /* 0 is reserved for the multiplexed PSL DSI interrupt */
2086         for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2087                 try = num;
2088                 while (try) {
2089                         hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2090                         if (hwirq >= 0)
2091                                 break;
2092                         try /= 2;
2093                 }
2094                 if (!try)
2095                         goto fail;
2096
2097                 irqs->offset[i] = phb->msi_base + hwirq;
2098                 irqs->range[i] = try;
2099                 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
2100                          i, irqs->offset[i], irqs->range[i]);
2101                 num -= try;
2102         }
2103         if (num)
2104                 goto fail;
2105
2106         return 0;
2107 fail:
2108         pnv_cxl_release_hwirq_ranges(irqs, dev);
2109         return -ENOSPC;
2110 }
2111 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2112
2113 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2114 {
2115         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2116         struct pnv_phb *phb = hose->private_data;
2117
2118         return phb->msi_bmp.irq_count;
2119 }
2120 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2121
2122 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2123                            unsigned int virq)
2124 {
2125         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2126         struct pnv_phb *phb = hose->private_data;
2127         unsigned int xive_num = hwirq - phb->msi_base;
2128         struct pnv_ioda_pe *pe;
2129         int rc;
2130
2131         if (!(pe = pnv_ioda_get_pe(dev)))
2132                 return -ENODEV;
2133
2134         /* Assign XIVE to PE */
2135         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2136         if (rc) {
2137                 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2138                         "hwirq 0x%x XIVE 0x%x PE\n",
2139                         pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2140                 return -EIO;
2141         }
2142         set_msi_irq_chip(phb, virq);
2143
2144         return 0;
2145 }
2146 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2147 #endif
2148
2149 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2150                                   unsigned int hwirq, unsigned int virq,
2151                                   unsigned int is_64, struct msi_msg *msg)
2152 {
2153         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2154         unsigned int xive_num = hwirq - phb->msi_base;
2155         __be32 data;
2156         int rc;
2157
2158         /* No PE assigned ? bail out ... no MSI for you ! */
2159         if (pe == NULL)
2160                 return -ENXIO;
2161
2162         /* Check if we have an MVE */
2163         if (pe->mve_number < 0)
2164                 return -ENXIO;
2165
2166         /* Force 32-bit MSI on some broken devices */
2167         if (dev->no_64bit_msi)
2168                 is_64 = 0;
2169
2170         /* Assign XIVE to PE */
2171         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2172         if (rc) {
2173                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2174                         pci_name(dev), rc, xive_num);
2175                 return -EIO;
2176         }
2177
2178         if (is_64) {
2179                 __be64 addr64;
2180
2181                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2182                                      &addr64, &data);
2183                 if (rc) {
2184                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2185                                 pci_name(dev), rc);
2186                         return -EIO;
2187                 }
2188                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2189                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2190         } else {
2191                 __be32 addr32;
2192
2193                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2194                                      &addr32, &data);
2195                 if (rc) {
2196                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2197                                 pci_name(dev), rc);
2198                         return -EIO;
2199                 }
2200                 msg->address_hi = 0;
2201                 msg->address_lo = be32_to_cpu(addr32);
2202         }
2203         msg->data = be32_to_cpu(data);
2204
2205         set_msi_irq_chip(phb, virq);
2206
2207         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2208                  " address=%x_%08x data=%x PE# %d\n",
2209                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2210                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2211
2212         return 0;
2213 }
2214
2215 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2216 {
2217         unsigned int count;
2218         const __be32 *prop = of_get_property(phb->hose->dn,
2219                                              "ibm,opal-msi-ranges", NULL);
2220         if (!prop) {
2221                 /* BML Fallback */
2222                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2223         }
2224         if (!prop)
2225                 return;
2226
2227         phb->msi_base = be32_to_cpup(prop);
2228         count = be32_to_cpup(prop + 1);
2229         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2230                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2231                        phb->hose->global_number);
2232                 return;
2233         }
2234
2235         phb->msi_setup = pnv_pci_ioda_msi_setup;
2236         phb->msi32_support = 1;
2237         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2238                 count, phb->msi_base);
2239 }
2240 #else
2241 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2242 #endif /* CONFIG_PCI_MSI */
2243
2244 #ifdef CONFIG_PCI_IOV
2245 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2246 {
2247         struct pci_controller *hose;
2248         struct pnv_phb *phb;
2249         struct resource *res;
2250         int i;
2251         resource_size_t size;
2252         struct pci_dn *pdn;
2253         int mul, total_vfs;
2254
2255         if (!pdev->is_physfn || pdev->is_added)
2256                 return;
2257
2258         hose = pci_bus_to_host(pdev->bus);
2259         phb = hose->private_data;
2260
2261         pdn = pci_get_pdn(pdev);
2262         pdn->vfs_expanded = 0;
2263
2264         total_vfs = pci_sriov_get_totalvfs(pdev);
2265         pdn->m64_per_iov = 1;
2266         mul = phb->ioda.total_pe;
2267
2268         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2269                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2270                 if (!res->flags || res->parent)
2271                         continue;
2272                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2273                         dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2274                                  i, res);
2275                         continue;
2276                 }
2277
2278                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2279
2280                 /* bigger than 64M */
2281                 if (size > (1 << 26)) {
2282                         dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2283                                  i, res);
2284                         pdn->m64_per_iov = M64_PER_IOV;
2285                         mul = roundup_pow_of_two(total_vfs);
2286                         break;
2287                 }
2288         }
2289
2290         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2291                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2292                 if (!res->flags || res->parent)
2293                         continue;
2294                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2295                         dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2296                                  i, res);
2297                         continue;
2298                 }
2299
2300                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2301                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2302                 res->end = res->start + size * mul - 1;
2303                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2304                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2305                          i, res, mul);
2306         }
2307         pdn->vfs_expanded = mul;
2308 }
2309 #endif /* CONFIG_PCI_IOV */
2310
2311 /*
2312  * This function is supposed to be called on basis of PE from top
2313  * to bottom style. So the the I/O or MMIO segment assigned to
2314  * parent PE could be overrided by its child PEs if necessary.
2315  */
2316 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2317                                   struct pnv_ioda_pe *pe)
2318 {
2319         struct pnv_phb *phb = hose->private_data;
2320         struct pci_bus_region region;
2321         struct resource *res;
2322         int i, index;
2323         int rc;
2324
2325         /*
2326          * NOTE: We only care PCI bus based PE for now. For PCI
2327          * device based PE, for example SRIOV sensitive VF should
2328          * be figured out later.
2329          */
2330         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2331
2332         pci_bus_for_each_resource(pe->pbus, res, i) {
2333                 if (!res || !res->flags ||
2334                     res->start > res->end)
2335                         continue;
2336
2337                 if (res->flags & IORESOURCE_IO) {
2338                         region.start = res->start - phb->ioda.io_pci_base;
2339                         region.end   = res->end - phb->ioda.io_pci_base;
2340                         index = region.start / phb->ioda.io_segsize;
2341
2342                         while (index < phb->ioda.total_pe &&
2343                                region.start <= region.end) {
2344                                 phb->ioda.io_segmap[index] = pe->pe_number;
2345                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2346                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2347                                 if (rc != OPAL_SUCCESS) {
2348                                         pr_err("%s: OPAL error %d when mapping IO "
2349                                                "segment #%d to PE#%d\n",
2350                                                __func__, rc, index, pe->pe_number);
2351                                         break;
2352                                 }
2353
2354                                 region.start += phb->ioda.io_segsize;
2355                                 index++;
2356                         }
2357                 } else if (res->flags & IORESOURCE_MEM) {
2358                         region.start = res->start -
2359                                        hose->mem_offset[0] -
2360                                        phb->ioda.m32_pci_base;
2361                         region.end   = res->end -
2362                                        hose->mem_offset[0] -
2363                                        phb->ioda.m32_pci_base;
2364                         index = region.start / phb->ioda.m32_segsize;
2365
2366                         while (index < phb->ioda.total_pe &&
2367                                region.start <= region.end) {
2368                                 phb->ioda.m32_segmap[index] = pe->pe_number;
2369                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2370                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2371                                 if (rc != OPAL_SUCCESS) {
2372                                         pr_err("%s: OPAL error %d when mapping M32 "
2373                                                "segment#%d to PE#%d",
2374                                                __func__, rc, index, pe->pe_number);
2375                                         break;
2376                                 }
2377
2378                                 region.start += phb->ioda.m32_segsize;
2379                                 index++;
2380                         }
2381                 }
2382         }
2383 }
2384
2385 static void pnv_pci_ioda_setup_seg(void)
2386 {
2387         struct pci_controller *tmp, *hose;
2388         struct pnv_phb *phb;
2389         struct pnv_ioda_pe *pe;
2390
2391         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2392                 phb = hose->private_data;
2393                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2394                         pnv_ioda_setup_pe_seg(hose, pe);
2395                 }
2396         }
2397 }
2398
2399 static void pnv_pci_ioda_setup_DMA(void)
2400 {
2401         struct pci_controller *hose, *tmp;
2402         struct pnv_phb *phb;
2403
2404         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2405                 pnv_ioda_setup_dma(hose->private_data);
2406
2407                 /* Mark the PHB initialization done */
2408                 phb = hose->private_data;
2409                 phb->initialized = 1;
2410         }
2411 }
2412
2413 static void pnv_pci_ioda_create_dbgfs(void)
2414 {
2415 #ifdef CONFIG_DEBUG_FS
2416         struct pci_controller *hose, *tmp;
2417         struct pnv_phb *phb;
2418         char name[16];
2419
2420         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2421                 phb = hose->private_data;
2422
2423                 sprintf(name, "PCI%04x", hose->global_number);
2424                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2425                 if (!phb->dbgfs)
2426                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2427                                 __func__, hose->global_number);
2428         }
2429 #endif /* CONFIG_DEBUG_FS */
2430 }
2431
2432 static void pnv_pci_ioda_fixup(void)
2433 {
2434         pnv_pci_ioda_setup_PEs();
2435         pnv_pci_ioda_setup_seg();
2436         pnv_pci_ioda_setup_DMA();
2437
2438         pnv_pci_ioda_create_dbgfs();
2439
2440 #ifdef CONFIG_EEH
2441         eeh_init();
2442         eeh_addr_cache_build();
2443 #endif
2444 }
2445
2446 /*
2447  * Returns the alignment for I/O or memory windows for P2P
2448  * bridges. That actually depends on how PEs are segmented.
2449  * For now, we return I/O or M32 segment size for PE sensitive
2450  * P2P bridges. Otherwise, the default values (4KiB for I/O,
2451  * 1MiB for memory) will be returned.
2452  *
2453  * The current PCI bus might be put into one PE, which was
2454  * create against the parent PCI bridge. For that case, we
2455  * needn't enlarge the alignment so that we can save some
2456  * resources.
2457  */
2458 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2459                                                 unsigned long type)
2460 {
2461         struct pci_dev *bridge;
2462         struct pci_controller *hose = pci_bus_to_host(bus);
2463         struct pnv_phb *phb = hose->private_data;
2464         int num_pci_bridges = 0;
2465
2466         bridge = bus->self;
2467         while (bridge) {
2468                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2469                         num_pci_bridges++;
2470                         if (num_pci_bridges >= 2)
2471                                 return 1;
2472                 }
2473
2474                 bridge = bridge->bus->self;
2475         }
2476
2477         /* We fail back to M32 if M64 isn't supported */
2478         if (phb->ioda.m64_segsize &&
2479             pnv_pci_is_mem_pref_64(type))
2480                 return phb->ioda.m64_segsize;
2481         if (type & IORESOURCE_MEM)
2482                 return phb->ioda.m32_segsize;
2483
2484         return phb->ioda.io_segsize;
2485 }
2486
2487 #ifdef CONFIG_PCI_IOV
2488 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
2489                                                       int resno)
2490 {
2491         struct pci_dn *pdn = pci_get_pdn(pdev);
2492         resource_size_t align, iov_align;
2493
2494         iov_align = resource_size(&pdev->resource[resno]);
2495         if (iov_align)
2496                 return iov_align;
2497
2498         align = pci_iov_resource_size(pdev, resno);
2499         if (pdn->vfs_expanded)
2500                 return pdn->vfs_expanded * align;
2501
2502         return align;
2503 }
2504 #endif /* CONFIG_PCI_IOV */
2505
2506 /* Prevent enabling devices for which we couldn't properly
2507  * assign a PE
2508  */
2509 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
2510 {
2511         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2512         struct pnv_phb *phb = hose->private_data;
2513         struct pci_dn *pdn;
2514
2515         /* The function is probably called while the PEs have
2516          * not be created yet. For example, resource reassignment
2517          * during PCI probe period. We just skip the check if
2518          * PEs isn't ready.
2519          */
2520         if (!phb->initialized)
2521                 return 0;
2522
2523         pdn = pci_get_pdn(dev);
2524         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2525                 return -EINVAL;
2526
2527         return 0;
2528 }
2529
2530 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
2531                                u32 devfn)
2532 {
2533         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
2534 }
2535
2536 static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
2537 {
2538         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
2539                        OPAL_ASSERT_RESET);
2540 }
2541
2542 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2543                                          u64 hub_id, int ioda_type)
2544 {
2545         struct pci_controller *hose;
2546         struct pnv_phb *phb;
2547         unsigned long size, m32map_off, pemap_off, iomap_off = 0;
2548         const __be64 *prop64;
2549         const __be32 *prop32;
2550         int len;
2551         u64 phb_id;
2552         void *aux;
2553         long rc;
2554
2555         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
2556
2557         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
2558         if (!prop64) {
2559                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
2560                 return;
2561         }
2562         phb_id = be64_to_cpup(prop64);
2563         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
2564
2565         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
2566
2567         /* Allocate PCI controller */
2568         phb->hose = hose = pcibios_alloc_controller(np);
2569         if (!phb->hose) {
2570                 pr_err("  Can't allocate PCI controller for %s\n",
2571                        np->full_name);
2572                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
2573                 return;
2574         }
2575
2576         spin_lock_init(&phb->lock);
2577         prop32 = of_get_property(np, "bus-range", &len);
2578         if (prop32 && len == 8) {
2579                 hose->first_busno = be32_to_cpu(prop32[0]);
2580                 hose->last_busno = be32_to_cpu(prop32[1]);
2581         } else {
2582                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
2583                 hose->first_busno = 0;
2584                 hose->last_busno = 0xff;
2585         }
2586         hose->private_data = phb;
2587         phb->hub_id = hub_id;
2588         phb->opal_id = phb_id;
2589         phb->type = ioda_type;
2590         mutex_init(&phb->ioda.pe_alloc_mutex);
2591
2592         /* Detect specific models for error handling */
2593         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
2594                 phb->model = PNV_PHB_MODEL_P7IOC;
2595         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
2596                 phb->model = PNV_PHB_MODEL_PHB3;
2597         else
2598                 phb->model = PNV_PHB_MODEL_UNKNOWN;
2599
2600         /* Parse 32-bit and IO ranges (if any) */
2601         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
2602
2603         /* Get registers */
2604         phb->regs = of_iomap(np, 0);
2605         if (phb->regs == NULL)
2606                 pr_err("  Failed to map registers !\n");
2607
2608         /* Initialize more IODA stuff */
2609         phb->ioda.total_pe = 1;
2610         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
2611         if (prop32)
2612                 phb->ioda.total_pe = be32_to_cpup(prop32);
2613         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
2614         if (prop32)
2615                 phb->ioda.reserved_pe = be32_to_cpup(prop32);
2616
2617         /* Parse 64-bit MMIO range */
2618         pnv_ioda_parse_m64_window(phb);
2619
2620         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
2621         /* FW Has already off top 64k of M32 space (MSI space) */
2622         phb->ioda.m32_size += 0x10000;
2623
2624         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
2625         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
2626         phb->ioda.io_size = hose->pci_io_size;
2627         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
2628         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
2629
2630         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
2631         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
2632         m32map_off = size;
2633         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
2634         if (phb->type == PNV_PHB_IODA1) {
2635                 iomap_off = size;
2636                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
2637         }
2638         pemap_off = size;
2639         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
2640         aux = memblock_virt_alloc(size, 0);
2641         phb->ioda.pe_alloc = aux;
2642         phb->ioda.m32_segmap = aux + m32map_off;
2643         if (phb->type == PNV_PHB_IODA1)
2644                 phb->ioda.io_segmap = aux + iomap_off;
2645         phb->ioda.pe_array = aux + pemap_off;
2646         set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
2647
2648         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
2649         INIT_LIST_HEAD(&phb->ioda.pe_list);
2650         mutex_init(&phb->ioda.pe_list_mutex);
2651
2652         /* Calculate how many 32-bit TCE segments we have */
2653         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
2654
2655 #if 0 /* We should really do that ... */
2656         rc = opal_pci_set_phb_mem_window(opal->phb_id,
2657                                          window_type,
2658                                          window_num,
2659                                          starting_real_address,
2660                                          starting_pci_address,
2661                                          segment_size);
2662 #endif
2663
2664         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
2665                 phb->ioda.total_pe, phb->ioda.reserved_pe,
2666                 phb->ioda.m32_size, phb->ioda.m32_segsize);
2667         if (phb->ioda.m64_size)
2668                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
2669                         phb->ioda.m64_size, phb->ioda.m64_segsize);
2670         if (phb->ioda.io_size)
2671                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
2672                         phb->ioda.io_size, phb->ioda.io_segsize);
2673
2674
2675         phb->hose->ops = &pnv_pci_ops;
2676         phb->get_pe_state = pnv_ioda_get_pe_state;
2677         phb->freeze_pe = pnv_ioda_freeze_pe;
2678         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
2679
2680         /* Setup RID -> PE mapping function */
2681         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
2682
2683         /* Setup TCEs */
2684         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
2685         phb->dma_set_mask = pnv_pci_ioda_dma_set_mask;
2686         phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask;
2687
2688         /* Setup shutdown function for kexec */
2689         phb->shutdown = pnv_pci_ioda_shutdown;
2690
2691         /* Setup MSI support */
2692         pnv_pci_init_ioda_msis(phb);
2693
2694         /*
2695          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
2696          * to let the PCI core do resource assignment. It's supposed
2697          * that the PCI core will do correct I/O and MMIO alignment
2698          * for the P2P bridge bars so that each PCI bus (excluding
2699          * the child P2P bridges) can form individual PE.
2700          */
2701         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
2702         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
2703         ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
2704         ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus;
2705 #ifdef CONFIG_PCI_IOV
2706         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
2707         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
2708 #endif /* CONFIG_PCI_IOV */
2709         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
2710
2711         /* Reset IODA tables to a clean state */
2712         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
2713         if (rc)
2714                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
2715
2716         /* If we're running in kdump kerenl, the previous kerenl never
2717          * shutdown PCI devices correctly. We already got IODA table
2718          * cleaned out. So we have to issue PHB reset to stop all PCI
2719          * transactions from previous kerenl.
2720          */
2721         if (is_kdump_kernel()) {
2722                 pr_info("  Issue PHB reset ...\n");
2723                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
2724                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
2725         }
2726
2727         /* Remove M64 resource if we can't configure it successfully */
2728         if (!phb->init_m64 || phb->init_m64(phb))
2729                 hose->mem_resources[1].flags = 0;
2730 }
2731
2732 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
2733 {
2734         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
2735 }
2736
2737 void __init pnv_pci_init_ioda_hub(struct device_node *np)
2738 {
2739         struct device_node *phbn;
2740         const __be64 *prop64;
2741         u64 hub_id;
2742
2743         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
2744
2745         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
2746         if (!prop64) {
2747                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
2748                 return;
2749         }
2750         hub_id = be64_to_cpup(prop64);
2751         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
2752
2753         /* Count child PHBs */
2754         for_each_child_of_node(np, phbn) {
2755                 /* Look for IODA1 PHBs */
2756                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
2757                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
2758         }
2759 }