arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26
  27 #include <asm/sections.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/machdep.h>
  32 #include <asm/msi_bitmap.h>
  33 #include <asm/ppc-pci.h>
  34 #include <asm/opal.h>
  35 #include <asm/iommu.h>
  36 #include <asm/tce.h>
  37 #include <asm/xics.h>
  38 #include <asm/debug.h>
  39 #include <asm/firmware.h>
  40
  41 #include "powernv.h"
  42 #include "pci.h"
  43
  44 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  45                             const char *fmt, ...)
  46 {
  47         struct va_format vaf;
  48         va_list args;
  49         char pfix[32];
  50
  51         va_start(args, fmt);
  52
  53         vaf.fmt = fmt;
  54         vaf.va = &args;
  55
  56         if (pe->pdev)
  57                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  58         else
  59                 sprintf(pfix, "%04x:%02x     ",
  60                         pci_domain_nr(pe->pbus), pe->pbus->number);
  61
  62         printk("%spci %s: [PE# %.3d] %pV",
  63                level, pfix, pe->pe_number, &vaf);
  64
  65         va_end(args);
  66 }
  67
  68 #define pe_err(pe, fmt, ...)                                    \
  69         pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
  70 #define pe_warn(pe, fmt, ...)                                   \
  71         pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
  72 #define pe_info(pe, fmt, ...)                                   \
  73         pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
  74
  75 /*
  76  * stdcix is only supposed to be used in hypervisor real mode as per
  77  * the architecture spec
  78  */
  79 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
  80 {
  81         __asm__ __volatile__("stdcix %0,0,%1"
  82                 : : "r" (val), "r" (paddr) : "memory");
  83 }
  84
  85 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
  86 {
  87         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
  88                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
  89 }
  90
  91 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
  92 {
  93         unsigned long pe;
  94
  95         do {
  96                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
  97                                         phb->ioda.total_pe, 0);
  98                 if (pe >= phb->ioda.total_pe)
  99                         return IODA_INVALID_PE;
 100         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 101
 102         phb->ioda.pe_array[pe].phb = phb;
 103         phb->ioda.pe_array[pe].pe_number = pe;
 104         return pe;
 105 }
 106
 107 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
 108 {
 109         WARN_ON(phb->ioda.pe_array[pe].pdev);
 110
 111         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
 112         clear_bit(pe, phb->ioda.pe_alloc);
 113 }
 114
 115 /* The default M64 BAR is shared by all PEs */
 116 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 117 {
 118         const char *desc;
 119         struct resource *r;
 120         s64 rc;
 121
 122         /* Configure the default M64 BAR */
 123         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 124                                          OPAL_M64_WINDOW_TYPE,
 125                                          phb->ioda.m64_bar_idx,
 126                                          phb->ioda.m64_base,
 127                                          0, /* unused */
 128                                          phb->ioda.m64_size);
 129         if (rc != OPAL_SUCCESS) {
 130                 desc = "configuring";
 131                 goto fail;
 132         }
 133
 134         /* Enable the default M64 BAR */
 135         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 136                                       OPAL_M64_WINDOW_TYPE,
 137                                       phb->ioda.m64_bar_idx,
 138                                       OPAL_ENABLE_M64_SPLIT);
 139         if (rc != OPAL_SUCCESS) {
 140                 desc = "enabling";
 141                 goto fail;
 142         }
 143
 144         /* Mark the M64 BAR assigned */
 145         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 146
 147         /*
 148          * Strip off the segment used by the reserved PE, which is
 149          * expected to be 0 or last one of PE capabicity.
 150          */
 151         r = &phb->hose->mem_resources[1];
 152         if (phb->ioda.reserved_pe == 0)
 153                 r->start += phb->ioda.m64_segsize;
 154         else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
 155                 r->end -= phb->ioda.m64_segsize;
 156         else
 157                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 158                         phb->ioda.reserved_pe);
 159
 160         return 0;
 161
 162 fail:
 163         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 164                 rc, desc, phb->ioda.m64_bar_idx);
 165         opal_pci_phb_mmio_enable(phb->opal_id,
 166                                  OPAL_M64_WINDOW_TYPE,
 167                                  phb->ioda.m64_bar_idx,
 168                                  OPAL_DISABLE_M64);
 169         return -EIO;
 170 }
 171
 172 static void pnv_ioda2_alloc_m64_pe(struct pnv_phb *phb)
 173 {
 174         resource_size_t sgsz = phb->ioda.m64_segsize;
 175         struct pci_dev *pdev;
 176         struct resource *r;
 177         int base, step, i;
 178
 179         /*
 180          * Root bus always has full M64 range and root port has
 181          * M64 range used in reality. So we're checking root port
 182          * instead of root bus.
 183          */
 184         list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) {
 185                 for (i = PCI_BRIDGE_RESOURCES;
 186                      i <= PCI_BRIDGE_RESOURCE_END; i++) {
 187                         r = &pdev->resource[i];
 188                         if (!r->parent ||
 189                             !pnv_pci_is_mem_pref_64(r->flags))
 190                                 continue;
 191
 192                         base = (r->start - phb->ioda.m64_base) / sgsz;
 193                         for (step = 0; step < resource_size(r) / sgsz; step++)
 194                                 set_bit(base + step, phb->ioda.pe_alloc);
 195                 }
 196         }
 197 }
 198
 199 static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb,
 200                                  struct pci_bus *bus, int all)
 201 {
 202         resource_size_t segsz = phb->ioda.m64_segsize;
 203         struct pci_dev *pdev;
 204         struct resource *r;
 205         struct pnv_ioda_pe *master_pe, *pe;
 206         unsigned long size, *pe_alloc;
 207         bool found;
 208         int start, i, j;
 209
 210         /* Root bus shouldn't use M64 */
 211         if (pci_is_root_bus(bus))
 212                 return IODA_INVALID_PE;
 213
 214         /* We support only one M64 window on each bus */
 215         found = false;
 216         pci_bus_for_each_resource(bus, r, i) {
 217                 if (r && r->parent &&
 218                     pnv_pci_is_mem_pref_64(r->flags)) {
 219                         found = true;
 220                         break;
 221                 }
 222         }
 223
 224         /* No M64 window found ? */
 225         if (!found)
 226                 return IODA_INVALID_PE;
 227
 228         /* Allocate bitmap */
 229         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
 230         pe_alloc = kzalloc(size, GFP_KERNEL);
 231         if (!pe_alloc) {
 232                 pr_warn("%s: Out of memory !\n",
 233                         __func__);
 234                 return IODA_INVALID_PE;
 235         }
 236
 237         /*
 238          * Figure out reserved PE numbers by the PE
 239          * the its child PEs.
 240          */
 241         start = (r->start - phb->ioda.m64_base) / segsz;
 242         for (i = 0; i < resource_size(r) / segsz; i++)
 243                 set_bit(start + i, pe_alloc);
 244
 245         if (all)
 246                 goto done;
 247
 248         /*
 249          * If the PE doesn't cover all subordinate buses,
 250          * we need subtract from reserved PEs for children.
 251          */
 252         list_for_each_entry(pdev, &bus->devices, bus_list) {
 253                 if (!pdev->subordinate)
 254                         continue;
 255
 256                 pci_bus_for_each_resource(pdev->subordinate, r, i) {
 257                         if (!r || !r->parent ||
 258                             !pnv_pci_is_mem_pref_64(r->flags))
 259                                 continue;
 260
 261                         start = (r->start - phb->ioda.m64_base) / segsz;
 262                         for (j = 0; j < resource_size(r) / segsz ; j++)
 263                                 clear_bit(start + j, pe_alloc);
 264                 }
 265         }
 266
 267         /*
 268          * the current bus might not own M64 window and that's all
 269          * contributed by its child buses. For the case, we needn't
 270          * pick M64 dependent PE#.
 271          */
 272         if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
 273                 kfree(pe_alloc);
 274                 return IODA_INVALID_PE;
 275         }
 276
 277         /*
 278          * Figure out the master PE and put all slave PEs to master
 279          * PE's list to form compound PE.
 280          */
 281 done:
 282         master_pe = NULL;
 283         i = -1;
 284         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
 285                 phb->ioda.total_pe) {
 286                 pe = &phb->ioda.pe_array[i];
 287                 pe->phb = phb;
 288                 pe->pe_number = i;
 289
 290                 if (!master_pe) {
 291                         pe->flags |= PNV_IODA_PE_MASTER;
 292                         INIT_LIST_HEAD(&pe->slaves);
 293                         master_pe = pe;
 294                 } else {
 295                         pe->flags |= PNV_IODA_PE_SLAVE;
 296                         pe->master = master_pe;
 297                         list_add_tail(&pe->list, &master_pe->slaves);
 298                 }
 299         }
 300
 301         kfree(pe_alloc);
 302         return master_pe->pe_number;
 303 }
 304
 305 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 306 {
 307         struct pci_controller *hose = phb->hose;
 308         struct device_node *dn = hose->dn;
 309         struct resource *res;
 310         const u32 *r;
 311         u64 pci_addr;
 312
 313         if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
 314                 pr_info("  Firmware too old to support M64 window\n");
 315                 return;
 316         }
 317
 318         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 319         if (!r) {
 320                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 321                         dn->full_name);
 322                 return;
 323         }
 324
 325         /* FIXME: Support M64 for P7IOC */
 326         if (phb->type != PNV_PHB_IODA2) {
 327                 pr_info("  Not support M64 window\n");
 328                 return;
 329         }
 330
 331         res = &hose->mem_resources[1];
 332         res->start = of_translate_address(dn, r + 2);
 333         res->end = res->start + of_read_number(r + 4, 2) - 1;
 334         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 335         pci_addr = of_read_number(r, 2);
 336         hose->mem_offset[1] = res->start - pci_addr;
 337
 338         phb->ioda.m64_size = resource_size(res);
 339         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
 340         phb->ioda.m64_base = pci_addr;
 341
 342         /* Use last M64 BAR to cover M64 window */
 343         phb->ioda.m64_bar_idx = 15;
 344         phb->init_m64 = pnv_ioda2_init_m64;
 345         phb->alloc_m64_pe = pnv_ioda2_alloc_m64_pe;
 346         phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
 347 }
 348
 349 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 350 {
 351         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 352         struct pnv_ioda_pe *slave;
 353         s64 rc;
 354
 355         /* Fetch master PE */
 356         if (pe->flags & PNV_IODA_PE_SLAVE) {
 357                 pe = pe->master;
 358                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 359                 pe_no = pe->pe_number;
 360         }
 361
 362         /* Freeze master PE */
 363         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 364                                      pe_no,
 365                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 366         if (rc != OPAL_SUCCESS) {
 367                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 368                         __func__, rc, phb->hose->global_number, pe_no);
 369                 return;
 370         }
 371
 372         /* Freeze slave PEs */
 373         if (!(pe->flags & PNV_IODA_PE_MASTER))
 374                 return;
 375
 376         list_for_each_entry(slave, &pe->slaves, list) {
 377                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 378                                              slave->pe_number,
 379                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 380                 if (rc != OPAL_SUCCESS)
 381                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 382                                 __func__, rc, phb->hose->global_number,
 383                                 slave->pe_number);
 384         }
 385 }
 386
 387 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 388 {
 389         struct pnv_ioda_pe *pe, *slave;
 390         s64 rc;
 391
 392         /* Find master PE */
 393         pe = &phb->ioda.pe_array[pe_no];
 394         if (pe->flags & PNV_IODA_PE_SLAVE) {
 395                 pe = pe->master;
 396                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 397                 pe_no = pe->pe_number;
 398         }
 399
 400         /* Clear frozen state for master PE */
 401         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 402         if (rc != OPAL_SUCCESS) {
 403                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 404                         __func__, rc, opt, phb->hose->global_number, pe_no);
 405                 return -EIO;
 406         }
 407
 408         if (!(pe->flags & PNV_IODA_PE_MASTER))
 409                 return 0;
 410
 411         /* Clear frozen state for slave PEs */
 412         list_for_each_entry(slave, &pe->slaves, list) {
 413                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 414                                              slave->pe_number,
 415                                              opt);
 416                 if (rc != OPAL_SUCCESS) {
 417                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 418                                 __func__, rc, opt, phb->hose->global_number,
 419                                 slave->pe_number);
 420                         return -EIO;
 421                 }
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 428 {
 429         struct pnv_ioda_pe *slave, *pe;
 430         u8 fstate, state;
 431         __be16 pcierr;
 432         s64 rc;
 433
 434         /* Sanity check on PE number */
 435         if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
 436                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 437
 438         /*
 439          * Fetch the master PE and the PE instance might be
 440          * not initialized yet.
 441          */
 442         pe = &phb->ioda.pe_array[pe_no];
 443         if (pe->flags & PNV_IODA_PE_SLAVE) {
 444                 pe = pe->master;
 445                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 446                 pe_no = pe->pe_number;
 447         }
 448
 449         /* Check the master PE */
 450         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 451                                         &state, &pcierr, NULL);
 452         if (rc != OPAL_SUCCESS) {
 453                 pr_warn("%s: Failure %lld getting "
 454                         "PHB#%x-PE#%x state\n",
 455                         __func__, rc,
 456                         phb->hose->global_number, pe_no);
 457                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 458         }
 459
 460         /* Check the slave PE */
 461         if (!(pe->flags & PNV_IODA_PE_MASTER))
 462                 return state;
 463
 464         list_for_each_entry(slave, &pe->slaves, list) {
 465                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 466                                                 slave->pe_number,
 467                                                 &fstate,
 468                                                 &pcierr,
 469                                                 NULL);
 470                 if (rc != OPAL_SUCCESS) {
 471                         pr_warn("%s: Failure %lld getting "
 472                                 "PHB#%x-PE#%x state\n",
 473                                 __func__, rc,
 474                                 phb->hose->global_number, slave->pe_number);
 475                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 476                 }
 477
 478                 /*
 479                  * Override the result based on the ascending
 480                  * priority.
 481                  */
 482                 if (fstate > state)
 483                         state = fstate;
 484         }
 485
 486         return state;
 487 }
 488
 489 /* Currently those 2 are only used when MSIs are enabled, this will change
 490  * but in the meantime, we need to protect them to avoid warnings
 491  */
 492 #ifdef CONFIG_PCI_MSI
 493 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 494 {
 495         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 496         struct pnv_phb *phb = hose->private_data;
 497         struct pci_dn *pdn = pci_get_pdn(dev);
 498
 499         if (!pdn)
 500                 return NULL;
 501         if (pdn->pe_number == IODA_INVALID_PE)
 502                 return NULL;
 503         return &phb->ioda.pe_array[pdn->pe_number];
 504 }
 505 #endif /* CONFIG_PCI_MSI */
 506
 507 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 508 {
 509         struct pci_dev *parent;
 510         uint8_t bcomp, dcomp, fcomp;
 511         long rc, rid_end, rid;
 512
 513         /* Bus validation ? */
 514         if (pe->pbus) {
 515                 int count;
 516
 517                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 518                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 519                 parent = pe->pbus->self;
 520                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 521                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 522                 else
 523                         count = 1;
 524
 525                 switch(count) {
 526                 case  1: bcomp = OpalPciBusAll;         break;
 527                 case  2: bcomp = OpalPciBus7Bits;       break;
 528                 case  4: bcomp = OpalPciBus6Bits;       break;
 529                 case  8: bcomp = OpalPciBus5Bits;       break;
 530                 case 16: bcomp = OpalPciBus4Bits;       break;
 531                 case 32: bcomp = OpalPciBus3Bits;       break;
 532                 default:
 533                         pr_err("%s: Number of subordinate busses %d"
 534                                " unsupported\n",
 535                                pci_name(pe->pbus->self), count);
 536                         /* Do an exact match only */
 537                         bcomp = OpalPciBusAll;
 538                 }
 539                 rid_end = pe->rid + (count << 8);
 540         } else {
 541                 parent = pe->pdev->bus->self;
 542                 bcomp = OpalPciBusAll;
 543                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 544                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 545                 rid_end = pe->rid + 1;
 546         }
 547
 548         /*
 549          * Associate PE in PELT. We need add the PE into the
 550          * corresponding PELT-V as well. Otherwise, the error
 551          * originated from the PE might contribute to other
 552          * PEs.
 553          */
 554         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 555                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 556         if (rc) {
 557                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 558                 return -ENXIO;
 559         }
 560
 561         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 562                                 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
 563         if (rc)
 564                 pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc);
 565         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 566                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 567
 568         /* Add to all parents PELT-V */
 569         while (parent) {
 570                 struct pci_dn *pdn = pci_get_pdn(parent);
 571                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 572                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 573                                                 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
 574                         /* XXX What to do in case of error ? */
 575                 }
 576                 parent = parent->bus->self;
 577         }
 578         /* Setup reverse map */
 579         for (rid = pe->rid; rid < rid_end; rid++)
 580                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 581
 582         /* Setup one MVTs on IODA1 */
 583         if (phb->type == PNV_PHB_IODA1) {
 584                 pe->mve_number = pe->pe_number;
 585                 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
 586                                       pe->pe_number);
 587                 if (rc) {
 588                         pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 589                                rc, pe->mve_number);
 590                         pe->mve_number = -1;
 591                 } else {
 592                         rc = opal_pci_set_mve_enable(phb->opal_id,
 593                                                      pe->mve_number, OPAL_ENABLE_MVE);
 594                         if (rc) {
 595                                 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 596                                        rc, pe->mve_number);
 597                                 pe->mve_number = -1;
 598                         }
 599                 }
 600         } else if (phb->type == PNV_PHB_IODA2)
 601                 pe->mve_number = 0;
 602
 603         return 0;
 604 }
 605
 606 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 607                                        struct pnv_ioda_pe *pe)
 608 {
 609         struct pnv_ioda_pe *lpe;
 610
 611         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 612                 if (lpe->dma_weight < pe->dma_weight) {
 613                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 614                         return;
 615                 }
 616         }
 617         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 618 }
 619
 620 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 621 {
 622         /* This is quite simplistic. The "base" weight of a device
 623          * is 10. 0 means no DMA is to be accounted for it.
 624          */
 625
 626         /* If it's a bridge, no DMA */
 627         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 628                 return 0;
 629
 630         /* Reduce the weight of slow USB controllers */
 631         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 632             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 633             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 634                 return 3;
 635
 636         /* Increase the weight of RAID (includes Obsidian) */
 637         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 638                 return 15;
 639
 640         /* Default */
 641         return 10;
 642 }
 643
 644 #if 0
 645 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 646 {
 647         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 648         struct pnv_phb *phb = hose->private_data;
 649         struct pci_dn *pdn = pci_get_pdn(dev);
 650         struct pnv_ioda_pe *pe;
 651         int pe_num;
 652
 653         if (!pdn) {
 654                 pr_err("%s: Device tree node not associated properly\n",
 655                            pci_name(dev));
 656                 return NULL;
 657         }
 658         if (pdn->pe_number != IODA_INVALID_PE)
 659                 return NULL;
 660
 661         /* PE#0 has been pre-set */
 662         if (dev->bus->number == 0)
 663                 pe_num = 0;
 664         else
 665                 pe_num = pnv_ioda_alloc_pe(phb);
 666         if (pe_num == IODA_INVALID_PE) {
 667                 pr_warning("%s: Not enough PE# available, disabling device\n",
 668                            pci_name(dev));
 669                 return NULL;
 670         }
 671
 672         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 673          * pointer in the PE data structure, both should be destroyed at the
 674          * same time. However, this needs to be looked at more closely again
 675          * once we actually start removing things (Hotplug, SR-IOV, ...)
 676          *
 677          * At some point we want to remove the PDN completely anyways
 678          */
 679         pe = &phb->ioda.pe_array[pe_num];
 680         pci_dev_get(dev);
 681         pdn->pcidev = dev;
 682         pdn->pe_number = pe_num;
 683         pe->pdev = dev;
 684         pe->pbus = NULL;
 685         pe->tce32_seg = -1;
 686         pe->mve_number = -1;
 687         pe->rid = dev->bus->number << 8 | pdn->devfn;
 688
 689         pe_info(pe, "Associated device to PE\n");
 690
 691         if (pnv_ioda_configure_pe(phb, pe)) {
 692                 /* XXX What do we do here ? */
 693                 if (pe_num)
 694                         pnv_ioda_free_pe(phb, pe_num);
 695                 pdn->pe_number = IODA_INVALID_PE;
 696                 pe->pdev = NULL;
 697                 pci_dev_put(dev);
 698                 return NULL;
 699         }
 700
 701         /* Assign a DMA weight to the device */
 702         pe->dma_weight = pnv_ioda_dma_weight(dev);
 703         if (pe->dma_weight != 0) {
 704                 phb->ioda.dma_weight += pe->dma_weight;
 705                 phb->ioda.dma_pe_count++;
 706         }
 707
 708         /* Link the PE */
 709         pnv_ioda_link_pe_by_weight(phb, pe);
 710
 711         return pe;
 712 }
 713 #endif /* Useful for SRIOV case */
 714
 715 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
 716 {
 717         struct pci_dev *dev;
 718
 719         list_for_each_entry(dev, &bus->devices, bus_list) {
 720                 struct pci_dn *pdn = pci_get_pdn(dev);
 721
 722                 if (pdn == NULL) {
 723                         pr_warn("%s: No device node associated with device !\n",
 724                                 pci_name(dev));
 725                         continue;
 726                 }
 727                 pdn->pcidev = dev;
 728                 pdn->pe_number = pe->pe_number;
 729                 pe->dma_weight += pnv_ioda_dma_weight(dev);
 730                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
 731                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
 732         }
 733 }
 734
 735 /*
 736  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
 737  * single PCI bus. Another one that contains the primary PCI bus and its
 738  * subordinate PCI devices and buses. The second type of PE is normally
 739  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
 740  */
 741 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
 742 {
 743         struct pci_controller *hose = pci_bus_to_host(bus);
 744         struct pnv_phb *phb = hose->private_data;
 745         struct pnv_ioda_pe *pe;
 746         int pe_num = IODA_INVALID_PE;
 747
 748         /* Check if PE is determined by M64 */
 749         if (phb->pick_m64_pe)
 750                 pe_num = phb->pick_m64_pe(phb, bus, all);
 751
 752         /* The PE number isn't pinned by M64 */
 753         if (pe_num == IODA_INVALID_PE)
 754                 pe_num = pnv_ioda_alloc_pe(phb);
 755
 756         if (pe_num == IODA_INVALID_PE) {
 757                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
 758                         __func__, pci_domain_nr(bus), bus->number);
 759                 return;
 760         }
 761
 762         pe = &phb->ioda.pe_array[pe_num];
 763         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
 764         pe->pbus = bus;
 765         pe->pdev = NULL;
 766         pe->tce32_seg = -1;
 767         pe->mve_number = -1;
 768         pe->rid = bus->busn_res.start << 8;
 769         pe->dma_weight = 0;
 770
 771         if (all)
 772                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
 773                         bus->busn_res.start, bus->busn_res.end, pe_num);
 774         else
 775                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
 776                         bus->busn_res.start, pe_num);
 777
 778         if (pnv_ioda_configure_pe(phb, pe)) {
 779                 /* XXX What do we do here ? */
 780                 if (pe_num)
 781                         pnv_ioda_free_pe(phb, pe_num);
 782                 pe->pbus = NULL;
 783                 return;
 784         }
 785
 786         /* Associate it with all child devices */
 787         pnv_ioda_setup_same_PE(bus, pe);
 788
 789         /* Put PE to the list */
 790         list_add_tail(&pe->list, &phb->ioda.pe_list);
 791
 792         /* Account for one DMA PE if at least one DMA capable device exist
 793          * below the bridge
 794          */
 795         if (pe->dma_weight != 0) {
 796                 phb->ioda.dma_weight += pe->dma_weight;
 797                 phb->ioda.dma_pe_count++;
 798         }
 799
 800         /* Link the PE */
 801         pnv_ioda_link_pe_by_weight(phb, pe);
 802 }
 803
 804 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
 805 {
 806         struct pci_dev *dev;
 807
 808         pnv_ioda_setup_bus_PE(bus, 0);
 809
 810         list_for_each_entry(dev, &bus->devices, bus_list) {
 811                 if (dev->subordinate) {
 812                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
 813                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
 814                         else
 815                                 pnv_ioda_setup_PEs(dev->subordinate);
 816                 }
 817         }
 818 }
 819
 820 /*
 821  * Configure PEs so that the downstream PCI buses and devices
 822  * could have their associated PE#. Unfortunately, we didn't
 823  * figure out the way to identify the PLX bridge yet. So we
 824  * simply put the PCI bus and the subordinate behind the root
 825  * port to PE# here. The game rule here is expected to be changed
 826  * as soon as we can detected PLX bridge correctly.
 827  */
 828 static void pnv_pci_ioda_setup_PEs(void)
 829 {
 830         struct pci_controller *hose, *tmp;
 831         struct pnv_phb *phb;
 832
 833         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 834                 phb = hose->private_data;
 835
 836                 /* M64 layout might affect PE allocation */
 837                 if (phb->alloc_m64_pe)
 838                         phb->alloc_m64_pe(phb);
 839
 840                 pnv_ioda_setup_PEs(hose->bus);
 841         }
 842 }
 843
 844 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
 845 {
 846         struct pci_dn *pdn = pci_get_pdn(pdev);
 847         struct pnv_ioda_pe *pe;
 848
 849         /*
 850          * The function can be called while the PE#
 851          * hasn't been assigned. Do nothing for the
 852          * case.
 853          */
 854         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
 855                 return;
 856
 857         pe = &phb->ioda.pe_array[pdn->pe_number];
 858         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
 859         set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
 860 }
 861
 862 static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
 863                                      struct pci_dev *pdev, u64 dma_mask)
 864 {
 865         struct pci_dn *pdn = pci_get_pdn(pdev);
 866         struct pnv_ioda_pe *pe;
 867         uint64_t top;
 868         bool bypass = false;
 869
 870         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
 871                 return -ENODEV;;
 872
 873         pe = &phb->ioda.pe_array[pdn->pe_number];
 874         if (pe->tce_bypass_enabled) {
 875                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
 876                 bypass = (dma_mask >= top);
 877         }
 878
 879         if (bypass) {
 880                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
 881                 set_dma_ops(&pdev->dev, &dma_direct_ops);
 882                 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
 883         } else {
 884                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
 885                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
 886                 set_iommu_table_base(&pdev->dev, &pe->tce32_table);
 887         }
 888         *pdev->dev.dma_mask = dma_mask;
 889         return 0;
 890 }
 891
 892 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
 893                                    struct pci_bus *bus,
 894                                    bool add_to_iommu_group)
 895 {
 896         struct pci_dev *dev;
 897
 898         list_for_each_entry(dev, &bus->devices, bus_list) {
 899                 if (add_to_iommu_group)
 900                         set_iommu_table_base_and_group(&dev->dev,
 901                                                        &pe->tce32_table);
 902                 else
 903                         set_iommu_table_base(&dev->dev, &pe->tce32_table);
 904
 905                 if (dev->subordinate)
 906                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
 907                                                add_to_iommu_group);
 908         }
 909 }
 910
 911 static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe,
 912                                          struct iommu_table *tbl,
 913                                          __be64 *startp, __be64 *endp, bool rm)
 914 {
 915         __be64 __iomem *invalidate = rm ?
 916                 (__be64 __iomem *)pe->tce_inval_reg_phys :
 917                 (__be64 __iomem *)tbl->it_index;
 918         unsigned long start, end, inc;
 919         const unsigned shift = tbl->it_page_shift;
 920
 921         start = __pa(startp);
 922         end = __pa(endp);
 923
 924         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
 925         if (tbl->it_busno) {
 926                 start <<= shift;
 927                 end <<= shift;
 928                 inc = 128ull << shift;
 929                 start |= tbl->it_busno;
 930                 end |= tbl->it_busno;
 931         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
 932                 /* p7ioc-style invalidation, 2 TCEs per write */
 933                 start |= (1ull << 63);
 934                 end |= (1ull << 63);
 935                 inc = 16;
 936         } else {
 937                 /* Default (older HW) */
 938                 inc = 128;
 939         }
 940
 941         end |= inc - 1; /* round up end to be different than start */
 942
 943         mb(); /* Ensure above stores are visible */
 944         while (start <= end) {
 945                 if (rm)
 946                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
 947                 else
 948                         __raw_writeq(cpu_to_be64(start), invalidate);
 949                 start += inc;
 950         }
 951
 952         /*
 953          * The iommu layer will do another mb() for us on build()
 954          * and we don't care on free()
 955          */
 956 }
 957
 958 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
 959                                          struct iommu_table *tbl,
 960                                          __be64 *startp, __be64 *endp, bool rm)
 961 {
 962         unsigned long start, end, inc;
 963         __be64 __iomem *invalidate = rm ?
 964                 (__be64 __iomem *)pe->tce_inval_reg_phys :
 965                 (__be64 __iomem *)tbl->it_index;
 966         const unsigned shift = tbl->it_page_shift;
 967
 968         /* We'll invalidate DMA address in PE scope */
 969         start = 0x2ull << 60;
 970         start |= (pe->pe_number & 0xFF);
 971         end = start;
 972
 973         /* Figure out the start, end and step */
 974         inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
 975         start |= (inc << shift);
 976         inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
 977         end |= (inc << shift);
 978         inc = (0x1ull << shift);
 979         mb();
 980
 981         while (start <= end) {
 982                 if (rm)
 983                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
 984                 else
 985                         __raw_writeq(cpu_to_be64(start), invalidate);
 986                 start += inc;
 987         }
 988 }
 989
 990 void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
 991                                  __be64 *startp, __be64 *endp, bool rm)
 992 {
 993         struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
 994                                               tce32_table);
 995         struct pnv_phb *phb = pe->phb;
 996
 997         if (phb->type == PNV_PHB_IODA1)
 998                 pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm);
 999         else
1000                 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm);
1001 }
1002
1003 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1004                                       struct pnv_ioda_pe *pe, unsigned int base,
1005                                       unsigned int segs)
1006 {
1007
1008         struct page *tce_mem = NULL;
1009         const __be64 *swinvp;
1010         struct iommu_table *tbl;
1011         unsigned int i;
1012         int64_t rc;
1013         void *addr;
1014
1015         /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
1016 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
1017
1018         /* XXX FIXME: Handle 64-bit only DMA devices */
1019         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1020         /* XXX FIXME: Allocate multi-level tables on PHB3 */
1021
1022         /* We shouldn't already have a 32-bit DMA associated */
1023         if (WARN_ON(pe->tce32_seg >= 0))
1024                 return;
1025
1026         /* Grab a 32-bit TCE table */
1027         pe->tce32_seg = base;
1028         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1029                 (base << 28), ((base + segs) << 28) - 1);
1030
1031         /* XXX Currently, we allocate one big contiguous table for the
1032          * TCEs. We only really need one chunk per 256M of TCE space
1033          * (ie per segment) but that's an optimization for later, it
1034          * requires some added smarts with our get/put_tce implementation
1035          */
1036         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1037                                    get_order(TCE32_TABLE_SIZE * segs));
1038         if (!tce_mem) {
1039                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1040                 goto fail;
1041         }
1042         addr = page_address(tce_mem);
1043         memset(addr, 0, TCE32_TABLE_SIZE * segs);
1044
1045         /* Configure HW */
1046         for (i = 0; i < segs; i++) {
1047                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1048                                               pe->pe_number,
1049                                               base + i, 1,
1050                                               __pa(addr) + TCE32_TABLE_SIZE * i,
1051                                               TCE32_TABLE_SIZE, 0x1000);
1052                 if (rc) {
1053                         pe_err(pe, " Failed to configure 32-bit TCE table,"
1054                                " err %ld\n", rc);
1055                         goto fail;
1056                 }
1057         }
1058
1059         /* Setup linux iommu table */
1060         tbl = &pe->tce32_table;
1061         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
1062                                   base << 28, IOMMU_PAGE_SHIFT_4K);
1063
1064         /* OPAL variant of P7IOC SW invalidated TCEs */
1065         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
1066         if (swinvp) {
1067                 /* We need a couple more fields -- an address and a data
1068                  * to or.  Since the bus is only printed out on table free
1069                  * errors, and on the first pass the data will be a relative
1070                  * bus number, print that out instead.
1071                  */
1072                 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
1073                 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
1074                                 8);
1075                 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
1076                                  TCE_PCI_SWINV_FREE   |
1077                                  TCE_PCI_SWINV_PAIR);
1078         }
1079         iommu_init_table(tbl, phb->hose->node);
1080         iommu_register_group(tbl, phb->hose->global_number, pe->pe_number);
1081
1082         if (pe->pdev)
1083                 set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
1084         else
1085                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
1086
1087         return;
1088  fail:
1089         /* XXX Failure: Try to fallback to 64-bit only ? */
1090         if (pe->tce32_seg >= 0)
1091                 pe->tce32_seg = -1;
1092         if (tce_mem)
1093                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
1094 }
1095
1096 static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
1097 {
1098         struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
1099                                               tce32_table);
1100         uint16_t window_id = (pe->pe_number << 1 ) + 1;
1101         int64_t rc;
1102
1103         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1104         if (enable) {
1105                 phys_addr_t top = memblock_end_of_DRAM();
1106
1107                 top = roundup_pow_of_two(top);
1108                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1109                                                      pe->pe_number,
1110                                                      window_id,
1111                                                      pe->tce_bypass_base,
1112                                                      top);
1113         } else {
1114                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1115                                                      pe->pe_number,
1116                                                      window_id,
1117                                                      pe->tce_bypass_base,
1118                                                      0);
1119
1120                 /*
1121                  * EEH needs the mapping between IOMMU table and group
1122                  * of those VFIO/KVM pass-through devices. We can postpone
1123                  * resetting DMA ops until the DMA mask is configured in
1124                  * host side.
1125                  */
1126                 if (pe->pdev)
1127                         set_iommu_table_base(&pe->pdev->dev, tbl);
1128                 else
1129                         pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
1130         }
1131         if (rc)
1132                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1133         else
1134                 pe->tce_bypass_enabled = enable;
1135 }
1136
1137 static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
1138                                           struct pnv_ioda_pe *pe)
1139 {
1140         /* TVE #1 is selected by PCI address bit 59 */
1141         pe->tce_bypass_base = 1ull << 59;
1142
1143         /* Install set_bypass callback for VFIO */
1144         pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass;
1145
1146         /* Enable bypass by default */
1147         pnv_pci_ioda2_set_bypass(&pe->tce32_table, true);
1148 }
1149
1150 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1151                                        struct pnv_ioda_pe *pe)
1152 {
1153         struct page *tce_mem = NULL;
1154         void *addr;
1155         const __be64 *swinvp;
1156         struct iommu_table *tbl;
1157         unsigned int tce_table_size, end;
1158         int64_t rc;
1159
1160         /* We shouldn't already have a 32-bit DMA associated */
1161         if (WARN_ON(pe->tce32_seg >= 0))
1162                 return;
1163
1164         /* The PE will reserve all possible 32-bits space */
1165         pe->tce32_seg = 0;
1166         end = (1 << ilog2(phb->ioda.m32_pci_base));
1167         tce_table_size = (end / 0x1000) * 8;
1168         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
1169                 end);
1170
1171         /* Allocate TCE table */
1172         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1173                                    get_order(tce_table_size));
1174         if (!tce_mem) {
1175                 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
1176                 goto fail;
1177         }
1178         addr = page_address(tce_mem);
1179         memset(addr, 0, tce_table_size);
1180
1181         /*
1182          * Map TCE table through TVT. The TVE index is the PE number
1183          * shifted by 1 bit for 32-bits DMA space.
1184          */
1185         rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1186                                         pe->pe_number << 1, 1, __pa(addr),
1187                                         tce_table_size, 0x1000);
1188         if (rc) {
1189                 pe_err(pe, "Failed to configure 32-bit TCE table,"
1190                        " err %ld\n", rc);
1191                 goto fail;
1192         }
1193
1194         /* Setup linux iommu table */
1195         tbl = &pe->tce32_table;
1196         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
1197                         IOMMU_PAGE_SHIFT_4K);
1198
1199         /* OPAL variant of PHB3 invalidated TCEs */
1200         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
1201         if (swinvp) {
1202                 /* We need a couple more fields -- an address and a data
1203                  * to or.  Since the bus is only printed out on table free
1204                  * errors, and on the first pass the data will be a relative
1205                  * bus number, print that out instead.
1206                  */
1207                 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
1208                 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
1209                                 8);
1210                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
1211         }
1212         iommu_init_table(tbl, phb->hose->node);
1213         iommu_register_group(tbl, phb->hose->global_number, pe->pe_number);
1214
1215         if (pe->pdev)
1216                 set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
1217         else
1218                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
1219
1220         /* Also create a bypass window */
1221         pnv_pci_ioda2_setup_bypass_pe(phb, pe);
1222         return;
1223 fail:
1224         if (pe->tce32_seg >= 0)
1225                 pe->tce32_seg = -1;
1226         if (tce_mem)
1227                 __free_pages(tce_mem, get_order(tce_table_size));
1228 }
1229
1230 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
1231 {
1232         struct pci_controller *hose = phb->hose;
1233         unsigned int residual, remaining, segs, tw, base;
1234         struct pnv_ioda_pe *pe;
1235
1236         /* If we have more PE# than segments available, hand out one
1237          * per PE until we run out and let the rest fail. If not,
1238          * then we assign at least one segment per PE, plus more based
1239          * on the amount of devices under that PE
1240          */
1241         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
1242                 residual = 0;
1243         else
1244                 residual = phb->ioda.tce32_count -
1245                         phb->ioda.dma_pe_count;
1246
1247         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
1248                 hose->global_number, phb->ioda.tce32_count);
1249         pr_info("PCI: %d PE# for a total weight of %d\n",
1250                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
1251
1252         /* Walk our PE list and configure their DMA segments, hand them
1253          * out one base segment plus any residual segments based on
1254          * weight
1255          */
1256         remaining = phb->ioda.tce32_count;
1257         tw = phb->ioda.dma_weight;
1258         base = 0;
1259         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
1260                 if (!pe->dma_weight)
1261                         continue;
1262                 if (!remaining) {
1263                         pe_warn(pe, "No DMA32 resources available\n");
1264                         continue;
1265                 }
1266                 segs = 1;
1267                 if (residual) {
1268                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
1269                         if (segs > remaining)
1270                                 segs = remaining;
1271                 }
1272
1273                 /*
1274                  * For IODA2 compliant PHB3, we needn't care about the weight.
1275                  * The all available 32-bits DMA space will be assigned to
1276                  * the specific PE.
1277                  */
1278                 if (phb->type == PNV_PHB_IODA1) {
1279                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
1280                                 pe->dma_weight, segs);
1281                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
1282                 } else {
1283                         pe_info(pe, "Assign DMA32 space\n");
1284                         segs = 0;
1285                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
1286                 }
1287
1288                 remaining -= segs;
1289                 base += segs;
1290         }
1291 }
1292
1293 #ifdef CONFIG_PCI_MSI
1294 static void pnv_ioda2_msi_eoi(struct irq_data *d)
1295 {
1296         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1297         struct irq_chip *chip = irq_data_get_irq_chip(d);
1298         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
1299                                            ioda.irq_chip);
1300         int64_t rc;
1301
1302         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
1303         WARN_ON_ONCE(rc);
1304
1305         icp_native_eoi(d);
1306 }
1307
1308 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
1309                                   unsigned int hwirq, unsigned int virq,
1310                                   unsigned int is_64, struct msi_msg *msg)
1311 {
1312         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
1313         struct pci_dn *pdn = pci_get_pdn(dev);
1314         struct irq_data *idata;
1315         struct irq_chip *ichip;
1316         unsigned int xive_num = hwirq - phb->msi_base;
1317         __be32 data;
1318         int rc;
1319
1320         /* No PE assigned ? bail out ... no MSI for you ! */
1321         if (pe == NULL)
1322                 return -ENXIO;
1323
1324         /* Check if we have an MVE */
1325         if (pe->mve_number < 0)
1326                 return -ENXIO;
1327
1328         /* Force 32-bit MSI on some broken devices */
1329         if (pdn && pdn->force_32bit_msi)
1330                 is_64 = 0;
1331
1332         /* Assign XIVE to PE */
1333         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
1334         if (rc) {
1335                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
1336                         pci_name(dev), rc, xive_num);
1337                 return -EIO;
1338         }
1339
1340         if (is_64) {
1341                 __be64 addr64;
1342
1343                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
1344                                      &addr64, &data);
1345                 if (rc) {
1346                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
1347                                 pci_name(dev), rc);
1348                         return -EIO;
1349                 }
1350                 msg->address_hi = be64_to_cpu(addr64) >> 32;
1351                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
1352         } else {
1353                 __be32 addr32;
1354
1355                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
1356                                      &addr32, &data);
1357                 if (rc) {
1358                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
1359                                 pci_name(dev), rc);
1360                         return -EIO;
1361                 }
1362                 msg->address_hi = 0;
1363                 msg->address_lo = be32_to_cpu(addr32);
1364         }
1365         msg->data = be32_to_cpu(data);
1366
1367         /*
1368          * Change the IRQ chip for the MSI interrupts on PHB3.
1369          * The corresponding IRQ chip should be populated for
1370          * the first time.
1371          */
1372         if (phb->type == PNV_PHB_IODA2) {
1373                 if (!phb->ioda.irq_chip_init) {
1374                         idata = irq_get_irq_data(virq);
1375                         ichip = irq_data_get_irq_chip(idata);
1376                         phb->ioda.irq_chip_init = 1;
1377                         phb->ioda.irq_chip = *ichip;
1378                         phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
1379                 }
1380
1381                 irq_set_chip(virq, &phb->ioda.irq_chip);
1382         }
1383
1384         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
1385                  " address=%x_%08x data=%x PE# %d\n",
1386                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
1387                  msg->address_hi, msg->address_lo, data, pe->pe_number);
1388
1389         return 0;
1390 }
1391
1392 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
1393 {
1394         unsigned int count;
1395         const __be32 *prop = of_get_property(phb->hose->dn,
1396                                              "ibm,opal-msi-ranges", NULL);
1397         if (!prop) {
1398                 /* BML Fallback */
1399                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
1400         }
1401         if (!prop)
1402                 return;
1403
1404         phb->msi_base = be32_to_cpup(prop);
1405         count = be32_to_cpup(prop + 1);
1406         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
1407                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
1408                        phb->hose->global_number);
1409                 return;
1410         }
1411
1412         phb->msi_setup = pnv_pci_ioda_msi_setup;
1413         phb->msi32_support = 1;
1414         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
1415                 count, phb->msi_base);
1416 }
1417 #else
1418 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
1419 #endif /* CONFIG_PCI_MSI */
1420
1421 /*
1422  * This function is supposed to be called on basis of PE from top
1423  * to bottom style. So the the I/O or MMIO segment assigned to
1424  * parent PE could be overrided by its child PEs if necessary.
1425  */
1426 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
1427                                   struct pnv_ioda_pe *pe)
1428 {
1429         struct pnv_phb *phb = hose->private_data;
1430         struct pci_bus_region region;
1431         struct resource *res;
1432         int i, index;
1433         int rc;
1434
1435         /*
1436          * NOTE: We only care PCI bus based PE for now. For PCI
1437          * device based PE, for example SRIOV sensitive VF should
1438          * be figured out later.
1439          */
1440         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
1441
1442         pci_bus_for_each_resource(pe->pbus, res, i) {
1443                 if (!res || !res->flags ||
1444                     res->start > res->end)
1445                         continue;
1446
1447                 if (res->flags & IORESOURCE_IO) {
1448                         region.start = res->start - phb->ioda.io_pci_base;
1449                         region.end   = res->end - phb->ioda.io_pci_base;
1450                         index = region.start / phb->ioda.io_segsize;
1451
1452                         while (index < phb->ioda.total_pe &&
1453                                region.start <= region.end) {
1454                                 phb->ioda.io_segmap[index] = pe->pe_number;
1455                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1456                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
1457                                 if (rc != OPAL_SUCCESS) {
1458                                         pr_err("%s: OPAL error %d when mapping IO "
1459                                                "segment #%d to PE#%d\n",
1460                                                __func__, rc, index, pe->pe_number);
1461                                         break;
1462                                 }
1463
1464                                 region.start += phb->ioda.io_segsize;
1465                                 index++;
1466                         }
1467                 } else if (res->flags & IORESOURCE_MEM) {
1468                         region.start = res->start -
1469                                        hose->mem_offset[0] -
1470                                        phb->ioda.m32_pci_base;
1471                         region.end   = res->end -
1472                                        hose->mem_offset[0] -
1473                                        phb->ioda.m32_pci_base;
1474                         index = region.start / phb->ioda.m32_segsize;
1475
1476                         while (index < phb->ioda.total_pe &&
1477                                region.start <= region.end) {
1478                                 phb->ioda.m32_segmap[index] = pe->pe_number;
1479                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1480                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
1481                                 if (rc != OPAL_SUCCESS) {
1482                                         pr_err("%s: OPAL error %d when mapping M32 "
1483                                                "segment#%d to PE#%d",
1484                                                __func__, rc, index, pe->pe_number);
1485                                         break;
1486                                 }
1487
1488                                 region.start += phb->ioda.m32_segsize;
1489                                 index++;
1490                         }
1491                 }
1492         }
1493 }
1494
1495 static void pnv_pci_ioda_setup_seg(void)
1496 {
1497         struct pci_controller *tmp, *hose;
1498         struct pnv_phb *phb;
1499         struct pnv_ioda_pe *pe;
1500
1501         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1502                 phb = hose->private_data;
1503                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
1504                         pnv_ioda_setup_pe_seg(hose, pe);
1505                 }
1506         }
1507 }
1508
1509 static void pnv_pci_ioda_setup_DMA(void)
1510 {
1511         struct pci_controller *hose, *tmp;
1512         struct pnv_phb *phb;
1513
1514         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1515                 pnv_ioda_setup_dma(hose->private_data);
1516
1517                 /* Mark the PHB initialization done */
1518                 phb = hose->private_data;
1519                 phb->initialized = 1;
1520         }
1521 }
1522
1523 static void pnv_pci_ioda_create_dbgfs(void)
1524 {
1525 #ifdef CONFIG_DEBUG_FS
1526         struct pci_controller *hose, *tmp;
1527         struct pnv_phb *phb;
1528         char name[16];
1529
1530         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1531                 phb = hose->private_data;
1532
1533                 sprintf(name, "PCI%04x", hose->global_number);
1534                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
1535                 if (!phb->dbgfs)
1536                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
1537                                 __func__, hose->global_number);
1538         }
1539 #endif /* CONFIG_DEBUG_FS */
1540 }
1541
1542 static void pnv_pci_ioda_fixup(void)
1543 {
1544         pnv_pci_ioda_setup_PEs();
1545         pnv_pci_ioda_setup_seg();
1546         pnv_pci_ioda_setup_DMA();
1547
1548         pnv_pci_ioda_create_dbgfs();
1549
1550 #ifdef CONFIG_EEH
1551         eeh_init();
1552         eeh_addr_cache_build();
1553 #endif
1554 }
1555
1556 /*
1557  * Returns the alignment for I/O or memory windows for P2P
1558  * bridges. That actually depends on how PEs are segmented.
1559  * For now, we return I/O or M32 segment size for PE sensitive
1560  * P2P bridges. Otherwise, the default values (4KiB for I/O,
1561  * 1MiB for memory) will be returned.
1562  *
1563  * The current PCI bus might be put into one PE, which was
1564  * create against the parent PCI bridge. For that case, we
1565  * needn't enlarge the alignment so that we can save some
1566  * resources.
1567  */
1568 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
1569                                                 unsigned long type)
1570 {
1571         struct pci_dev *bridge;
1572         struct pci_controller *hose = pci_bus_to_host(bus);
1573         struct pnv_phb *phb = hose->private_data;
1574         int num_pci_bridges = 0;
1575
1576         bridge = bus->self;
1577         while (bridge) {
1578                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
1579                         num_pci_bridges++;
1580                         if (num_pci_bridges >= 2)
1581                                 return 1;
1582                 }
1583
1584                 bridge = bridge->bus->self;
1585         }
1586
1587         /* We fail back to M32 if M64 isn't supported */
1588         if (phb->ioda.m64_segsize &&
1589             pnv_pci_is_mem_pref_64(type))
1590                 return phb->ioda.m64_segsize;
1591         if (type & IORESOURCE_MEM)
1592                 return phb->ioda.m32_segsize;
1593
1594         return phb->ioda.io_segsize;
1595 }
1596
1597 /* Prevent enabling devices for which we couldn't properly
1598  * assign a PE
1599  */
1600 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
1601 {
1602         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1603         struct pnv_phb *phb = hose->private_data;
1604         struct pci_dn *pdn;
1605
1606         /* The function is probably called while the PEs have
1607          * not be created yet. For example, resource reassignment
1608          * during PCI probe period. We just skip the check if
1609          * PEs isn't ready.
1610          */
1611         if (!phb->initialized)
1612                 return 0;
1613
1614         pdn = pci_get_pdn(dev);
1615         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1616                 return -EINVAL;
1617
1618         return 0;
1619 }
1620
1621 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
1622                                u32 devfn)
1623 {
1624         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
1625 }
1626
1627 static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
1628 {
1629         opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET,
1630                        OPAL_ASSERT_RESET);
1631 }
1632
1633 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
1634                                          u64 hub_id, int ioda_type)
1635 {
1636         struct pci_controller *hose;
1637         struct pnv_phb *phb;
1638         unsigned long size, m32map_off, pemap_off, iomap_off = 0;
1639         const __be64 *prop64;
1640         const __be32 *prop32;
1641         int len;
1642         u64 phb_id;
1643         void *aux;
1644         long rc;
1645
1646         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
1647
1648         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
1649         if (!prop64) {
1650                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
1651                 return;
1652         }
1653         phb_id = be64_to_cpup(prop64);
1654         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
1655
1656         phb = alloc_bootmem(sizeof(struct pnv_phb));
1657         if (!phb) {
1658                 pr_err("  Out of memory !\n");
1659                 return;
1660         }
1661
1662         /* Allocate PCI controller */
1663         memset(phb, 0, sizeof(struct pnv_phb));
1664         phb->hose = hose = pcibios_alloc_controller(np);
1665         if (!phb->hose) {
1666                 pr_err("  Can't allocate PCI controller for %s\n",
1667                        np->full_name);
1668                 free_bootmem((unsigned long)phb, sizeof(struct pnv_phb));
1669                 return;
1670         }
1671
1672         spin_lock_init(&phb->lock);
1673         prop32 = of_get_property(np, "bus-range", &len);
1674         if (prop32 && len == 8) {
1675                 hose->first_busno = be32_to_cpu(prop32[0]);
1676                 hose->last_busno = be32_to_cpu(prop32[1]);
1677         } else {
1678                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
1679                 hose->first_busno = 0;
1680                 hose->last_busno = 0xff;
1681         }
1682         hose->private_data = phb;
1683         phb->hub_id = hub_id;
1684         phb->opal_id = phb_id;
1685         phb->type = ioda_type;
1686
1687         /* Detect specific models for error handling */
1688         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
1689                 phb->model = PNV_PHB_MODEL_P7IOC;
1690         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
1691                 phb->model = PNV_PHB_MODEL_PHB3;
1692         else
1693                 phb->model = PNV_PHB_MODEL_UNKNOWN;
1694
1695         /* Parse 32-bit and IO ranges (if any) */
1696         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
1697
1698         /* Get registers */
1699         phb->regs = of_iomap(np, 0);
1700         if (phb->regs == NULL)
1701                 pr_err("  Failed to map registers !\n");
1702
1703         /* Initialize more IODA stuff */
1704         phb->ioda.total_pe = 1;
1705         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
1706         if (prop32)
1707                 phb->ioda.total_pe = be32_to_cpup(prop32);
1708         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
1709         if (prop32)
1710                 phb->ioda.reserved_pe = be32_to_cpup(prop32);
1711
1712         /* Parse 64-bit MMIO range */
1713         pnv_ioda_parse_m64_window(phb);
1714
1715         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
1716         /* FW Has already off top 64k of M32 space (MSI space) */
1717         phb->ioda.m32_size += 0x10000;
1718
1719         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
1720         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
1721         phb->ioda.io_size = hose->pci_io_size;
1722         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
1723         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
1724
1725         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
1726         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
1727         m32map_off = size;
1728         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
1729         if (phb->type == PNV_PHB_IODA1) {
1730                 iomap_off = size;
1731                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
1732         }
1733         pemap_off = size;
1734         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
1735         aux = alloc_bootmem(size);
1736         memset(aux, 0, size);
1737         phb->ioda.pe_alloc = aux;
1738         phb->ioda.m32_segmap = aux + m32map_off;
1739         if (phb->type == PNV_PHB_IODA1)
1740                 phb->ioda.io_segmap = aux + iomap_off;
1741         phb->ioda.pe_array = aux + pemap_off;
1742         set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
1743
1744         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
1745         INIT_LIST_HEAD(&phb->ioda.pe_list);
1746
1747         /* Calculate how many 32-bit TCE segments we have */
1748         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
1749
1750 #if 0 /* We should really do that ... */
1751         rc = opal_pci_set_phb_mem_window(opal->phb_id,
1752                                          window_type,
1753                                          window_num,
1754                                          starting_real_address,
1755                                          starting_pci_address,
1756                                          segment_size);
1757 #endif
1758
1759         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
1760                 phb->ioda.total_pe, phb->ioda.reserved_pe,
1761                 phb->ioda.m32_size, phb->ioda.m32_segsize);
1762         if (phb->ioda.m64_size)
1763                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
1764                         phb->ioda.m64_size, phb->ioda.m64_segsize);
1765         if (phb->ioda.io_size)
1766                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
1767                         phb->ioda.io_size, phb->ioda.io_segsize);
1768
1769
1770         phb->hose->ops = &pnv_pci_ops;
1771         phb->get_pe_state = pnv_ioda_get_pe_state;
1772         phb->freeze_pe = pnv_ioda_freeze_pe;
1773         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
1774 #ifdef CONFIG_EEH
1775         phb->eeh_ops = &ioda_eeh_ops;
1776 #endif
1777
1778         /* Setup RID -> PE mapping function */
1779         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
1780
1781         /* Setup TCEs */
1782         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
1783         phb->dma_set_mask = pnv_pci_ioda_dma_set_mask;
1784
1785         /* Setup shutdown function for kexec */
1786         phb->shutdown = pnv_pci_ioda_shutdown;
1787
1788         /* Setup MSI support */
1789         pnv_pci_init_ioda_msis(phb);
1790
1791         /*
1792          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
1793          * to let the PCI core do resource assignment. It's supposed
1794          * that the PCI core will do correct I/O and MMIO alignment
1795          * for the P2P bridge bars so that each PCI bus (excluding
1796          * the child P2P bridges) can form individual PE.
1797          */
1798         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
1799         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1800         ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
1801         ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus;
1802         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1803
1804         /* Reset IODA tables to a clean state */
1805         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1806         if (rc)
1807                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
1808
1809         /* If we're running in kdump kerenl, the previous kerenl never
1810          * shutdown PCI devices correctly. We already got IODA table
1811          * cleaned out. So we have to issue PHB reset to stop all PCI
1812          * transactions from previous kerenl.
1813          */
1814         if (is_kdump_kernel()) {
1815                 pr_info("  Issue PHB reset ...\n");
1816                 ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
1817                 ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET);
1818         }
1819
1820         /* Configure M64 window */
1821         if (phb->init_m64 && phb->init_m64(phb))
1822                 hose->mem_resources[1].flags = 0;
1823 }
1824
1825 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
1826 {
1827         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
1828 }
1829
1830 void __init pnv_pci_init_ioda_hub(struct device_node *np)
1831 {
1832         struct device_node *phbn;
1833         const __be64 *prop64;
1834         u64 hub_id;
1835
1836         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1837
1838         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1839         if (!prop64) {
1840                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1841                 return;
1842         }
1843         hub_id = be64_to_cpup(prop64);
1844         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1845
1846         /* Count child PHBs */
1847         for_each_child_of_node(np, phbn) {
1848                 /* Look for IODA1 PHBs */
1849                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1850                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
1851         }
1852 }