1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN,
20 #define PNV_PCI_DIAG_BUF_SIZE 8192
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
25 /* Data associated with a PE, including IOMMU tracking etc.. */
31 /* A PE can be associated with a single device or an
32 * entire bus (& children). In the former case, pdev
33 * is populated, in the later case, pbus is.
38 /* Effective RID (device RID for a device PE and base bus
39 * RID with devfn 0 for a bus PE)
44 unsigned int pe_number;
46 /* "Weight" assigned to the PE for the sake of DMA resource
49 unsigned int dma_weight;
51 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
54 struct iommu_table tce32_table;
55 phys_addr_t tce_inval_reg_phys;
57 /* 64-bit TCE bypass region */
58 bool tce_bypass_enabled;
59 uint64_t tce_bypass_base;
61 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
62 * and -1 if not supported. (It's actually identical to the
67 /* Link in list of PE#s */
68 struct list_head dma_link;
69 struct list_head list;
72 /* IOC dependent EEH operations */
75 int (*post_init)(struct pci_controller *hose);
76 int (*set_option)(struct eeh_pe *pe, int option);
77 int (*get_state)(struct eeh_pe *pe);
78 int (*reset)(struct eeh_pe *pe, int option);
79 int (*get_log)(struct eeh_pe *pe, int severity,
80 char *drv_log, unsigned long len);
81 int (*configure_bridge)(struct eeh_pe *pe);
82 int (*next_error)(struct eeh_pe **pe);
85 #define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */
86 #define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */
88 #endif /* CONFIG_EEH */
91 struct pci_controller *hose;
92 enum pnv_phb_type type;
93 enum pnv_phb_model model;
101 struct pnv_eeh_ops *eeh_ops;
105 #ifdef CONFIG_DEBUG_FS
106 struct dentry *dbgfs;
109 #ifdef CONFIG_PCI_MSI
110 unsigned int msi_base;
111 unsigned int msi32_support;
112 struct msi_bitmap msi_bmp;
114 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
115 unsigned int hwirq, unsigned int virq,
116 unsigned int is_64, struct msi_msg *msg);
117 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
118 int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
120 void (*fixup_phb)(struct pci_controller *hose);
121 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
122 void (*shutdown)(struct pnv_phb *phb);
126 struct iommu_table iommu_table;
130 /* Global bridge info */
131 unsigned int total_pe;
132 unsigned int reserved_pe;
133 unsigned int m32_size;
134 unsigned int m32_segsize;
135 unsigned int m32_pci_base;
136 unsigned int io_size;
137 unsigned int io_segsize;
138 unsigned int io_pci_base;
140 /* PE allocation bitmap */
141 unsigned long *pe_alloc;
143 /* M32 & IO segment maps */
144 unsigned int *m32_segmap;
145 unsigned int *io_segmap;
146 struct pnv_ioda_pe *pe_array;
150 struct irq_chip irq_chip;
152 /* Sorted list of used PE's based
153 * on the sequence of creation
155 struct list_head pe_list;
157 /* Reverse map of PEs, will have to extend if
158 * we are to support more than 256 PEs, indexed
161 unsigned char pe_rmap[0x10000];
163 /* 32-bit TCE tables allocation */
164 unsigned long tce32_count;
166 /* Total "weight" for the sake of DMA resources
169 unsigned int dma_weight;
170 unsigned int dma_pe_count;
172 /* Sorted list of used PE's, sorted at
173 * boot for resource allocation purposes
175 struct list_head pe_dma_list;
179 /* PHB and hub status structure */
181 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
182 struct OpalIoP7IOCPhbErrorData p7ioc;
183 struct OpalIoPhb3ErrorData phb3;
184 struct OpalIoP7IOCErrorData hub_diag;
189 extern struct pci_ops pnv_pci_ops;
191 extern struct pnv_eeh_ops ioda_eeh_ops;
194 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
195 unsigned char *log_buff);
196 int pnv_pci_cfg_read(struct device_node *dn,
197 int where, int size, u32 *val);
198 int pnv_pci_cfg_write(struct device_node *dn,
199 int where, int size, u32 val);
200 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
201 void *tce_mem, u64 tce_size,
203 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
204 extern void pnv_pci_init_ioda_hub(struct device_node *np);
205 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
206 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
207 __be64 *startp, __be64 *endp, bool rm);
209 #endif /* __POWERNV_PCI_H */