2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/init.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/sched.h> /* for show_stack */
33 #include <linux/string.h>
34 #include <linux/pci.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/crash_dump.h>
37 #include <linux/memory.h>
41 #include <asm/iommu.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/abs_addr.h>
45 #include <asm/pSeries_reconfig.h>
46 #include <asm/firmware.h>
48 #include <asm/ppc-pci.h>
50 #include <asm/mmzone.h>
52 #include "plpar_wrappers.h"
55 static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
56 u64 *startp, u64 *endp)
58 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
59 unsigned long start, end, inc;
63 inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
65 /* If this is non-zero, change the format. We shift the
66 * address and or in the magic from the device tree. */
71 start |= tbl->it_busno;
75 end |= inc - 1; /* round up end to be different than start */
77 mb(); /* Make sure TCEs in memory are written */
78 while (start <= end) {
79 out_be64(invalidate, start);
84 static int tce_build_pSeries(struct iommu_table *tbl, long index,
85 long npages, unsigned long uaddr,
86 enum dma_data_direction direction,
87 struct dma_attrs *attrs)
93 proto_tce = TCE_PCI_READ; // Read allowed
95 if (direction != DMA_TO_DEVICE)
96 proto_tce |= TCE_PCI_WRITE;
98 tces = tcep = ((u64 *)tbl->it_base) + index;
101 /* can't move this out since we might cross MEMBLOCK boundary */
102 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
103 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
105 uaddr += TCE_PAGE_SIZE;
109 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
110 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
115 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
119 tces = tcep = ((u64 *)tbl->it_base) + index;
124 if (tbl->it_type & TCE_PCI_SWINV_FREE)
125 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
128 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
132 tcep = ((u64 *)tbl->it_base) + index;
137 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
138 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
140 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
141 long npages, unsigned long uaddr,
142 enum dma_data_direction direction,
143 struct dma_attrs *attrs)
149 long tcenum_start = tcenum, npages_start = npages;
151 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
152 proto_tce = TCE_PCI_READ;
153 if (direction != DMA_TO_DEVICE)
154 proto_tce |= TCE_PCI_WRITE;
157 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
158 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
160 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
162 tce_free_pSeriesLP(tbl, tcenum_start,
163 (npages_start - (npages + 1)));
167 if (rc && printk_ratelimit()) {
168 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
169 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
170 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
171 printk("\ttce val = 0x%llx\n", tce );
172 show_stack(current, (unsigned long *)__get_SP());
181 static DEFINE_PER_CPU(u64 *, tce_page);
183 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
184 long npages, unsigned long uaddr,
185 enum dma_data_direction direction,
186 struct dma_attrs *attrs)
193 long tcenum_start = tcenum, npages_start = npages;
197 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
201 tcep = __get_cpu_var(tce_page);
203 /* This is safe to do since interrupts are off when we're called
204 * from iommu_alloc{,_sg}()
207 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
208 /* If allocation fails, fall back to the loop implementation */
210 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
213 __get_cpu_var(tce_page) = tcep;
216 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
217 proto_tce = TCE_PCI_READ;
218 if (direction != DMA_TO_DEVICE)
219 proto_tce |= TCE_PCI_WRITE;
221 /* We can map max one pageful of TCEs at a time */
224 * Set up the page with TCE data, looping through and setting
227 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
229 for (l = 0; l < limit; l++) {
230 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
234 rc = plpar_tce_put_indirect((u64)tbl->it_index,
236 (u64)virt_to_abs(tcep),
241 } while (npages > 0 && !rc);
243 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
245 tce_freemulti_pSeriesLP(tbl, tcenum_start,
246 (npages_start - (npages + limit)));
250 if (rc && printk_ratelimit()) {
251 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
252 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
253 printk("\tnpages = 0x%llx\n", (u64)npages);
254 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
255 show_stack(current, (unsigned long *)__get_SP());
260 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
265 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
267 if (rc && printk_ratelimit()) {
268 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
269 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
270 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
271 show_stack(current, (unsigned long *)__get_SP());
279 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
283 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
285 if (rc && printk_ratelimit()) {
286 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
287 printk("\trc = %lld\n", rc);
288 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
289 printk("\tnpages = 0x%llx\n", (u64)npages);
290 show_stack(current, (unsigned long *)__get_SP());
294 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
297 unsigned long tce_ret;
299 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
301 if (rc && printk_ratelimit()) {
302 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
303 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
304 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
305 show_stack(current, (unsigned long *)__get_SP());
311 /* this is compatible with cells for the device tree property */
312 struct dynamic_dma_window_prop {
313 __be32 liobn; /* tce table number */
314 __be64 dma_base; /* address hi,lo */
315 __be32 tce_shift; /* ilog2(tce_page_size) */
316 __be32 window_shift; /* ilog2(tce_window_size) */
319 struct direct_window {
320 struct device_node *device;
321 const struct dynamic_dma_window_prop *prop;
322 struct list_head list;
325 /* Dynamic DMA Window support */
326 struct ddw_query_response {
327 u32 windows_available;
328 u32 largest_available_block;
330 u32 migration_capable;
333 struct ddw_create_response {
339 static LIST_HEAD(direct_window_list);
340 /* prevents races between memory on/offline and window creation */
341 static DEFINE_SPINLOCK(direct_window_list_lock);
342 /* protects initializing window twice for same device */
343 static DEFINE_MUTEX(direct_window_init_mutex);
344 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
346 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
347 unsigned long num_pfn, const void *arg)
349 const struct dynamic_dma_window_prop *maprange = arg;
351 u64 tce_size, num_tce, dma_offset, next;
355 tce_shift = be32_to_cpu(maprange->tce_shift);
356 tce_size = 1ULL << tce_shift;
357 next = start_pfn << PAGE_SHIFT;
358 num_tce = num_pfn << PAGE_SHIFT;
360 /* round back to the beginning of the tce page size */
361 num_tce += next & (tce_size - 1);
362 next &= ~(tce_size - 1);
364 /* covert to number of tces */
365 num_tce |= tce_size - 1;
366 num_tce >>= tce_shift;
370 * Set up the page with TCE data, looping through and setting
373 limit = min_t(long, num_tce, 512);
374 dma_offset = next + be64_to_cpu(maprange->dma_base);
376 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
380 } while (num_tce > 0 && !rc);
385 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
386 unsigned long num_pfn, const void *arg)
388 const struct dynamic_dma_window_prop *maprange = arg;
389 u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
394 local_irq_disable(); /* to protect tcep and the page behind it */
395 tcep = __get_cpu_var(tce_page);
398 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
403 __get_cpu_var(tce_page) = tcep;
406 proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
408 liobn = (u64)be32_to_cpu(maprange->liobn);
409 tce_shift = be32_to_cpu(maprange->tce_shift);
410 tce_size = 1ULL << tce_shift;
411 next = start_pfn << PAGE_SHIFT;
412 num_tce = num_pfn << PAGE_SHIFT;
414 /* round back to the beginning of the tce page size */
415 num_tce += next & (tce_size - 1);
416 next &= ~(tce_size - 1);
418 /* covert to number of tces */
419 num_tce |= tce_size - 1;
420 num_tce >>= tce_shift;
422 /* We can map max one pageful of TCEs at a time */
425 * Set up the page with TCE data, looping through and setting
428 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
429 dma_offset = next + be64_to_cpu(maprange->dma_base);
431 for (l = 0; l < limit; l++) {
432 tcep[l] = proto_tce | next;
436 rc = plpar_tce_put_indirect(liobn,
438 (u64)virt_to_abs(tcep),
442 } while (num_tce > 0 && !rc);
444 /* error cleanup: caller will clear whole range */
450 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
451 unsigned long num_pfn, void *arg)
453 return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
458 static void iommu_table_setparms(struct pci_controller *phb,
459 struct device_node *dn,
460 struct iommu_table *tbl)
462 struct device_node *node;
463 const unsigned long *basep, *sw_inval;
468 basep = of_get_property(node, "linux,tce-base", NULL);
469 sizep = of_get_property(node, "linux,tce-size", NULL);
470 if (basep == NULL || sizep == NULL) {
471 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
472 "missing tce entries !\n", dn->full_name);
476 tbl->it_base = (unsigned long)__va(*basep);
478 if (!is_kdump_kernel())
479 memset((void *)tbl->it_base, 0, *sizep);
481 tbl->it_busno = phb->bus->number;
483 /* Units of tce entries */
484 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
486 /* Test if we are going over 2GB of DMA space */
487 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
488 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
489 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
492 phb->dma_window_base_cur += phb->dma_window_size;
494 /* Set the tce table size - measured in entries */
495 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
498 tbl->it_blocksize = 16;
499 tbl->it_type = TCE_PCI;
501 sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
504 * This property contains information on how to
505 * invalidate the TCE entry. The first property is
506 * the base MMIO address used to invalidate entries.
507 * The second property tells us the format of the TCE
508 * invalidate (whether it needs to be shifted) and
509 * some magic routing info to add to our invalidate
512 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
513 tbl->it_busno = sw_inval[1]; /* overload this with magic */
514 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
519 * iommu_table_setparms_lpar
521 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
523 static void iommu_table_setparms_lpar(struct pci_controller *phb,
524 struct device_node *dn,
525 struct iommu_table *tbl,
526 const void *dma_window)
528 unsigned long offset, size;
530 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
532 tbl->it_busno = phb->bus->number;
534 tbl->it_blocksize = 16;
535 tbl->it_type = TCE_PCI;
536 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
537 tbl->it_size = size >> IOMMU_PAGE_SHIFT;
540 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
542 struct device_node *dn;
543 struct iommu_table *tbl;
544 struct device_node *isa_dn, *isa_dn_orig;
545 struct device_node *tmp;
549 dn = pci_bus_to_OF_node(bus);
551 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
554 /* This is not a root bus, any setup will be done for the
555 * device-side of the bridge in iommu_dev_setup_pSeries().
561 /* Check if the ISA bus on the system is under
564 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
566 while (isa_dn && isa_dn != dn)
567 isa_dn = isa_dn->parent;
570 of_node_put(isa_dn_orig);
572 /* Count number of direct PCI children of the PHB. */
573 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
576 pr_debug("Children: %d\n", children);
578 /* Calculate amount of DMA window per slot. Each window must be
579 * a power of two (due to pci_alloc_consistent requirements).
581 * Keep 256MB aside for PHBs with ISA.
585 /* No ISA/IDE - just set window size and return */
586 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
588 while (pci->phb->dma_window_size * children > 0x80000000ul)
589 pci->phb->dma_window_size >>= 1;
590 pr_debug("No ISA/IDE, window size is 0x%llx\n",
591 pci->phb->dma_window_size);
592 pci->phb->dma_window_base_cur = 0;
597 /* If we have ISA, then we probably have an IDE
598 * controller too. Allocate a 128MB table but
599 * skip the first 128MB to avoid stepping on ISA
602 pci->phb->dma_window_size = 0x8000000ul;
603 pci->phb->dma_window_base_cur = 0x8000000ul;
605 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
608 iommu_table_setparms(pci->phb, dn, tbl);
609 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
611 /* Divide the rest (1.75GB) among the children */
612 pci->phb->dma_window_size = 0x80000000ul;
613 while (pci->phb->dma_window_size * children > 0x70000000ul)
614 pci->phb->dma_window_size >>= 1;
616 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
620 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
622 struct iommu_table *tbl;
623 struct device_node *dn, *pdn;
625 const void *dma_window = NULL;
627 dn = pci_bus_to_OF_node(bus);
629 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
632 /* Find nearest ibm,dma-window, walking up the device tree */
633 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
634 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
635 if (dma_window != NULL)
639 if (dma_window == NULL) {
640 pr_debug(" no ibm,dma-window property !\n");
646 pr_debug(" parent is %s, iommu_table: 0x%p\n",
647 pdn->full_name, ppci->iommu_table);
649 if (!ppci->iommu_table) {
650 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
652 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
653 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
654 pr_debug(" created table: %p\n", ppci->iommu_table);
659 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
661 struct device_node *dn;
662 struct iommu_table *tbl;
664 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
666 dn = dev->dev.of_node;
668 /* If we're the direct child of a root bus, then we need to allocate
669 * an iommu table ourselves. The bus setup code should have setup
670 * the window sizes already.
672 if (!dev->bus->self) {
673 struct pci_controller *phb = PCI_DN(dn)->phb;
675 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
676 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
678 iommu_table_setparms(phb, dn, tbl);
679 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
680 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
684 /* If this device is further down the bus tree, search upwards until
685 * an already allocated iommu table is found and use that.
688 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
691 if (dn && PCI_DN(dn))
692 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
694 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
698 static int __read_mostly disable_ddw;
700 static int __init disable_ddw_setup(char *str)
703 printk(KERN_INFO "ppc iommu: disabling ddw.\n");
708 early_param("disable_ddw", disable_ddw_setup);
710 static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn)
714 ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
716 pr_warning("%s: failed to remove DMA window: rtas returned "
717 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
718 np->full_name, ret, ddw_avail[2], liobn);
720 pr_debug("%s: successfully removed DMA window: rtas returned "
721 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
722 np->full_name, ret, ddw_avail[2], liobn);
725 static void remove_ddw(struct device_node *np)
727 struct dynamic_dma_window_prop *dwp;
728 struct property *win64;
729 const u32 *ddw_avail;
733 ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len);
734 win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
738 if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp))
742 liobn = (u64)be32_to_cpu(dwp->liobn);
744 /* clear the whole window, note the arg is in kernel pages */
745 ret = tce_clearrange_multi_pSeriesLP(0,
746 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
748 pr_warning("%s failed to clear tces in window.\n",
751 pr_debug("%s successfully cleared tces in window.\n",
754 __remove_ddw(np, ddw_avail, liobn);
757 ret = prom_remove_property(np, win64);
759 pr_warning("%s: failed to remove direct window property: %d\n",
763 static u64 find_existing_ddw(struct device_node *pdn)
765 struct direct_window *window;
766 const struct dynamic_dma_window_prop *direct64;
769 spin_lock(&direct_window_list_lock);
770 /* check if we already created a window and dupe that config if so */
771 list_for_each_entry(window, &direct_window_list, list) {
772 if (window->device == pdn) {
773 direct64 = window->prop;
774 dma_addr = direct64->dma_base;
778 spin_unlock(&direct_window_list_lock);
783 static int find_existing_ddw_windows(void)
786 struct device_node *pdn;
787 struct direct_window *window;
788 const struct dynamic_dma_window_prop *direct64;
790 if (!firmware_has_feature(FW_FEATURE_LPAR))
793 for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
794 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
798 window = kzalloc(sizeof(*window), GFP_KERNEL);
799 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
805 window->device = pdn;
806 window->prop = direct64;
807 spin_lock(&direct_window_list_lock);
808 list_add(&window->list, &direct_window_list);
809 spin_unlock(&direct_window_list_lock);
814 machine_arch_initcall(pseries, find_existing_ddw_windows);
816 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
817 struct ddw_query_response *query)
819 struct eeh_dev *edev;
825 * Get the config address and phb buid of the PE window.
826 * Rely on eeh to retrieve this for us.
827 * Retrieve them from the pci device, not the node with the
828 * dma-window property
830 edev = pci_dev_to_eeh_dev(dev);
831 cfg_addr = edev->config_addr;
832 if (edev->pe_config_addr)
833 cfg_addr = edev->pe_config_addr;
834 buid = edev->phb->buid;
836 ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
837 cfg_addr, BUID_HI(buid), BUID_LO(buid));
838 dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
839 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
844 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
845 struct ddw_create_response *create, int page_shift,
848 struct eeh_dev *edev;
854 * Get the config address and phb buid of the PE window.
855 * Rely on eeh to retrieve this for us.
856 * Retrieve them from the pci device, not the node with the
857 * dma-window property
859 edev = pci_dev_to_eeh_dev(dev);
860 cfg_addr = edev->config_addr;
861 if (edev->pe_config_addr)
862 cfg_addr = edev->pe_config_addr;
863 buid = edev->phb->buid;
866 /* extra outputs are LIOBN and dma-addr (hi, lo) */
867 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr,
868 BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
869 } while (rtas_busy_delay(ret));
871 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
872 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
873 cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
874 window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
879 static void restore_default_window(struct pci_dev *dev,
880 u32 ddw_restore_token, unsigned long liobn)
882 struct eeh_dev *edev;
888 * Get the config address and phb buid of the PE window.
889 * Rely on eeh to retrieve this for us.
890 * Retrieve them from the pci device, not the node with the
891 * dma-window property
893 edev = pci_dev_to_eeh_dev(dev);
894 cfg_addr = edev->config_addr;
895 if (edev->pe_config_addr)
896 cfg_addr = edev->pe_config_addr;
897 buid = edev->phb->buid;
900 ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr,
901 BUID_HI(buid), BUID_LO(buid));
902 } while (rtas_busy_delay(ret));
904 "ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n",
905 ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret);
909 * If the PE supports dynamic dma windows, and there is space for a table
910 * that can map all pages in a linear offset, then setup such a table,
911 * and record the dma-offset in the struct device.
913 * dev: the pci device we are checking
914 * pdn: the parent pe node with the ibm,dma_window property
915 * Future: also check if we can remap the base window for our base page size
917 * returns the dma offset for use by dma_set_mask
919 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
922 struct ddw_query_response query;
923 struct ddw_create_response create;
925 u64 dma_addr, max_addr;
926 struct device_node *dn;
927 const u32 *uninitialized_var(ddw_avail);
928 const u32 *uninitialized_var(ddw_extensions);
929 u32 ddw_restore_token = 0;
930 struct direct_window *window;
931 struct property *win64;
932 struct dynamic_dma_window_prop *ddwprop;
933 const void *dma_window = NULL;
934 unsigned long liobn, offset, size;
936 mutex_lock(&direct_window_init_mutex);
938 dma_addr = find_existing_ddw(pdn);
943 * the ibm,ddw-applicable property holds the tokens for:
944 * ibm,query-pe-dma-window
945 * ibm,create-pe-dma-window
946 * ibm,remove-pe-dma-window
947 * for the given node in that order.
948 * the property is actually in the parent, not the PE
950 ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
951 if (!ddw_avail || len < 3 * sizeof(u32))
955 * the extensions property is only required to exist in certain
956 * levels of firmware and later
957 * the ibm,ddw-extensions property is a list with the first
958 * element containing the number of extensions and each
959 * subsequent entry is a value corresponding to that extension
961 ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len);
962 if (ddw_extensions) {
964 * each new defined extension length should be added to
965 * the top of the switch so the "earlier" entries also
968 switch (ddw_extensions[0]) {
969 /* ibm,reset-pe-dma-windows */
971 ddw_restore_token = ddw_extensions[1];
977 * Only remove the existing DMA window if we can restore back to
978 * the default state. Removing the existing window maximizes the
979 * resources available to firmware for dynamic window creation.
981 if (ddw_restore_token) {
982 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
983 of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size);
984 __remove_ddw(pdn, ddw_avail, liobn);
988 * Query if there is a second window of size to map the
989 * whole partition. Query returns number of windows, largest
990 * block assigned to PE (partition endpoint), and two bitmasks
991 * of page sizes: supported and supported for migrate-dma.
993 dn = pci_device_to_OF_node(dev);
994 ret = query_ddw(dev, ddw_avail, &query);
996 goto out_restore_window;
998 if (query.windows_available == 0) {
1000 * no additional windows are available for this device.
1001 * We might be able to reallocate the existing window,
1002 * trading in for a larger page size.
1004 dev_dbg(&dev->dev, "no free dynamic windows");
1005 goto out_restore_window;
1007 if (query.page_size & 4) {
1008 page_shift = 24; /* 16MB */
1009 } else if (query.page_size & 2) {
1010 page_shift = 16; /* 64kB */
1011 } else if (query.page_size & 1) {
1012 page_shift = 12; /* 4kB */
1014 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1016 goto out_restore_window;
1018 /* verify the window * number of ptes will map the partition */
1019 /* check largest block * page size > max memory hotplug addr */
1020 max_addr = memory_hotplug_max();
1021 if (query.largest_available_block < (max_addr >> page_shift)) {
1022 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1023 "%llu-sized pages\n", max_addr, query.largest_available_block,
1024 1ULL << page_shift);
1025 goto out_restore_window;
1027 len = order_base_2(max_addr);
1028 win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1031 "couldn't allocate property for 64bit dma window\n");
1032 goto out_restore_window;
1034 win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1035 win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1036 win64->length = sizeof(*ddwprop);
1037 if (!win64->name || !win64->value) {
1039 "couldn't allocate property name and value\n");
1043 ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1047 ddwprop->liobn = cpu_to_be32(create.liobn);
1048 ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
1049 ddwprop->tce_shift = cpu_to_be32(page_shift);
1050 ddwprop->window_shift = cpu_to_be32(len);
1052 dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1053 create.liobn, dn->full_name);
1055 window = kzalloc(sizeof(*window), GFP_KERNEL);
1057 goto out_clear_window;
1059 ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1060 win64->value, tce_setrange_multi_pSeriesLP_walk);
1062 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1063 dn->full_name, ret);
1064 goto out_free_window;
1067 ret = prom_add_property(pdn, win64);
1069 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1070 pdn->full_name, ret);
1071 goto out_free_window;
1074 window->device = pdn;
1075 window->prop = ddwprop;
1076 spin_lock(&direct_window_list_lock);
1077 list_add(&window->list, &direct_window_list);
1078 spin_unlock(&direct_window_list_lock);
1080 dma_addr = of_read_number(&create.addr_hi, 2);
1091 kfree(win64->value);
1095 if (ddw_restore_token)
1096 restore_default_window(dev, ddw_restore_token, liobn);
1099 mutex_unlock(&direct_window_init_mutex);
1103 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1105 struct device_node *pdn, *dn;
1106 struct iommu_table *tbl;
1107 const void *dma_window = NULL;
1110 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1112 /* dev setup for LPAR is a little tricky, since the device tree might
1113 * contain the dma-window properties per-device and not necessarily
1114 * for the bus. So we need to search upwards in the tree until we
1115 * either hit a dma-window property, OR find a parent with a table
1116 * already allocated.
1118 dn = pci_device_to_OF_node(dev);
1119 pr_debug(" node is %s\n", dn->full_name);
1121 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1122 pdn = pdn->parent) {
1123 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1128 if (!pdn || !PCI_DN(pdn)) {
1129 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1130 "no DMA window found for pci dev=%s dn=%s\n",
1131 pci_name(dev), dn? dn->full_name : "<null>");
1134 pr_debug(" parent is %s\n", pdn->full_name);
1137 if (!pci->iommu_table) {
1138 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
1140 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1141 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
1142 pr_debug(" created table: %p\n", pci->iommu_table);
1144 pr_debug(" found DMA window, table: %p\n", pci->iommu_table);
1147 set_iommu_table_base(&dev->dev, pci->iommu_table);
1150 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1152 bool ddw_enabled = false;
1153 struct device_node *pdn, *dn;
1154 struct pci_dev *pdev;
1155 const void *dma_window = NULL;
1161 if (!dev_is_pci(dev))
1164 pdev = to_pci_dev(dev);
1166 /* only attempt to use a new window if 64-bit DMA is requested */
1167 if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1168 dn = pci_device_to_OF_node(pdev);
1169 dev_dbg(dev, "node is %s\n", dn->full_name);
1172 * the device tree might contain the dma-window properties
1173 * per-device and not necessarily for the bus. So we need to
1174 * search upwards in the tree until we either hit a dma-window
1175 * property, OR find a parent with a table already allocated.
1177 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1178 pdn = pdn->parent) {
1179 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1183 if (pdn && PCI_DN(pdn)) {
1184 dma_offset = enable_ddw(pdev, pdn);
1185 if (dma_offset != 0) {
1186 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1187 set_dma_offset(dev, dma_offset);
1188 set_dma_ops(dev, &dma_direct_ops);
1194 /* fall back on iommu ops, restore table pointer with ops */
1195 if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1196 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1197 set_dma_ops(dev, &dma_iommu_ops);
1198 pci_dma_dev_setup_pSeriesLP(pdev);
1202 if (!dma_supported(dev, dma_mask))
1205 *dev->dma_mask = dma_mask;
1209 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1214 if (!disable_ddw && dev_is_pci(dev)) {
1215 struct pci_dev *pdev = to_pci_dev(dev);
1216 struct device_node *dn;
1218 dn = pci_device_to_OF_node(pdev);
1220 /* search upwards for ibm,dma-window */
1221 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
1223 if (of_get_property(dn, "ibm,dma-window", NULL))
1225 /* if there is a ibm,ddw-applicable property require 64 bits */
1226 if (dn && PCI_DN(dn) &&
1227 of_get_property(dn, "ibm,ddw-applicable", NULL))
1228 return DMA_BIT_MASK(64);
1231 return dma_iommu_ops.get_required_mask(dev);
1234 #else /* CONFIG_PCI */
1235 #define pci_dma_bus_setup_pSeries NULL
1236 #define pci_dma_dev_setup_pSeries NULL
1237 #define pci_dma_bus_setup_pSeriesLP NULL
1238 #define pci_dma_dev_setup_pSeriesLP NULL
1239 #define dma_set_mask_pSeriesLP NULL
1240 #define dma_get_required_mask_pSeriesLP NULL
1241 #endif /* !CONFIG_PCI */
1243 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1246 struct direct_window *window;
1247 struct memory_notify *arg = data;
1251 case MEM_GOING_ONLINE:
1252 spin_lock(&direct_window_list_lock);
1253 list_for_each_entry(window, &direct_window_list, list) {
1254 ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1255 arg->nr_pages, window->prop);
1258 spin_unlock(&direct_window_list_lock);
1260 case MEM_CANCEL_ONLINE:
1262 spin_lock(&direct_window_list_lock);
1263 list_for_each_entry(window, &direct_window_list, list) {
1264 ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1265 arg->nr_pages, window->prop);
1268 spin_unlock(&direct_window_list_lock);
1273 if (ret && action != MEM_CANCEL_ONLINE)
1279 static struct notifier_block iommu_mem_nb = {
1280 .notifier_call = iommu_mem_notifier,
1283 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
1285 int err = NOTIFY_OK;
1286 struct device_node *np = node;
1287 struct pci_dn *pci = PCI_DN(np);
1288 struct direct_window *window;
1291 case PSERIES_RECONFIG_REMOVE:
1292 if (pci && pci->iommu_table)
1293 iommu_free_table(pci->iommu_table, np->full_name);
1295 spin_lock(&direct_window_list_lock);
1296 list_for_each_entry(window, &direct_window_list, list) {
1297 if (window->device == np) {
1298 list_del(&window->list);
1303 spin_unlock(&direct_window_list_lock);
1306 * Because the notifier runs after isolation of the
1307 * slot, we are guaranteed any DMA window has already
1308 * been revoked and the TCEs have been marked invalid,
1309 * so we don't need a call to remove_ddw(np). However,
1310 * if an additional notifier action is added before the
1311 * isolate call, we should update this code for
1312 * completeness with such a call.
1322 static struct notifier_block iommu_reconfig_nb = {
1323 .notifier_call = iommu_reconfig_notifier,
1326 /* These are called very early. */
1327 void iommu_init_early_pSeries(void)
1329 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1332 if (firmware_has_feature(FW_FEATURE_LPAR)) {
1333 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
1334 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
1335 ppc_md.tce_free = tce_freemulti_pSeriesLP;
1337 ppc_md.tce_build = tce_build_pSeriesLP;
1338 ppc_md.tce_free = tce_free_pSeriesLP;
1340 ppc_md.tce_get = tce_get_pSeriesLP;
1341 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1342 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1343 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1344 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1346 ppc_md.tce_build = tce_build_pSeries;
1347 ppc_md.tce_free = tce_free_pSeries;
1348 ppc_md.tce_get = tce_get_pseries;
1349 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
1350 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
1354 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
1355 register_memory_notifier(&iommu_mem_nb);
1357 set_pci_dma_ops(&dma_iommu_ops);
1360 static int __init disable_multitce(char *str)
1362 if (strcmp(str, "off") == 0 &&
1363 firmware_has_feature(FW_FEATURE_LPAR) &&
1364 firmware_has_feature(FW_FEATURE_MULTITCE)) {
1365 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1366 ppc_md.tce_build = tce_build_pSeriesLP;
1367 ppc_md.tce_free = tce_free_pSeriesLP;
1368 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1373 __setup("multitce=", disable_multitce);