2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
39 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
57 static int __init fsl_pcie_check_link(struct pci_controller *hose)
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
67 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
69 #define MAX_PHYS_ADDR_BITS 40
70 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
72 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
74 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
78 * Fixup PCI devices that are able to DMA to above the physical
79 * address width of the SoC such that we can address any internal
80 * SoC address from across PCI if needed
82 if ((dev->bus == &pci_bus_type) &&
83 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
84 set_dma_ops(dev, &dma_direct_ops);
85 set_dma_offset(dev, pci64_dma_offset);
88 *dev->dma_mask = dma_mask;
92 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
93 unsigned int index, const struct resource *res,
94 resource_size_t offset)
96 resource_size_t pci_addr = res->start - offset;
97 resource_size_t phys_addr = res->start;
98 resource_size_t size = resource_size(res);
99 u32 flags = 0x80044000; /* enable & mem R/W */
102 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
103 (u64)res->start, (u64)size);
105 if (res->flags & IORESOURCE_PREFETCH)
106 flags |= 0x10000000; /* enable relaxed ordering */
108 for (i = 0; size > 0; i++) {
109 unsigned int bits = min(__ilog2(size),
110 __ffs(pci_addr | phys_addr));
115 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
116 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
117 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
118 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
120 pci_addr += (resource_size_t)1U << bits;
121 phys_addr += (resource_size_t)1U << bits;
122 size -= (resource_size_t)1U << bits;
128 /* atmu setup for fsl pci/pcie controller */
129 static void __init setup_pci_atmu(struct pci_controller *hose,
130 struct resource *rsrc)
132 struct ccsr_pci __iomem *pci;
133 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
134 u64 mem, sz, paddr_hi = 0;
135 u64 paddr_lo = ULLONG_MAX;
136 u32 pcicsrbar = 0, pcicsrbar_sz;
137 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
138 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
139 char *name = hose->dn->full_name;
141 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
142 (u64)rsrc->start, (u64)resource_size(rsrc));
144 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
150 pci = ioremap(rsrc->start, resource_size(rsrc));
152 dev_err(hose->parent, "Unable to map ATMU registers\n");
156 /* Disable all windows (except powar0 since it's ignored) */
157 for(i = 1; i < 5; i++)
158 out_be32(&pci->pow[i].powar, 0);
159 for (i = start_idx; i < end_idx; i++)
160 out_be32(&pci->piw[i].piwar, 0);
162 /* Setup outbound MEM window */
163 for(i = 0, j = 1; i < 3; i++) {
164 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
167 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
168 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
170 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
171 hose->pci_mem_offset);
173 if (n < 0 || j >= 5) {
174 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
175 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
180 /* Setup outbound IO window */
181 if (hose->io_resource.flags & IORESOURCE_IO) {
183 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
185 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
186 "phy base 0x%016llx.\n",
187 (u64)hose->io_resource.start,
188 (u64)resource_size(&hose->io_resource),
189 (u64)hose->io_base_phys);
190 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
191 out_be32(&pci->pow[j].potear, 0);
192 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
194 out_be32(&pci->pow[j].powar, 0x80088000
195 | (__ilog2(hose->io_resource.end
196 - hose->io_resource.start + 1) - 1));
200 /* convert to pci address space */
201 paddr_hi -= hose->pci_mem_offset;
202 paddr_lo -= hose->pci_mem_offset;
204 if (paddr_hi == paddr_lo) {
205 pr_err("%s: No outbound window space\n", name);
210 pr_err("%s: No space for inbound window\n", name);
214 /* setup PCSRBAR/PEXCSRBAR */
215 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
216 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
217 pcicsrbar_sz = ~pcicsrbar_sz + 1;
219 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
220 (paddr_lo > 0x100000000ull))
221 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
223 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
224 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
226 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
228 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
230 /* Setup inbound mem window */
231 mem = memblock_end_of_DRAM();
232 sz = min(mem, paddr_lo);
233 mem_log = __ilog2_u64(sz);
235 /* PCIe can overmap inbound & outbound since RX & TX are separated */
236 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
237 /* Size window to exact size if power-of-two or one size up */
238 if ((1ull << mem_log) != mem) {
239 if ((1ull << mem_log) > mem)
240 pr_info("%s: Setting PCI inbound window "
241 "greater than memory size\n", name);
245 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
247 /* Setup inbound memory window */
248 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
249 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
250 out_be32(&pci->piw[win_idx].piwar, piwar);
253 hose->dma_window_base_cur = 0x00000000;
254 hose->dma_window_size = (resource_size_t)sz;
257 * if we have >4G of memory setup second PCI inbound window to
258 * let devices that are 64-bit address capable to work w/o
259 * SWIOTLB and access the full range of memory
262 mem_log = __ilog2_u64(mem);
264 /* Size window up if we dont fit in exact power-of-2 */
265 if ((1ull << mem_log) != mem)
268 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
270 /* Setup inbound memory window */
271 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
272 out_be32(&pci->piw[win_idx].piwbear,
273 pci64_dma_offset >> 44);
274 out_be32(&pci->piw[win_idx].piwbar,
275 pci64_dma_offset >> 12);
276 out_be32(&pci->piw[win_idx].piwar, piwar);
279 * install our own dma_set_mask handler to fixup dma_ops
282 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
284 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
289 /* Setup inbound memory window */
290 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
291 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
292 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
295 paddr += 1ull << mem_log;
296 sz -= 1ull << mem_log;
299 mem_log = __ilog2_u64(sz);
300 piwar |= (mem_log - 1);
302 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
303 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
304 out_be32(&pci->piw[win_idx].piwar, piwar);
307 paddr += 1ull << mem_log;
310 hose->dma_window_base_cur = 0x00000000;
311 hose->dma_window_size = (resource_size_t)paddr;
314 if (hose->dma_window_size < mem) {
315 #ifndef CONFIG_SWIOTLB
316 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
317 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
320 /* adjusting outbound windows could reclaim space in mem map */
321 if (paddr_hi < 0xffffffffull)
322 pr_warning("%s: WARNING: Outbound window cfg leaves "
323 "gaps in memory map. Adjusting the memory map "
324 "could reduce unnecessary bounce buffering.\n",
327 pr_info("%s: DMA window size is 0x%llx\n", name,
328 (u64)hose->dma_window_size);
334 static void __init setup_pci_cmd(struct pci_controller *hose)
339 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
340 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
342 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
344 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
346 int pci_x_cmd = cap_x + PCI_X_CMD;
347 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
348 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
349 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
351 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
355 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
357 struct pci_controller *hose = pci_bus_to_host(bus);
360 if ((bus->parent == hose->bus) &&
361 ((fsl_pcie_bus_fixup &&
362 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
363 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
365 for (i = 0; i < 4; ++i) {
366 struct resource *res = bus->resource[i];
367 struct resource *par = bus->parent->resource[i];
374 res->start = par->start;
376 res->flags = par->flags;
382 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
385 struct pci_controller *hose;
386 struct resource rsrc;
387 const int *bus_range;
390 if (!of_device_is_available(dev)) {
391 pr_warning("%s: disabled\n", dev->full_name);
395 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
397 /* Fetch host bridge registers address */
398 if (of_address_to_resource(dev, 0, &rsrc)) {
399 printk(KERN_WARNING "Can't get pci register base!");
403 /* Get bus range if any */
404 bus_range = of_get_property(dev, "bus-range", &len);
405 if (bus_range == NULL || len < 2 * sizeof(int))
406 printk(KERN_WARNING "Can't get bus-range for %s, assume"
407 " bus 0\n", dev->full_name);
409 pci_add_flags(PCI_REASSIGN_ALL_BUS);
410 hose = pcibios_alloc_controller(dev);
414 hose->first_busno = bus_range ? bus_range[0] : 0x0;
415 hose->last_busno = bus_range ? bus_range[1] : 0xff;
417 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
418 PPC_INDIRECT_TYPE_BIG_ENDIAN);
420 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
421 if ((progif & 1) == 1) {
422 /* unmap cfg_data & cfg_addr separately if not on same page */
423 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
424 ((unsigned long)hose->cfg_addr & PAGE_MASK))
425 iounmap(hose->cfg_data);
426 iounmap(hose->cfg_addr);
427 pcibios_free_controller(hose);
433 /* check PCI express link status */
434 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
435 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
436 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
437 if (fsl_pcie_check_link(hose))
438 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
441 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
442 "Firmware bus number: %d->%d\n",
443 (unsigned long long)rsrc.start, hose->first_busno,
446 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
447 hose, hose->cfg_addr, hose->cfg_data);
449 /* Interpret the "ranges" property */
450 /* This also maps the I/O region and sets isa_io/mem_base */
451 pci_process_bridge_OF_ranges(hose, dev, is_primary);
453 /* Setup PEX window registers */
454 setup_pci_atmu(hose, &rsrc);
458 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
462 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
463 struct mpc83xx_pcie_priv {
464 void __iomem *cfg_type0;
465 void __iomem *cfg_type1;
469 struct pex_inbound_window {
477 * With the convention of u-boot, the PCIE outbound window 0 serves
478 * as configuration transactions outbound.
480 #define PEX_OUTWIN0_BAR 0xCA4
481 #define PEX_OUTWIN0_TAL 0xCA8
482 #define PEX_OUTWIN0_TAH 0xCAC
483 #define PEX_RC_INWIN_BASE 0xE60
484 #define PEX_RCIWARn_EN 0x1
486 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
488 struct pci_controller *hose = pci_bus_to_host(bus);
490 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
491 return PCIBIOS_DEVICE_NOT_FOUND;
493 * Workaround for the HW bug: for Type 0 configure transactions the
494 * PCI-E controller does not check the device number bits and just
495 * assumes that the device number bits are 0.
497 if (bus->number == hose->first_busno ||
498 bus->primary == hose->first_busno) {
500 return PCIBIOS_DEVICE_NOT_FOUND;
503 if (ppc_md.pci_exclude_device) {
504 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
505 return PCIBIOS_DEVICE_NOT_FOUND;
508 return PCIBIOS_SUCCESSFUL;
511 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
512 unsigned int devfn, int offset)
514 struct pci_controller *hose = pci_bus_to_host(bus);
515 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
516 u32 dev_base = bus->number << 24 | devfn << 16;
519 ret = mpc83xx_pcie_exclude_device(bus, devfn);
526 if (bus->number == hose->first_busno)
527 return pcie->cfg_type0 + offset;
529 if (pcie->dev_base == dev_base)
532 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
534 pcie->dev_base = dev_base;
536 return pcie->cfg_type1 + offset;
539 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
540 int offset, int len, u32 *val)
542 void __iomem *cfg_addr;
544 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
546 return PCIBIOS_DEVICE_NOT_FOUND;
550 *val = in_8(cfg_addr);
553 *val = in_le16(cfg_addr);
556 *val = in_le32(cfg_addr);
560 return PCIBIOS_SUCCESSFUL;
563 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
564 int offset, int len, u32 val)
566 struct pci_controller *hose = pci_bus_to_host(bus);
567 void __iomem *cfg_addr;
569 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
571 return PCIBIOS_DEVICE_NOT_FOUND;
573 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
574 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
579 out_8(cfg_addr, val);
582 out_le16(cfg_addr, val);
585 out_le32(cfg_addr, val);
589 return PCIBIOS_SUCCESSFUL;
592 static struct pci_ops mpc83xx_pcie_ops = {
593 .read = mpc83xx_pcie_read_config,
594 .write = mpc83xx_pcie_write_config,
597 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
598 struct resource *reg)
600 struct mpc83xx_pcie_priv *pcie;
604 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
608 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
609 if (!pcie->cfg_type0)
612 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
614 /* PCI-E isn't configured. */
619 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
620 if (!pcie->cfg_type1)
623 WARN_ON(hose->dn->data);
624 hose->dn->data = pcie;
625 hose->ops = &mpc83xx_pcie_ops;
627 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
628 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
630 if (fsl_pcie_check_link(hose))
631 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
635 iounmap(pcie->cfg_type0);
642 int __init mpc83xx_add_bridge(struct device_node *dev)
646 struct pci_controller *hose;
647 struct resource rsrc_reg;
648 struct resource rsrc_cfg;
649 const int *bus_range;
654 if (!of_device_is_available(dev)) {
655 pr_warning("%s: disabled by the firmware.\n",
659 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
661 /* Fetch host bridge registers address */
662 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
663 printk(KERN_WARNING "Can't get pci register base!\n");
667 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
669 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
671 "No pci config register base in dev tree, "
674 * MPC83xx supports up to two host controllers
675 * one at 0x8500 has config space registers at 0x8300
676 * one at 0x8600 has config space registers at 0x8380
678 if ((rsrc_reg.start & 0xfffff) == 0x8500)
679 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
680 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
681 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
684 * Controller at offset 0x8500 is primary
686 if ((rsrc_reg.start & 0xfffff) == 0x8500)
691 /* Get bus range if any */
692 bus_range = of_get_property(dev, "bus-range", &len);
693 if (bus_range == NULL || len < 2 * sizeof(int)) {
694 printk(KERN_WARNING "Can't get bus-range for %s, assume"
695 " bus 0\n", dev->full_name);
698 pci_add_flags(PCI_REASSIGN_ALL_BUS);
699 hose = pcibios_alloc_controller(dev);
703 hose->first_busno = bus_range ? bus_range[0] : 0;
704 hose->last_busno = bus_range ? bus_range[1] : 0xff;
706 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
707 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
711 setup_indirect_pci(hose, rsrc_cfg.start,
712 rsrc_cfg.start + 4, 0);
715 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
716 "Firmware bus number: %d->%d\n",
717 (unsigned long long)rsrc_reg.start, hose->first_busno,
720 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
721 hose, hose->cfg_addr, hose->cfg_data);
723 /* Interpret the "ranges" property */
724 /* This also maps the I/O region and sets isa_io/mem_base */
725 pci_process_bridge_OF_ranges(hose, dev, primary);
729 pcibios_free_controller(hose);
732 #endif /* CONFIG_PPC_83xx */
734 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
736 #ifdef CONFIG_PPC_83xx
737 if (is_mpc83xx_pci) {
738 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
739 struct pex_inbound_window *in;
742 /* Walk the Root Complex Inbound windows to match IMMR base */
743 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
744 for (i = 0; i < 4; i++) {
745 /* not enabled, skip */
746 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
749 if (get_immrbase() == in_le32(&in[i].tar))
750 return (u64)in_le32(&in[i].barh) << 32 |
751 in_le32(&in[i].barl);
754 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
758 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
759 if (!is_mpc83xx_pci) {
762 pci_bus_read_config_dword(hose->bus,
763 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);