2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2010
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/ptrace.h>
17 #include <asm/thread_info.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/unistd.h>
23 * Stack layout for the system_call stack entry.
24 * The first few entries are identical to the user_regs_struct.
26 SP_PTREGS = STACK_FRAME_OVERHEAD
27 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
28 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
29 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
30 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
31 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
32 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
33 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
34 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
35 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
36 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
37 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
38 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
39 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
40 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
41 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
42 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
43 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
44 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
45 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
46 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
47 SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR
48 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
50 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
53 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
54 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
55 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
57 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
58 _TIF_SECCOMP>>8 | _TIF_SYSCALL_TRACEPOINT>>8)
60 #define BASED(name) name-system_call(%r13)
62 .macro HANDLE_SIE_INTERCEPT
63 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
72 #ifdef CONFIG_TRACE_IRQFLAGS
75 brasl %r14,trace_hardirqs_on_caller
80 brasl %r14,trace_hardirqs_off_caller
83 .macro TRACE_IRQS_CHECK_ON
84 tm SP_PSW(%r15),0x03 # irqs enabled?
90 .macro TRACE_IRQS_CHECK_OFF
91 tm SP_PSW(%r15),0x03 # irqs enabled?
98 #define TRACE_IRQS_OFF
99 #define TRACE_IRQS_CHECK_ON
100 #define TRACE_IRQS_CHECK_OFF
103 #ifdef CONFIG_LOCKDEP
104 .macro LOCKDEP_SYS_EXIT
105 tm SP_PSW+1(%r15),0x01 # returning to user ?
107 brasl %r14,lockdep_sys_exit
111 #define LOCKDEP_SYS_EXIT
114 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
122 * Register usage in interrupt handlers:
123 * R9 - pointer to current task structure
124 * R13 - pointer to literal pool
125 * R14 - return register for function calls
126 * R15 - kernel stack pointer
129 .macro SAVE_ALL_BASE savearea
130 stmg %r12,%r15,\savearea
131 larl %r13,system_call
134 .macro SAVE_ALL_SVC psworg,savearea
136 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
139 .macro SAVE_ALL_SYNC psworg,savearea
141 tm \psworg+1,0x01 # test problem state bit
142 jz 2f # skip stack setup save
143 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
144 #ifdef CONFIG_CHECK_STACK
146 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
153 .macro SAVE_ALL_ASYNC psworg,savearea
155 tm \psworg+1,0x01 # test problem state bit
156 jnz 1f # from user -> load kernel stack
157 clc \psworg+8(8),BASED(.Lcritical_end)
159 clc \psworg+8(8),BASED(.Lcritical_start)
161 brasl %r14,cleanup_critical
162 tm 1(%r12),0x01 # retest problem state after cleanup
164 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
166 srag %r14,%r14,STACK_SHIFT
168 1: lg %r15,__LC_ASYNC_STACK # load async stack
169 #ifdef CONFIG_CHECK_STACK
171 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
178 .macro CREATE_STACK_FRAME psworg,savearea
179 aghi %r15,-SP_SIZE # make room for registers & psw
180 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
181 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
182 icm %r12,3,__LC_SVC_ILC
183 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
184 st %r12,SP_SVCNR(%r15)
185 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
187 stg %r12,__SF_BACKCHAIN(%r15)
190 .macro RESTORE_ALL psworg,sync
191 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
193 ni \psworg+1,0xfd # clear wait state bit
195 lg %r14,__LC_VDSO_PER_CPU
196 lmg %r0,%r13,SP_R0(%r15) # load gprs 0-13 of user
198 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
199 lmg %r14,%r15,SP_R14(%r15) # load grps 14-15 of user
200 lpswe \psworg # back to caller
204 * Scheduler resume function, called by switch_to
205 * gpr2 = (task_struct *) prev
206 * gpr3 = (task_struct *) next
212 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
213 jz __switch_to_noper # if not we're fine
214 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
215 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
216 je __switch_to_noper # we got away without bashing TLB's
217 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
219 lg %r4,__THREAD_info(%r2) # get thread_info of prev
220 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
221 jz __switch_to_no_mcck
222 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
223 lg %r4,__THREAD_info(%r3) # get thread_info of next
224 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
226 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
227 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
228 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
229 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
230 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
231 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
232 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
233 stg %r3,__LC_THREAD_INFO
235 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
240 * SVC interrupt handler routine. System calls are synchronous events and
241 * are executed with interrupts enabled.
246 stpt __LC_SYNC_ENTER_TIMER
248 SAVE_ALL_BASE __LC_SAVE_AREA
249 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
250 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
251 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
253 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
255 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
257 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
259 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
260 ltgr %r7,%r7 # test for svc 0
262 # svc 0: system call number in %r1
263 cl %r1,BASED(.Lnr_syscalls)
265 lgfr %r7,%r1 # clear high word in r1
267 mvc SP_ARGS(8,%r15),SP_R7(%r15)
269 sth %r7,SP_SVCNR(%r15)
270 sllg %r7,%r7,2 # svc number * 4
271 larl %r10,sys_call_table
273 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
275 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
278 tm __TI_flags+6(%r9),_TIF_SYSCALL
279 lgf %r8,0(%r7,%r10) # load address of system call routine
281 basr %r14,%r8 # call sys_xxxx
282 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
287 tm __TI_flags+7(%r9),_TIF_WORK_SVC
288 jnz sysc_work # there is work to do (signals etc.)
290 RESTORE_ALL __LC_RETURN_PSW,1
294 # There is work to do, but first we need to check if we return to userspace.
297 tm SP_PSW+1(%r15),0x01 # returning to user ?
301 # One of the work bits is on. Find out which one.
304 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
306 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
308 tm __TI_flags+7(%r9),_TIF_SIGPENDING
310 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
311 jo sysc_notify_resume
312 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
314 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
316 j sysc_return # beware of critical section cleanup
319 # _TIF_NEED_RESCHED is set, call schedule
322 larl %r14,sysc_return
323 jg schedule # return point is sysc_return
326 # _TIF_MCCK_PENDING is set, call handler
329 larl %r14,sysc_return
330 jg s390_handle_mcck # TIF bit will be cleared by handler
333 # _TIF_SIGPENDING is set, call do_signal
336 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
337 la %r2,SP_PTREGS(%r15) # load pt_regs
338 brasl %r14,do_signal # call do_signal
339 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
341 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
346 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
349 la %r2,SP_PTREGS(%r15) # load pt_regs
350 larl %r14,sysc_return
351 jg do_notify_resume # call do_notify_resume
354 # _TIF_RESTART_SVC is set, set up registers and restart svc
357 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
358 lg %r7,SP_R2(%r15) # load new svc number
359 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
360 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
361 j sysc_do_restart # restart svc
364 # _TIF_SINGLE_STEP is set, call do_single_step
367 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
368 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
369 la %r2,SP_PTREGS(%r15) # address of register-save area
370 larl %r14,sysc_return # load adr. of system return
371 jg do_single_step # branch to do_sigtrap
374 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
375 # and after the system call
378 la %r2,SP_PTREGS(%r15) # load pt_regs
382 brasl %r14,do_syscall_trace_enter
386 sllg %r7,%r2,2 # svc number *4
389 lmg %r3,%r6,SP_R3(%r15)
390 lg %r2,SP_ORIG_R2(%r15)
391 basr %r14,%r8 # call sys_xxx
392 stg %r2,SP_R2(%r15) # store return value
394 tm __TI_flags+6(%r9),_TIF_SYSCALL
396 la %r2,SP_PTREGS(%r15) # load pt_regs
397 larl %r14,sysc_return # return point is sysc_return
398 jg do_syscall_trace_exit
401 # a new process exits the kernel with ret_from_fork
405 lg %r13,__LC_SVC_NEW_PSW+8
406 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
407 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
409 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
410 0: brasl %r14,schedule_tail
412 stosm 24(%r15),0x03 # reenable interrupts
416 # kernel_execve function needs to deal with pt_regs that is not
421 stmg %r12,%r15,96(%r15)
424 stg %r14,__SF_BACKCHAIN(%r15)
425 la %r12,SP_PTREGS(%r15)
426 xc 0(__PT_SIZE,%r12),0(%r12)
432 lmg %r12,%r15,96(%r15)
435 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
437 lg %r15,__LC_KERNEL_STACK # load ksp
438 aghi %r15,-SP_SIZE # make room for registers & psw
439 lg %r13,__LC_SVC_NEW_PSW+8
440 lg %r9,__LC_THREAD_INFO
441 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
442 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
444 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
445 brasl %r14,execve_tail
449 * Program check handler routine
452 .globl pgm_check_handler
455 * First we need to check for a special case:
456 * Single stepping an instruction that disables the PER event mask will
457 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
458 * For a single stepped SVC the program check handler gets control after
459 * the SVC new PSW has been loaded. But we want to execute the SVC first and
460 * then handle the PER event. Therefore we update the SVC old PSW to point
461 * to the pgm_check_handler and branch to the SVC handler after we checked
462 * if we have to load the kernel stack register.
463 * For every other possible cause for PER event without the PER mask set
464 * we just ignore the PER event (FIXME: is there anything we have to do
467 stpt __LC_SYNC_ENTER_TIMER
468 SAVE_ALL_BASE __LC_SAVE_AREA
469 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
470 jnz pgm_per # got per exception -> special case
471 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
472 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
473 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
475 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
476 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
477 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
481 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
482 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
483 lgf %r3,__LC_PGM_ILC # load program interruption code
488 larl %r1,pgm_check_table
489 lg %r1,0(%r8,%r1) # load address of handler routine
490 la %r2,SP_PTREGS(%r15) # address of register-save area
491 basr %r14,%r1 # branch to interrupt-handler
497 # handle per exception
500 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
501 jnz pgm_per_std # ok, normal per event from user space
502 # ok its one of the special cases, now we need to find out which one
503 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
505 # no interesting special case, ignore PER event
506 lmg %r12,%r15,__LC_SAVE_AREA
507 lpswe __LC_PGM_OLD_PSW
510 # Normal per exception
513 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
514 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
515 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
517 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
518 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
519 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
523 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
524 lg %r1,__TI_task(%r9)
525 tm SP_PSW+1(%r15),0x01 # kernel per event ?
527 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
528 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
529 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
530 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
531 lgf %r3,__LC_PGM_ILC # load program interruption code
533 ngr %r8,%r3 # clear per-event-bit and ilc
538 # it was a single stepped SVC that is causing all the trouble
541 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
542 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
543 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
544 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
545 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
546 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
547 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
549 lg %r8,__TI_task(%r9)
550 mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID
551 mvc __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS
552 mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
553 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
555 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
556 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
560 # per was called from kernel, must be kprobes
563 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
564 la %r2,SP_PTREGS(%r15) # address of register-save area
565 brasl %r14,do_single_step
569 * IO interrupt handler routine
571 .globl io_int_handler
574 stpt __LC_ASYNC_ENTER_TIMER
575 SAVE_ALL_BASE __LC_SAVE_AREA+32
576 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
577 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
578 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
580 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
581 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
582 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
584 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
587 la %r2,SP_PTREGS(%r15) # address of register-save area
588 brasl %r14,do_IRQ # call standard irq handler
593 tm __TI_flags+7(%r9),_TIF_WORK_INT
594 jnz io_work # there is work to do (signals etc.)
596 RESTORE_ALL __LC_RETURN_PSW,0
600 # There is work todo, find out in which context we have been interrupted:
601 # 1) if we return to user space we can do all _TIF_WORK_INT work
602 # 2) if we return to kernel code and kvm is enabled check if we need to
603 # modify the psw to leave SIE
604 # 3) if we return to kernel code and preemptive scheduling is enabled check
605 # the preemption counter and if it is zero call preempt_schedule_irq
606 # Before any work can be done, a switch to the kernel stack is required.
609 tm SP_PSW+1(%r15),0x01 # returning to user ?
610 jo io_work_user # yes -> do resched & signal
611 #ifdef CONFIG_PREEMPT
612 # check for preemptive scheduling
613 icm %r0,15,__TI_precount(%r9)
614 jnz io_restore # preemption is disabled
615 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
617 # switch to kernel stack
620 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
621 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
623 # TRACE_IRQS_ON already done at io_return, call
624 # TRACE_IRQS_OFF to keep things symmetrical
626 brasl %r14,preempt_schedule_irq
633 # Need to do work before returning to userspace, switch to kernel stack
636 lg %r1,__LC_KERNEL_STACK
638 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
639 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
643 # One of the work bits is on. Find out which one.
644 # Checked are: _TIF_SIGPENDING, _TIF_NOTIFY_RESUME, _TIF_NEED_RESCHED
645 # and _TIF_MCCK_PENDING
648 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
650 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
652 tm __TI_flags+7(%r9),_TIF_SIGPENDING
654 tm __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
656 j io_return # beware of critical section cleanup
659 # _TIF_MCCK_PENDING is set, call handler
662 # TRACE_IRQS_ON already done at io_return
663 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
668 # _TIF_NEED_RESCHED is set, call schedule
671 # TRACE_IRQS_ON already done at io_return
672 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
673 brasl %r14,schedule # call scheduler
674 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
679 # _TIF_SIGPENDING or is set, call do_signal
682 # TRACE_IRQS_ON already done at io_return
683 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
684 la %r2,SP_PTREGS(%r15) # load pt_regs
685 brasl %r14,do_signal # call do_signal
686 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
691 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
694 # TRACE_IRQS_ON already done at io_return
695 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
696 la %r2,SP_PTREGS(%r15) # load pt_regs
697 brasl %r14,do_notify_resume # call do_notify_resume
698 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
703 * External interrupt handler routine
705 .globl ext_int_handler
708 stpt __LC_ASYNC_ENTER_TIMER
709 SAVE_ALL_BASE __LC_SAVE_AREA+32
710 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
711 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
712 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
714 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
715 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
716 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
718 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
721 la %r2,SP_PTREGS(%r15) # address of register-save area
722 llgh %r3,__LC_EXT_INT_CODE # get interruption code
729 * Machine check handler routines
731 .globl mcck_int_handler
734 la %r1,4095 # revalidate r1
735 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
736 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
737 SAVE_ALL_BASE __LC_SAVE_AREA+64
738 la %r12,__LC_MCK_OLD_PSW
739 tm __LC_MCCK_CODE,0x80 # system damage?
740 jo mcck_int_main # yes -> rest of mcck code invalid
742 mvc __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
743 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
745 la %r14,__LC_SYNC_ENTER_TIMER
746 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
748 la %r14,__LC_ASYNC_ENTER_TIMER
749 0: clc 0(8,%r14),__LC_EXIT_TIMER
751 la %r14,__LC_EXIT_TIMER
752 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
754 la %r14,__LC_LAST_UPDATE_TIMER
756 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
757 1: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
758 jno mcck_int_main # no -> skip cleanup critical
759 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
760 jnz mcck_int_main # from user -> load kernel stack
761 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
763 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
765 brasl %r14,cleanup_critical
767 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
769 srag %r14,%r14,PAGE_SHIFT
771 lg %r15,__LC_PANIC_STACK # load panic stack
772 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
773 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
774 jno mcck_no_vtime # no -> no timer update
775 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
777 UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER
778 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
779 mvc __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
781 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
782 la %r2,SP_PTREGS(%r15) # load pt_regs
783 brasl %r14,s390_do_machine_check
784 tm SP_PSW+1(%r15),0x01 # returning to user ?
786 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
788 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
789 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
791 stosm __SF_EMPTY(%r15),0x04 # turn dat on
792 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
796 brasl %r14,s390_handle_mcck
799 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
800 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
801 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
802 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
805 0: lpswe __LC_RETURN_MCCK_PSW # back to caller
808 * Restart interruption handler, kick starter for additional CPUs
812 .globl restart_int_handler
816 spt restart_vtime-restart_base(%r1)
817 stck __LC_LAST_UPDATE_CLOCK
818 mvc __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
819 mvc __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
820 lg %r15,__LC_SAVE_AREA+120 # load ksp
821 lghi %r10,__LC_CREGS_SAVE_AREA
822 lctlg %c0,%c15,0(%r10) # get new ctl regs
823 lghi %r10,__LC_AREGS_SAVE_AREA
825 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
826 lg %r1,__LC_THREAD_INFO
827 mvc __LC_USER_TIMER(8),__TI_user_timer(%r1)
828 mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
829 xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
830 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
834 .long 0x7fffffff,0xffffffff
838 * If we do not run with SMP enabled, let the new CPU crash ...
840 .globl restart_int_handler
844 lpswe restart_crash-restart_base(%r1)
847 .long 0x000a0000,0x00000000,0x00000000,0x00000000
851 #ifdef CONFIG_CHECK_STACK
853 * The synchronous or the asynchronous stack overflowed. We are dead.
854 * No need to properly save the registers, we are going to panic anyway.
855 * Setup a pt_regs so that show_trace can provide a good call trace.
858 lg %r15,__LC_PANIC_STACK # change to panic stack
860 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
861 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
862 la %r1,__LC_SAVE_AREA
863 chi %r12,__LC_SVC_OLD_PSW
865 chi %r12,__LC_PGM_OLD_PSW
867 la %r1,__LC_SAVE_AREA+32
868 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
869 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
870 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
871 la %r2,SP_PTREGS(%r15) # load pt_regs
872 jg kernel_stack_overflow
875 cleanup_table_system_call:
876 .quad system_call, sysc_do_svc
877 cleanup_table_sysc_tif:
878 .quad sysc_tif, sysc_restore
879 cleanup_table_sysc_restore:
880 .quad sysc_restore, sysc_done
881 cleanup_table_io_tif:
882 .quad io_tif, io_restore
883 cleanup_table_io_restore:
884 .quad io_restore, io_done
887 clc 8(8,%r12),BASED(cleanup_table_system_call)
889 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
890 jl cleanup_system_call
892 clc 8(8,%r12),BASED(cleanup_table_sysc_tif)
894 clc 8(8,%r12),BASED(cleanup_table_sysc_tif+8)
897 clc 8(8,%r12),BASED(cleanup_table_sysc_restore)
899 clc 8(8,%r12),BASED(cleanup_table_sysc_restore+8)
900 jl cleanup_sysc_restore
902 clc 8(8,%r12),BASED(cleanup_table_io_tif)
904 clc 8(8,%r12),BASED(cleanup_table_io_tif+8)
907 clc 8(8,%r12),BASED(cleanup_table_io_restore)
909 clc 8(8,%r12),BASED(cleanup_table_io_restore+8)
910 jl cleanup_io_restore
915 mvc __LC_RETURN_PSW(16),0(%r12)
916 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
918 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
919 cghi %r12,__LC_MCK_OLD_PSW
921 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
922 0: cghi %r12,__LC_MCK_OLD_PSW
923 la %r12,__LC_SAVE_AREA+64
925 la %r12,__LC_SAVE_AREA+32
926 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
928 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
930 mvc __LC_SAVE_AREA(32),0(%r12)
932 stg %r12,__LC_SAVE_AREA+96 # argh
933 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
934 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
935 lg %r12,__LC_SAVE_AREA+96 # argh
937 llgh %r7,__LC_SVC_INT_CODE
939 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
941 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
943 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
945 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
947 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
948 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
949 la %r12,__LC_RETURN_PSW
951 cleanup_system_call_insn:
959 mvc __LC_RETURN_PSW(8),0(%r12)
960 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_tif)
961 la %r12,__LC_RETURN_PSW
964 cleanup_sysc_restore:
965 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn)
967 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn+8)
969 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
970 cghi %r12,__LC_MCK_OLD_PSW
972 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
973 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
974 cghi %r12,__LC_MCK_OLD_PSW
975 la %r12,__LC_SAVE_AREA+64
977 la %r12,__LC_SAVE_AREA+32
978 1: mvc 0(32,%r12),SP_R12(%r15)
979 lmg %r0,%r11,SP_R0(%r15)
981 2: la %r12,__LC_RETURN_PSW
983 cleanup_sysc_restore_insn:
988 mvc __LC_RETURN_PSW(8),0(%r12)
989 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_tif)
990 la %r12,__LC_RETURN_PSW
994 clc 8(8,%r12),BASED(cleanup_io_restore_insn)
996 clc 8(8,%r12),BASED(cleanup_io_restore_insn+8)
998 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
999 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1000 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
1001 lmg %r0,%r11,SP_R0(%r15)
1002 lg %r15,SP_R15(%r15)
1003 1: la %r12,__LC_RETURN_PSW
1005 cleanup_io_restore_insn:
1014 .Lnr_syscalls: .long NR_syscalls
1015 .L0x0130: .short 0x130
1016 .L0x0140: .short 0x140
1017 .L0x0150: .short 0x150
1018 .L0x0160: .short 0x160
1019 .L0x0170: .short 0x170
1021 .quad __critical_start
1023 .quad __critical_end
1025 .section .rodata, "a"
1026 #define SYSCALL(esa,esame,emu) .long esame
1027 .globl sys_call_table
1029 #include "syscalls.S"
1032 #ifdef CONFIG_COMPAT
1034 #define SYSCALL(esa,esame,emu) .long emu
1036 #include "syscalls.S"