1 menu "Processor selection"
7 select SH_WRITETHROUGH if !CPU_SH2A
23 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
33 config CPU_SUBTYPE_ST40
36 select CPU_HAS_INTC2_IRQ
45 comment "SH-2 Processor Support"
47 config CPU_SUBTYPE_SH7604
48 bool "Support SH7604 processor"
51 config CPU_SUBTYPE_SH7619
52 bool "Support SH7619 processor"
55 comment "SH-2A Processor Support"
57 config CPU_SUBTYPE_SH7206
58 bool "Support SH7206 processor"
61 comment "SH-3 Processor Support"
63 config CPU_SUBTYPE_SH7300
64 bool "Support SH7300 processor"
67 config CPU_SUBTYPE_SH7705
68 bool "Support SH7705 processor"
70 select CPU_HAS_PINT_IRQ
72 config CPU_SUBTYPE_SH7706
73 bool "Support SH7706 processor"
75 select CPU_HAS_IPR_IRQ
77 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
79 config CPU_SUBTYPE_SH7707
80 bool "Support SH7707 processor"
82 select CPU_HAS_PINT_IRQ
84 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
86 config CPU_SUBTYPE_SH7708
87 bool "Support SH7708 processor"
90 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
91 if you have a 100 Mhz SH-3 HD6417708R CPU.
93 config CPU_SUBTYPE_SH7709
94 bool "Support SH7709 processor"
96 select CPU_HAS_IPR_IRQ
97 select CPU_HAS_PINT_IRQ
99 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
101 config CPU_SUBTYPE_SH7710
102 bool "Support SH7710 processor"
104 select CPU_HAS_IPR_IRQ
106 Select SH7710 if you have a SH3-DSP SH7710 CPU.
108 config CPU_SUBTYPE_SH7712
109 bool "Support SH7712 processor"
111 select CPU_HAS_IPR_IRQ
113 Select SH7712 if you have a SH3-DSP SH7712 CPU.
115 comment "SH-4 Processor Support"
117 config CPU_SUBTYPE_SH7750
118 bool "Support SH7750 processor"
120 select CPU_HAS_IPR_IRQ
122 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
124 config CPU_SUBTYPE_SH7091
125 bool "Support SH7091 processor"
127 select CPU_SUBTYPE_SH7750
129 Select SH7091 if you have an SH-4 based Sega device (such as
130 the Dreamcast, Naomi, and Naomi 2).
132 config CPU_SUBTYPE_SH7750R
133 bool "Support SH7750R processor"
135 select CPU_SUBTYPE_SH7750
136 select CPU_HAS_IPR_IRQ
138 config CPU_SUBTYPE_SH7750S
139 bool "Support SH7750S processor"
141 select CPU_SUBTYPE_SH7750
142 select CPU_HAS_IPR_IRQ
144 config CPU_SUBTYPE_SH7751
145 bool "Support SH7751 processor"
147 select CPU_HAS_IPR_IRQ
149 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
150 or if you have a HD6417751R CPU.
152 config CPU_SUBTYPE_SH7751R
153 bool "Support SH7751R processor"
155 select CPU_SUBTYPE_SH7751
156 select CPU_HAS_IPR_IRQ
158 config CPU_SUBTYPE_SH7760
159 bool "Support SH7760 processor"
161 select CPU_HAS_INTC2_IRQ
162 select CPU_HAS_IPR_IRQ
164 config CPU_SUBTYPE_SH4_202
165 bool "Support SH4-202 processor"
168 comment "ST40 Processor Support"
170 config CPU_SUBTYPE_ST40STB1
171 bool "Support ST40STB1/ST40RA processors"
172 select CPU_SUBTYPE_ST40
174 Select ST40STB1 if you have a ST40RA CPU.
175 This was previously called the ST40STB1, hence the option name.
177 config CPU_SUBTYPE_ST40GX1
178 bool "Support ST40GX1 processor"
179 select CPU_SUBTYPE_ST40
181 Select ST40GX1 if you have a ST40GX1 CPU.
183 comment "SH-4A Processor Support"
185 config CPU_SUBTYPE_SH7770
186 bool "Support SH7770 processor"
189 config CPU_SUBTYPE_SH7780
190 bool "Support SH7780 processor"
192 select CPU_HAS_INTC2_IRQ
194 config CPU_SUBTYPE_SH7785
195 bool "Support SH7785 processor"
198 select CPU_HAS_INTC2_IRQ
200 comment "SH4AL-DSP Processor Support"
202 config CPU_SUBTYPE_SH73180
203 bool "Support SH73180 processor"
206 config CPU_SUBTYPE_SH7343
207 bool "Support SH7343 processor"
210 config CPU_SUBTYPE_SH7722
211 bool "Support SH7722 processor"
214 select CPU_HAS_IPR_IRQ
218 menu "Memory management options"
221 bool "Support for memory management hardware"
225 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
226 boot on these systems, this option must not be set.
228 On other systems (such as the SH-3 and 4) where an MMU exists,
229 turning this off will boot the kernel on these machines with the
230 MMU implicitly switched off.
234 default "0x80000000" if MMU
238 hex "Physical memory start address"
241 Computers built with Hitachi SuperH processors always
242 map the ROM starting at address zero. But the processor
243 does not specify the range that RAM takes.
245 The physical memory (RAM) start address will be automatically
246 set to 08000000. Other platforms, such as the Solution Engine
247 boards typically map RAM at 0C000000.
249 Tweak this only when porting to a new machine which does not
250 already have a defconfig. Changing it from the known correct
251 value on any of the known systems will only lead to disaster.
254 hex "Physical memory size"
257 This sets the default memory size assumed by your SH kernel. It can
258 be overridden as normal by the 'mem=' argument on the kernel command
259 line. If unsure, consult your board specifications or just leave it
260 as 0x00400000 which was the default value before this became
264 bool "Support 32-bit physical addressing through PMB"
265 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
268 If you say Y here, physical addressing will be extended to
269 32-bits through the SH-4A PMB. If this is not set, legacy
270 29-bit physical addressing will be used.
273 bool "Enable extended TLB mode"
274 depends on CPU_SHX2 && MMU && EXPERIMENTAL
276 Selecting this option will enable the extended mode of the SH-X2
277 TLB. For legacy SH-X behaviour and interoperability, say N. For
278 all of the fun new features and a willingless to submit bug reports,
282 bool "Support vsyscall page"
286 This will enable support for the kernel mapping a vDSO page
287 in process space, and subsequently handing down the entry point
288 to the libc through the ELF auxiliary vector.
290 From the kernel side this is used for the signal trampoline.
291 For systems with an MMU that can afford to give up a page,
292 (the default value) say Y.
297 depends on NEED_MULTIPLE_NODES
299 config ARCH_FLATMEM_ENABLE
302 config ARCH_POPULATES_NODE_MAP
306 prompt "Kernel page size"
307 default PAGE_SIZE_4KB
312 This is the default page size used by all SuperH CPUs.
316 depends on EXPERIMENTAL && X2TLB
318 This enables 8kB pages as supported by SH-X2 and later MMUs.
320 config PAGE_SIZE_64KB
322 depends on EXPERIMENTAL && CPU_SH4
324 This enables support for 64kB pages, possible on all SH-4
325 CPUs and later. Highly experimental, not recommended.
330 prompt "HugeTLB page size"
331 depends on HUGETLB_PAGE && CPU_SH4 && MMU
332 default HUGETLB_PAGE_SIZE_64K
334 config HUGETLB_PAGE_SIZE_64K
337 config HUGETLB_PAGE_SIZE_256K
341 config HUGETLB_PAGE_SIZE_1MB
344 config HUGETLB_PAGE_SIZE_4MB
348 config HUGETLB_PAGE_SIZE_64MB
358 menu "Cache configuration"
360 config SH7705_CACHE_32KB
361 bool "Enable 32KB cache size for SH7705"
362 depends on CPU_SUBTYPE_SH7705
365 config SH_DIRECT_MAPPED
366 bool "Use direct-mapped caching"
369 Selecting this option will configure the caches to be direct-mapped,
370 even if the cache supports a 2 or 4-way mode. This is useful primarily
371 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
372 SH4-202, SH4-501, etc.)
374 Turn this option off for platforms that do not have a direct-mapped
375 cache, and you have no need to run the caches in such a configuration.
377 config SH_WRITETHROUGH
378 bool "Use write-through caching"
380 Selecting this option will configure the caches in write-through
381 mode, as opposed to the default write-back configuration.
383 Since there's sill some aliasing issues on SH-4, this option will
384 unfortunately still require the majority of flushing functions to
385 be implemented to deal with aliasing.
390 bool "Operand Cache RAM (OCRAM) support"
392 Selecting this option will automatically tear down the number of
393 sets in the dcache by half, which in turn exposes a memory range.
395 The addresses for the OC RAM base will vary according to the
396 processor version. Consult vendor documentation for specifics.