1 menu "Processor selection"
7 select SH_WRITETHROUGH if !CPU_SH2A
23 select CPU_HAS_PTEA if !CPU_SUBTYPE_ST40
33 config CPU_SUBTYPE_ST40
36 select CPU_HAS_INTC2_IRQ
42 comment "SH-2 Processor Support"
44 config CPU_SUBTYPE_SH7604
45 bool "Support SH7604 processor"
48 config CPU_SUBTYPE_SH7619
49 bool "Support SH7619 processor"
52 comment "SH-2A Processor Support"
54 config CPU_SUBTYPE_SH7206
55 bool "Support SH7206 processor"
58 comment "SH-3 Processor Support"
60 config CPU_SUBTYPE_SH7300
61 bool "Support SH7300 processor"
64 config CPU_SUBTYPE_SH7705
65 bool "Support SH7705 processor"
67 select CPU_HAS_PINT_IRQ
69 config CPU_SUBTYPE_SH7706
70 bool "Support SH7706 processor"
73 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
75 config CPU_SUBTYPE_SH7707
76 bool "Support SH7707 processor"
78 select CPU_HAS_PINT_IRQ
80 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
82 config CPU_SUBTYPE_SH7708
83 bool "Support SH7708 processor"
86 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
87 if you have a 100 Mhz SH-3 HD6417708R CPU.
89 config CPU_SUBTYPE_SH7709
90 bool "Support SH7709 processor"
92 select CPU_HAS_PINT_IRQ
94 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
96 config CPU_SUBTYPE_SH7710
97 bool "Support SH7710 processor"
100 Select SH7710 if you have a SH3-DSP SH7710 CPU.
102 comment "SH-4 Processor Support"
104 config CPU_SUBTYPE_SH7750
105 bool "Support SH7750 processor"
107 select CPU_HAS_IPR_IRQ
109 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
111 config CPU_SUBTYPE_SH7091
112 bool "Support SH7091 processor"
114 select CPU_SUBTYPE_SH7750
116 Select SH7091 if you have an SH-4 based Sega device (such as
117 the Dreamcast, Naomi, and Naomi 2).
119 config CPU_SUBTYPE_SH7750R
120 bool "Support SH7750R processor"
122 select CPU_SUBTYPE_SH7750
123 select CPU_HAS_IPR_IRQ
125 config CPU_SUBTYPE_SH7750S
126 bool "Support SH7750S processor"
128 select CPU_SUBTYPE_SH7750
129 select CPU_HAS_IPR_IRQ
131 config CPU_SUBTYPE_SH7751
132 bool "Support SH7751 processor"
134 select CPU_HAS_IPR_IRQ
136 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
137 or if you have a HD6417751R CPU.
139 config CPU_SUBTYPE_SH7751R
140 bool "Support SH7751R processor"
142 select CPU_SUBTYPE_SH7751
143 select CPU_HAS_IPR_IRQ
145 config CPU_SUBTYPE_SH7760
146 bool "Support SH7760 processor"
148 select CPU_HAS_INTC2_IRQ
150 config CPU_SUBTYPE_SH4_202
151 bool "Support SH4-202 processor"
154 comment "ST40 Processor Support"
156 config CPU_SUBTYPE_ST40STB1
157 bool "Support ST40STB1/ST40RA processors"
158 select CPU_SUBTYPE_ST40
160 Select ST40STB1 if you have a ST40RA CPU.
161 This was previously called the ST40STB1, hence the option name.
163 config CPU_SUBTYPE_ST40GX1
164 bool "Support ST40GX1 processor"
165 select CPU_SUBTYPE_ST40
167 Select ST40GX1 if you have a ST40GX1 CPU.
169 comment "SH-4A Processor Support"
171 config CPU_SUBTYPE_SH7770
172 bool "Support SH7770 processor"
175 config CPU_SUBTYPE_SH7780
176 bool "Support SH7780 processor"
178 select CPU_HAS_INTC2_IRQ
180 config CPU_SUBTYPE_SH7785
181 bool "Support SH7785 processor"
183 select CPU_HAS_INTC2_IRQ
185 comment "SH4AL-DSP Processor Support"
187 config CPU_SUBTYPE_SH73180
188 bool "Support SH73180 processor"
191 config CPU_SUBTYPE_SH7343
192 bool "Support SH7343 processor"
197 menu "Memory management options"
200 bool "Support for memory management hardware"
204 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
205 boot on these systems, this option must not be set.
207 On other systems (such as the SH-3 and 4) where an MMU exists,
208 turning this off will boot the kernel on these machines with the
209 MMU implicitly switched off.
213 default "0x80000000" if MMU
217 hex "Physical memory start address"
220 Computers built with Hitachi SuperH processors always
221 map the ROM starting at address zero. But the processor
222 does not specify the range that RAM takes.
224 The physical memory (RAM) start address will be automatically
225 set to 08000000. Other platforms, such as the Solution Engine
226 boards typically map RAM at 0C000000.
228 Tweak this only when porting to a new machine which does not
229 already have a defconfig. Changing it from the known correct
230 value on any of the known systems will only lead to disaster.
233 hex "Physical memory size"
236 This sets the default memory size assumed by your SH kernel. It can
237 be overridden as normal by the 'mem=' argument on the kernel command
238 line. If unsure, consult your board specifications or just leave it
239 as 0x00400000 which was the default value before this became
243 bool "Support 32-bit physical addressing through PMB"
244 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
247 If you say Y here, physical addressing will be extended to
248 32-bits through the SH-4A PMB. If this is not set, legacy
249 29-bit physical addressing will be used.
252 bool "Enable extended TLB mode"
253 depends on CPU_SUBTYPE_SH7785 && MMU && EXPERIMENTAL
255 Selecting this option will enable the extended mode of the SH-X2
256 TLB. For legacy SH-X behaviour and interoperability, say N. For
257 all of the fun new features and a willingless to submit bug reports,
261 bool "Support vsyscall page"
265 This will enable support for the kernel mapping a vDSO page
266 in process space, and subsequently handing down the entry point
267 to the libc through the ELF auxiliary vector.
269 From the kernel side this is used for the signal trampoline.
270 For systems with an MMU that can afford to give up a page,
271 (the default value) say Y.
274 prompt "Kernel page size"
275 default PAGE_SIZE_4KB
280 This is the default page size used by all SuperH CPUs.
284 depends on EXPERIMENTAL && X2TLB
286 This enables 8kB pages as supported by SH-X2 and later MMUs.
288 config PAGE_SIZE_64KB
290 depends on EXPERIMENTAL && CPU_SH4
292 This enables support for 64kB pages, possible on all SH-4
293 CPUs and later. Highly experimental, not recommended.
298 prompt "HugeTLB page size"
299 depends on HUGETLB_PAGE && CPU_SH4 && MMU
300 default HUGETLB_PAGE_SIZE_64K
302 config HUGETLB_PAGE_SIZE_64K
305 config HUGETLB_PAGE_SIZE_256K
309 config HUGETLB_PAGE_SIZE_1MB
312 config HUGETLB_PAGE_SIZE_4MB
316 config HUGETLB_PAGE_SIZE_64MB
326 menu "Cache configuration"
328 config SH7705_CACHE_32KB
329 bool "Enable 32KB cache size for SH7705"
330 depends on CPU_SUBTYPE_SH7705
333 config SH_DIRECT_MAPPED
334 bool "Use direct-mapped caching"
337 Selecting this option will configure the caches to be direct-mapped,
338 even if the cache supports a 2 or 4-way mode. This is useful primarily
339 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
340 SH4-202, SH4-501, etc.)
342 Turn this option off for platforms that do not have a direct-mapped
343 cache, and you have no need to run the caches in such a configuration.
345 config SH_WRITETHROUGH
346 bool "Use write-through caching"
348 Selecting this option will configure the caches in write-through
349 mode, as opposed to the default write-back configuration.
351 Since there's sill some aliasing issues on SH-4, this option will
352 unfortunately still require the majority of flushing functions to
353 be implemented to deal with aliasing.
358 bool "Operand Cache RAM (OCRAM) support"
360 Selecting this option will automatically tear down the number of
361 sets in the dcache by half, which in turn exposes a memory range.
363 The addresses for the OC RAM base will vary according to the
364 processor version. Consult vendor documentation for specifics.