arch/sparc/kernel/pci_sun4v.c

   1 /* pci_sun4v.c: SUN4V specific PCI controller support.
   2  *
   3  * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/percpu.h>
  13 #include <linux/irq.h>
  14 #include <linux/msi.h>
  15 #include <linux/export.h>
  16 #include <linux/log2.h>
  17 #include <linux/of_device.h>
  18 #include <linux/hash.h>
  19 #include <linux/iommu-common.h>
  20
  21 #include <asm/iommu.h>
  22 #include <asm/irq.h>
  23 #include <asm/hypervisor.h>
  24 #include <asm/prom.h>
  25
  26 #include "pci_impl.h"
  27 #include "iommu_common.h"
  28
  29 #include "pci_sun4v.h"
  30
  31 #define DRIVER_NAME     "pci_sun4v"
  32 #define PFX             DRIVER_NAME ": "
  33 static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
  34
  35 static unsigned long vpci_major = 1;
  36 static unsigned long vpci_minor = 1;
  37
  38 #define PGLIST_NENTS    (PAGE_SIZE / sizeof(u64))
  39
  40 struct iommu_batch {
  41         struct device   *dev;           /* Device mapping is for.       */
  42         unsigned long   prot;           /* IOMMU page protections       */
  43         unsigned long   entry;          /* Index into IOTSB.            */
  44         u64             *pglist;        /* List of physical pages       */
  45         unsigned long   npages;         /* Number of pages in list.     */
  46 };
  47
  48 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
  49 static int iommu_batch_initialized;
  50
  51 /* Interrupts must be disabled.  */
  52 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
  53 {
  54         struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
  55
  56         p->dev          = dev;
  57         p->prot         = prot;
  58         p->entry        = entry;
  59         p->npages       = 0;
  60 }
  61
  62 /* Interrupts must be disabled.  */
  63 static long iommu_batch_flush(struct iommu_batch *p)
  64 {
  65         struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
  66         unsigned long devhandle = pbm->devhandle;
  67         unsigned long prot = p->prot;
  68         unsigned long entry = p->entry;
  69         u64 *pglist = p->pglist;
  70         unsigned long npages = p->npages;
  71
  72         while (npages != 0) {
  73                 long num;
  74
  75                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
  76                                           npages, prot, __pa(pglist));
  77                 if (unlikely(num < 0)) {
  78                         if (printk_ratelimit())
  79                                 printk("iommu_batch_flush: IOMMU map of "
  80                                        "[%08lx:%08llx:%lx:%lx:%lx] failed with "
  81                                        "status %ld\n",
  82                                        devhandle, HV_PCI_TSBID(0, entry),
  83                                        npages, prot, __pa(pglist), num);
  84                         return -1;
  85                 }
  86
  87                 entry += num;
  88                 npages -= num;
  89                 pglist += num;
  90         }
  91
  92         p->entry = entry;
  93         p->npages = 0;
  94
  95         return 0;
  96 }
  97
  98 static inline void iommu_batch_new_entry(unsigned long entry)
  99 {
 100         struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
 101
 102         if (p->entry + p->npages == entry)
 103                 return;
 104         if (p->entry != ~0UL)
 105                 iommu_batch_flush(p);
 106         p->entry = entry;
 107 }
 108
 109 /* Interrupts must be disabled.  */
 110 static inline long iommu_batch_add(u64 phys_page)
 111 {
 112         struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
 113
 114         BUG_ON(p->npages >= PGLIST_NENTS);
 115
 116         p->pglist[p->npages++] = phys_page;
 117         if (p->npages == PGLIST_NENTS)
 118                 return iommu_batch_flush(p);
 119
 120         return 0;
 121 }
 122
 123 /* Interrupts must be disabled.  */
 124 static inline long iommu_batch_end(void)
 125 {
 126         struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
 127
 128         BUG_ON(p->npages >= PGLIST_NENTS);
 129
 130         return iommu_batch_flush(p);
 131 }
 132
 133 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
 134                                    dma_addr_t *dma_addrp, gfp_t gfp,
 135                                    struct dma_attrs *attrs)
 136 {
 137         unsigned long flags, order, first_page, npages, n;
 138         struct iommu *iommu;
 139         struct page *page;
 140         void *ret;
 141         long entry;
 142         int nid;
 143
 144         size = IO_PAGE_ALIGN(size);
 145         order = get_order(size);
 146         if (unlikely(order >= MAX_ORDER))
 147                 return NULL;
 148
 149         npages = size >> IO_PAGE_SHIFT;
 150
 151         nid = dev->archdata.numa_node;
 152         page = alloc_pages_node(nid, gfp, order);
 153         if (unlikely(!page))
 154                 return NULL;
 155
 156         first_page = (unsigned long) page_address(page);
 157         memset((char *)first_page, 0, PAGE_SIZE << order);
 158
 159         iommu = dev->archdata.iommu;
 160
 161         entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
 162                                       __this_cpu_read(iommu_pool_hash));
 163
 164         if (unlikely(entry == DMA_ERROR_CODE))
 165                 goto range_alloc_fail;
 166
 167         *dma_addrp = (iommu->tbl.page_table_map_base +
 168                       (entry << IO_PAGE_SHIFT));
 169         ret = (void *) first_page;
 170         first_page = __pa(first_page);
 171
 172         local_irq_save(flags);
 173
 174         iommu_batch_start(dev,
 175                           (HV_PCI_MAP_ATTR_READ |
 176                            HV_PCI_MAP_ATTR_WRITE),
 177                           entry);
 178
 179         for (n = 0; n < npages; n++) {
 180                 long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
 181                 if (unlikely(err < 0L))
 182                         goto iommu_map_fail;
 183         }
 184
 185         if (unlikely(iommu_batch_end() < 0L))
 186                 goto iommu_map_fail;
 187
 188         local_irq_restore(flags);
 189
 190         return ret;
 191
 192 iommu_map_fail:
 193         iommu_tbl_range_free(&iommu->tbl, *dma_addrp, npages, false, NULL);
 194
 195 range_alloc_fail:
 196         free_pages(first_page, order);
 197         return NULL;
 198 }
 199
 200 static void dma_4v_iommu_demap(void *demap_arg, unsigned long entry,
 201                                unsigned long npages)
 202 {
 203         u32 devhandle = *(u32 *)demap_arg;
 204         unsigned long num, flags;
 205
 206         local_irq_save(flags);
 207         do {
 208                 num = pci_sun4v_iommu_demap(devhandle,
 209                                             HV_PCI_TSBID(0, entry),
 210                                             npages);
 211
 212                 entry += num;
 213                 npages -= num;
 214         } while (npages != 0);
 215         local_irq_restore(flags);
 216 }
 217
 218 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
 219                                  dma_addr_t dvma, struct dma_attrs *attrs)
 220 {
 221         struct pci_pbm_info *pbm;
 222         struct iommu *iommu;
 223         unsigned long order, npages, entry;
 224         u32 devhandle;
 225
 226         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 227         iommu = dev->archdata.iommu;
 228         pbm = dev->archdata.host_controller;
 229         devhandle = pbm->devhandle;
 230         entry = ((dvma - iommu->tbl.page_table_map_base) >> IO_PAGE_SHIFT);
 231         dma_4v_iommu_demap(&devhandle, entry, npages);
 232         iommu_tbl_range_free(&iommu->tbl, dvma, npages, false, NULL);
 233         order = get_order(size);
 234         if (order < 10)
 235                 free_pages((unsigned long)cpu, order);
 236 }
 237
 238 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
 239                                   unsigned long offset, size_t sz,
 240                                   enum dma_data_direction direction,
 241                                   struct dma_attrs *attrs)
 242 {
 243         struct iommu *iommu;
 244         unsigned long flags, npages, oaddr;
 245         unsigned long i, base_paddr;
 246         u32 bus_addr, ret;
 247         unsigned long prot;
 248         long entry;
 249
 250         iommu = dev->archdata.iommu;
 251
 252         if (unlikely(direction == DMA_NONE))
 253                 goto bad;
 254
 255         oaddr = (unsigned long)(page_address(page) + offset);
 256         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 257         npages >>= IO_PAGE_SHIFT;
 258
 259         entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
 260                                       __this_cpu_read(iommu_pool_hash));
 261
 262         if (unlikely(entry == DMA_ERROR_CODE))
 263                 goto bad;
 264
 265         bus_addr = (iommu->tbl.page_table_map_base +
 266                     (entry << IO_PAGE_SHIFT));
 267         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 268         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 269         prot = HV_PCI_MAP_ATTR_READ;
 270         if (direction != DMA_TO_DEVICE)
 271                 prot |= HV_PCI_MAP_ATTR_WRITE;
 272
 273         local_irq_save(flags);
 274
 275         iommu_batch_start(dev, prot, entry);
 276
 277         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
 278                 long err = iommu_batch_add(base_paddr);
 279                 if (unlikely(err < 0L))
 280                         goto iommu_map_fail;
 281         }
 282         if (unlikely(iommu_batch_end() < 0L))
 283                 goto iommu_map_fail;
 284
 285         local_irq_restore(flags);
 286
 287         return ret;
 288
 289 bad:
 290         if (printk_ratelimit())
 291                 WARN_ON(1);
 292         return DMA_ERROR_CODE;
 293
 294 iommu_map_fail:
 295         iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, false, NULL);
 296         return DMA_ERROR_CODE;
 297 }
 298
 299 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
 300                               size_t sz, enum dma_data_direction direction,
 301                               struct dma_attrs *attrs)
 302 {
 303         struct pci_pbm_info *pbm;
 304         struct iommu *iommu;
 305         unsigned long npages;
 306         long entry;
 307         u32 devhandle;
 308
 309         if (unlikely(direction == DMA_NONE)) {
 310                 if (printk_ratelimit())
 311                         WARN_ON(1);
 312                 return;
 313         }
 314
 315         iommu = dev->archdata.iommu;
 316         pbm = dev->archdata.host_controller;
 317         devhandle = pbm->devhandle;
 318
 319         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 320         npages >>= IO_PAGE_SHIFT;
 321         bus_addr &= IO_PAGE_MASK;
 322         entry = (bus_addr - iommu->tbl.page_table_map_base) >> IO_PAGE_SHIFT;
 323         dma_4v_iommu_demap(&devhandle, entry, npages);
 324         iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, false, NULL);
 325 }
 326
 327 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
 328                          int nelems, enum dma_data_direction direction,
 329                          struct dma_attrs *attrs)
 330 {
 331         struct scatterlist *s, *outs, *segstart;
 332         unsigned long flags, handle, prot;
 333         dma_addr_t dma_next = 0, dma_addr;
 334         unsigned int max_seg_size;
 335         unsigned long seg_boundary_size;
 336         int outcount, incount, i;
 337         struct iommu *iommu;
 338         unsigned long base_shift;
 339         long err;
 340
 341         BUG_ON(direction == DMA_NONE);
 342
 343         iommu = dev->archdata.iommu;
 344         if (nelems == 0 || !iommu)
 345                 return 0;
 346
 347         prot = HV_PCI_MAP_ATTR_READ;
 348         if (direction != DMA_TO_DEVICE)
 349                 prot |= HV_PCI_MAP_ATTR_WRITE;
 350
 351         outs = s = segstart = &sglist[0];
 352         outcount = 1;
 353         incount = nelems;
 354         handle = 0;
 355
 356         /* Init first segment length for backout at failure */
 357         outs->dma_length = 0;
 358
 359         local_irq_save(flags);
 360
 361         iommu_batch_start(dev, prot, ~0UL);
 362
 363         max_seg_size = dma_get_max_seg_size(dev);
 364         seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 365                                   IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
 366         base_shift = iommu->tbl.page_table_map_base >> IO_PAGE_SHIFT;
 367         for_each_sg(sglist, s, nelems, i) {
 368                 unsigned long paddr, npages, entry, out_entry = 0, slen;
 369
 370                 slen = s->length;
 371                 /* Sanity check */
 372                 if (slen == 0) {
 373                         dma_next = 0;
 374                         continue;
 375                 }
 376                 /* Allocate iommu entries for that segment */
 377                 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
 378                 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
 379                 entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, &handle,
 380                                       __this_cpu_read(iommu_pool_hash));
 381
 382                 /* Handle failure */
 383                 if (unlikely(entry == DMA_ERROR_CODE)) {
 384                         if (printk_ratelimit())
 385                                 printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
 386                                        " npages %lx\n", iommu, paddr, npages);
 387                         goto iommu_map_failed;
 388                 }
 389
 390                 iommu_batch_new_entry(entry);
 391
 392                 /* Convert entry to a dma_addr_t */
 393                 dma_addr = iommu->tbl.page_table_map_base +
 394                         (entry << IO_PAGE_SHIFT);
 395                 dma_addr |= (s->offset & ~IO_PAGE_MASK);
 396
 397                 /* Insert into HW table */
 398                 paddr &= IO_PAGE_MASK;
 399                 while (npages--) {
 400                         err = iommu_batch_add(paddr);
 401                         if (unlikely(err < 0L))
 402                                 goto iommu_map_failed;
 403                         paddr += IO_PAGE_SIZE;
 404                 }
 405
 406                 /* If we are in an open segment, try merging */
 407                 if (segstart != s) {
 408                         /* We cannot merge if:
 409                          * - allocated dma_addr isn't contiguous to previous allocation
 410                          */
 411                         if ((dma_addr != dma_next) ||
 412                             (outs->dma_length + s->length > max_seg_size) ||
 413                             (is_span_boundary(out_entry, base_shift,
 414                                               seg_boundary_size, outs, s))) {
 415                                 /* Can't merge: create a new segment */
 416                                 segstart = s;
 417                                 outcount++;
 418                                 outs = sg_next(outs);
 419                         } else {
 420                                 outs->dma_length += s->length;
 421                         }
 422                 }
 423
 424                 if (segstart == s) {
 425                         /* This is a new segment, fill entries */
 426                         outs->dma_address = dma_addr;
 427                         outs->dma_length = slen;
 428                         out_entry = entry;
 429                 }
 430
 431                 /* Calculate next page pointer for contiguous check */
 432                 dma_next = dma_addr + slen;
 433         }
 434
 435         err = iommu_batch_end();
 436
 437         if (unlikely(err < 0L))
 438                 goto iommu_map_failed;
 439
 440         local_irq_restore(flags);
 441
 442         if (outcount < incount) {
 443                 outs = sg_next(outs);
 444                 outs->dma_address = DMA_ERROR_CODE;
 445                 outs->dma_length = 0;
 446         }
 447
 448         return outcount;
 449
 450 iommu_map_failed:
 451         for_each_sg(sglist, s, nelems, i) {
 452                 if (s->dma_length != 0) {
 453                         unsigned long vaddr, npages;
 454
 455                         vaddr = s->dma_address & IO_PAGE_MASK;
 456                         npages = iommu_num_pages(s->dma_address, s->dma_length,
 457                                                  IO_PAGE_SIZE);
 458                         iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
 459                                              false, NULL);
 460                         /* XXX demap? XXX */
 461                         s->dma_address = DMA_ERROR_CODE;
 462                         s->dma_length = 0;
 463                 }
 464                 if (s == outs)
 465                         break;
 466         }
 467         local_irq_restore(flags);
 468
 469         return 0;
 470 }
 471
 472 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
 473                             int nelems, enum dma_data_direction direction,
 474                             struct dma_attrs *attrs)
 475 {
 476         struct pci_pbm_info *pbm;
 477         struct scatterlist *sg;
 478         struct iommu *iommu;
 479         unsigned long flags, entry;
 480         u32 devhandle;
 481
 482         BUG_ON(direction == DMA_NONE);
 483
 484         iommu = dev->archdata.iommu;
 485         pbm = dev->archdata.host_controller;
 486         devhandle = pbm->devhandle;
 487
 488         local_irq_save(flags);
 489
 490         sg = sglist;
 491         while (nelems--) {
 492                 dma_addr_t dma_handle = sg->dma_address;
 493                 unsigned int len = sg->dma_length;
 494                 unsigned long npages;
 495                 struct iommu_table *tbl = &iommu->tbl;
 496                 unsigned long shift = IO_PAGE_SHIFT;
 497
 498                 if (!len)
 499                         break;
 500                 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
 501                 entry = ((dma_handle - tbl->page_table_map_base) >> shift);
 502                 dma_4v_iommu_demap(&devhandle, entry, npages);
 503                 iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
 504                                      false, NULL);
 505                 sg = sg_next(sg);
 506         }
 507
 508         local_irq_restore(flags);
 509 }
 510
 511 static struct dma_map_ops sun4v_dma_ops = {
 512         .alloc                          = dma_4v_alloc_coherent,
 513         .free                           = dma_4v_free_coherent,
 514         .map_page                       = dma_4v_map_page,
 515         .unmap_page                     = dma_4v_unmap_page,
 516         .map_sg                         = dma_4v_map_sg,
 517         .unmap_sg                       = dma_4v_unmap_sg,
 518 };
 519
 520 static struct iommu_tbl_ops dma_4v_iommu_ops;
 521
 522 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
 523 {
 524         struct property *prop;
 525         struct device_node *dp;
 526
 527         dp = pbm->op->dev.of_node;
 528         prop = of_find_property(dp, "66mhz-capable", NULL);
 529         pbm->is_66mhz_capable = (prop != NULL);
 530         pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 531
 532         /* XXX register error interrupt handlers XXX */
 533 }
 534
 535 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
 536                                             struct iommu_table *iommu)
 537 {
 538         struct iommu_pool *pool;
 539         unsigned long i, pool_nr, cnt = 0;
 540         u32 devhandle;
 541
 542         devhandle = pbm->devhandle;
 543         for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
 544                 pool = &(iommu->arena_pool[pool_nr]);
 545                 for (i = pool->start; i <= pool->end; i++) {
 546                         unsigned long ret, io_attrs, ra;
 547
 548                         ret = pci_sun4v_iommu_getmap(devhandle,
 549                                                      HV_PCI_TSBID(0, i),
 550                                                      &io_attrs, &ra);
 551                         if (ret == HV_EOK) {
 552                                 if (page_in_phys_avail(ra)) {
 553                                         pci_sun4v_iommu_demap(devhandle,
 554                                                               HV_PCI_TSBID(0,
 555                                                               i), 1);
 556                                 } else {
 557                                         cnt++;
 558                                         __set_bit(i, iommu->map);
 559                                 }
 560                         }
 561                 }
 562         }
 563         return cnt;
 564 }
 565
 566 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
 567 {
 568         static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
 569         struct iommu *iommu = pbm->iommu;
 570         unsigned long num_tsb_entries, sz;
 571         u32 dma_mask, dma_offset;
 572         const u32 *vdma;
 573
 574         vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
 575         if (!vdma)
 576                 vdma = vdma_default;
 577
 578         if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
 579                 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
 580                        vdma[0], vdma[1]);
 581                 return -EINVAL;
 582         }
 583
 584         dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
 585         num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
 586
 587         dma_offset = vdma[0];
 588
 589         /* Setup initial software IOMMU state. */
 590         iommu->ctx_lowest_free = 1;
 591         iommu->tbl.page_table_map_base = dma_offset;
 592         iommu->dma_addr_mask = dma_mask;
 593
 594         /* Allocate and initialize the free area map.  */
 595         sz = (num_tsb_entries + 7) / 8;
 596         sz = (sz + 7UL) & ~7UL;
 597         iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
 598         if (!iommu->tbl.map) {
 599                 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
 600                 return -ENOMEM;
 601         }
 602         iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
 603                             &dma_4v_iommu_ops, false /* no large_pool */,
 604                             0 /* default npools */);
 605         sz = probe_existing_entries(pbm, &iommu->tbl);
 606         if (sz)
 607                 printk("%s: Imported %lu TSB entries from OBP\n",
 608                        pbm->name, sz);
 609
 610         return 0;
 611 }
 612
 613 #ifdef CONFIG_PCI_MSI
 614 struct pci_sun4v_msiq_entry {
 615         u64             version_type;
 616 #define MSIQ_VERSION_MASK               0xffffffff00000000UL
 617 #define MSIQ_VERSION_SHIFT              32
 618 #define MSIQ_TYPE_MASK                  0x00000000000000ffUL
 619 #define MSIQ_TYPE_SHIFT                 0
 620 #define MSIQ_TYPE_NONE                  0x00
 621 #define MSIQ_TYPE_MSG                   0x01
 622 #define MSIQ_TYPE_MSI32                 0x02
 623 #define MSIQ_TYPE_MSI64                 0x03
 624 #define MSIQ_TYPE_INTX                  0x08
 625 #define MSIQ_TYPE_NONE2                 0xff
 626
 627         u64             intx_sysino;
 628         u64             reserved1;
 629         u64             stick;
 630         u64             req_id;  /* bus/device/func */
 631 #define MSIQ_REQID_BUS_MASK             0xff00UL
 632 #define MSIQ_REQID_BUS_SHIFT            8
 633 #define MSIQ_REQID_DEVICE_MASK          0x00f8UL
 634 #define MSIQ_REQID_DEVICE_SHIFT         3
 635 #define MSIQ_REQID_FUNC_MASK            0x0007UL
 636 #define MSIQ_REQID_FUNC_SHIFT           0
 637
 638         u64             msi_address;
 639
 640         /* The format of this value is message type dependent.
 641          * For MSI bits 15:0 are the data from the MSI packet.
 642          * For MSI-X bits 31:0 are the data from the MSI packet.
 643          * For MSG, the message code and message routing code where:
 644          *      bits 39:32 is the bus/device/fn of the msg target-id
 645          *      bits 18:16 is the message routing code
 646          *      bits 7:0 is the message code
 647          * For INTx the low order 2-bits are:
 648          *      00 - INTA
 649          *      01 - INTB
 650          *      10 - INTC
 651          *      11 - INTD
 652          */
 653         u64             msi_data;
 654
 655         u64             reserved2;
 656 };
 657
 658 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 659                               unsigned long *head)
 660 {
 661         unsigned long err, limit;
 662
 663         err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
 664         if (unlikely(err))
 665                 return -ENXIO;
 666
 667         limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 668         if (unlikely(*head >= limit))
 669                 return -EFBIG;
 670
 671         return 0;
 672 }
 673
 674 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
 675                                  unsigned long msiqid, unsigned long *head,
 676                                  unsigned long *msi)
 677 {
 678         struct pci_sun4v_msiq_entry *ep;
 679         unsigned long err, type;
 680
 681         /* Note: void pointer arithmetic, 'head' is a byte offset  */
 682         ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
 683                                  (pbm->msiq_ent_count *
 684                                   sizeof(struct pci_sun4v_msiq_entry))) +
 685               *head);
 686
 687         if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
 688                 return 0;
 689
 690         type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
 691         if (unlikely(type != MSIQ_TYPE_MSI32 &&
 692                      type != MSIQ_TYPE_MSI64))
 693                 return -EINVAL;
 694
 695         *msi = ep->msi_data;
 696
 697         err = pci_sun4v_msi_setstate(pbm->devhandle,
 698                                      ep->msi_data /* msi_num */,
 699                                      HV_MSISTATE_IDLE);
 700         if (unlikely(err))
 701                 return -ENXIO;
 702
 703         /* Clear the entry.  */
 704         ep->version_type &= ~MSIQ_TYPE_MASK;
 705
 706         (*head) += sizeof(struct pci_sun4v_msiq_entry);
 707         if (*head >=
 708             (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
 709                 *head = 0;
 710
 711         return 1;
 712 }
 713
 714 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 715                               unsigned long head)
 716 {
 717         unsigned long err;
 718
 719         err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
 720         if (unlikely(err))
 721                 return -EINVAL;
 722
 723         return 0;
 724 }
 725
 726 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
 727                                unsigned long msi, int is_msi64)
 728 {
 729         if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
 730                                   (is_msi64 ?
 731                                    HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
 732                 return -ENXIO;
 733         if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
 734                 return -ENXIO;
 735         if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
 736                 return -ENXIO;
 737         return 0;
 738 }
 739
 740 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
 741 {
 742         unsigned long err, msiqid;
 743
 744         err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
 745         if (err)
 746                 return -ENXIO;
 747
 748         pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
 749
 750         return 0;
 751 }
 752
 753 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
 754 {
 755         unsigned long q_size, alloc_size, pages, order;
 756         int i;
 757
 758         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 759         alloc_size = (pbm->msiq_num * q_size);
 760         order = get_order(alloc_size);
 761         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
 762         if (pages == 0UL) {
 763                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
 764                        order);
 765                 return -ENOMEM;
 766         }
 767         memset((char *)pages, 0, PAGE_SIZE << order);
 768         pbm->msi_queues = (void *) pages;
 769
 770         for (i = 0; i < pbm->msiq_num; i++) {
 771                 unsigned long err, base = __pa(pages + (i * q_size));
 772                 unsigned long ret1, ret2;
 773
 774                 err = pci_sun4v_msiq_conf(pbm->devhandle,
 775                                           pbm->msiq_first + i,
 776                                           base, pbm->msiq_ent_count);
 777                 if (err) {
 778                         printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
 779                                err);
 780                         goto h_error;
 781                 }
 782
 783                 err = pci_sun4v_msiq_info(pbm->devhandle,
 784                                           pbm->msiq_first + i,
 785                                           &ret1, &ret2);
 786                 if (err) {
 787                         printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
 788                                err);
 789                         goto h_error;
 790                 }
 791                 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
 792                         printk(KERN_ERR "MSI: Bogus qconf "
 793                                "expected[%lx:%x] got[%lx:%lx]\n",
 794                                base, pbm->msiq_ent_count,
 795                                ret1, ret2);
 796                         goto h_error;
 797                 }
 798         }
 799
 800         return 0;
 801
 802 h_error:
 803         free_pages(pages, order);
 804         return -EINVAL;
 805 }
 806
 807 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
 808 {
 809         unsigned long q_size, alloc_size, pages, order;
 810         int i;
 811
 812         for (i = 0; i < pbm->msiq_num; i++) {
 813                 unsigned long msiqid = pbm->msiq_first + i;
 814
 815                 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
 816         }
 817
 818         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 819         alloc_size = (pbm->msiq_num * q_size);
 820         order = get_order(alloc_size);
 821
 822         pages = (unsigned long) pbm->msi_queues;
 823
 824         free_pages(pages, order);
 825
 826         pbm->msi_queues = NULL;
 827 }
 828
 829 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
 830                                     unsigned long msiqid,
 831                                     unsigned long devino)
 832 {
 833         unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
 834
 835         if (!irq)
 836                 return -ENOMEM;
 837
 838         if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
 839                 return -EINVAL;
 840         if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
 841                 return -EINVAL;
 842
 843         return irq;
 844 }
 845
 846 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
 847         .get_head       =       pci_sun4v_get_head,
 848         .dequeue_msi    =       pci_sun4v_dequeue_msi,
 849         .set_head       =       pci_sun4v_set_head,
 850         .msi_setup      =       pci_sun4v_msi_setup,
 851         .msi_teardown   =       pci_sun4v_msi_teardown,
 852         .msiq_alloc     =       pci_sun4v_msiq_alloc,
 853         .msiq_free      =       pci_sun4v_msiq_free,
 854         .msiq_build_irq =       pci_sun4v_msiq_build_irq,
 855 };
 856
 857 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
 858 {
 859         sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
 860 }
 861 #else /* CONFIG_PCI_MSI */
 862 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
 863 {
 864 }
 865 #endif /* !(CONFIG_PCI_MSI) */
 866
 867 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
 868                               struct platform_device *op, u32 devhandle)
 869 {
 870         struct device_node *dp = op->dev.of_node;
 871         int err;
 872
 873         pbm->numa_node = of_node_to_nid(dp);
 874
 875         pbm->pci_ops = &sun4v_pci_ops;
 876         pbm->config_space_reg_bits = 12;
 877
 878         pbm->index = pci_num_pbms++;
 879
 880         pbm->op = op;
 881
 882         pbm->devhandle = devhandle;
 883
 884         pbm->name = dp->full_name;
 885
 886         printk("%s: SUN4V PCI Bus Module\n", pbm->name);
 887         printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
 888
 889         pci_determine_mem_io_space(pbm);
 890
 891         pci_get_pbm_props(pbm);
 892
 893         err = pci_sun4v_iommu_init(pbm);
 894         if (err)
 895                 return err;
 896
 897         pci_sun4v_msi_init(pbm);
 898
 899         pci_sun4v_scan_bus(pbm, &op->dev);
 900
 901         pbm->next = pci_pbm_root;
 902         pci_pbm_root = pbm;
 903
 904         return 0;
 905 }
 906
 907 static int pci_sun4v_probe(struct platform_device *op)
 908 {
 909         const struct linux_prom64_registers *regs;
 910         static int hvapi_negotiated = 0;
 911         struct pci_pbm_info *pbm;
 912         struct device_node *dp;
 913         struct iommu *iommu;
 914         u32 devhandle;
 915         int i, err;
 916
 917         dp = op->dev.of_node;
 918
 919         if (!hvapi_negotiated++) {
 920                 err = sun4v_hvapi_register(HV_GRP_PCI,
 921                                            vpci_major,
 922                                            &vpci_minor);
 923
 924                 if (err) {
 925                         printk(KERN_ERR PFX "Could not register hvapi, "
 926                                "err=%d\n", err);
 927                         return err;
 928                 }
 929                 printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n",
 930                        vpci_major, vpci_minor);
 931
 932                 dma_ops = &sun4v_dma_ops;
 933         }
 934
 935         regs = of_get_property(dp, "reg", NULL);
 936         err = -ENODEV;
 937         if (!regs) {
 938                 printk(KERN_ERR PFX "Could not find config registers\n");
 939                 goto out_err;
 940         }
 941         devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 942
 943         err = -ENOMEM;
 944         if (!iommu_batch_initialized) {
 945                 for_each_possible_cpu(i) {
 946                         unsigned long page = get_zeroed_page(GFP_KERNEL);
 947
 948                         if (!page)
 949                                 goto out_err;
 950
 951                         per_cpu(iommu_batch, i).pglist = (u64 *) page;
 952                 }
 953                 iommu_batch_initialized = 1;
 954         }
 955
 956         pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
 957         if (!pbm) {
 958                 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
 959                 goto out_err;
 960         }
 961
 962         iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
 963         if (!iommu) {
 964                 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
 965                 goto out_free_controller;
 966         }
 967
 968         pbm->iommu = iommu;
 969
 970         err = pci_sun4v_pbm_init(pbm, op, devhandle);
 971         if (err)
 972                 goto out_free_iommu;
 973
 974         dev_set_drvdata(&op->dev, pbm);
 975
 976         return 0;
 977
 978 out_free_iommu:
 979         kfree(pbm->iommu);
 980
 981 out_free_controller:
 982         kfree(pbm);
 983
 984 out_err:
 985         return err;
 986 }
 987
 988 static const struct of_device_id pci_sun4v_match[] = {
 989         {
 990                 .name = "pci",
 991                 .compatible = "SUNW,sun4v-pci",
 992         },
 993         {},
 994 };
 995
 996 static struct platform_driver pci_sun4v_driver = {
 997         .driver = {
 998                 .name = DRIVER_NAME,
 999                 .of_match_table = pci_sun4v_match,
1000         },
1001         .probe          = pci_sun4v_probe,
1002 };
1003
1004 static void setup_iommu_pool_hash(void)
1005 {
1006         unsigned int i;
1007
1008         for_each_possible_cpu(i)
1009                 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
1010 }
1011
1012 static int __init pci_sun4v_init(void)
1013 {
1014         setup_iommu_pool_hash();
1015         return platform_driver_register(&pci_sun4v_driver);
1016 }
1017
1018 subsys_initcall(pci_sun4v_init);