1 /* pci_sun4v.c: SUN4V specific PCI controller support.
3 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/kernel.h>
7 #include <linux/types.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/export.h>
16 #include <linux/log2.h>
17 #include <linux/of_device.h>
19 #include <asm/iommu.h>
21 #include <asm/hypervisor.h>
25 #include "iommu_common.h"
27 #include "pci_sun4v.h"
29 #define DRIVER_NAME "pci_sun4v"
30 #define PFX DRIVER_NAME ": "
32 static unsigned long vpci_major = 1;
33 static unsigned long vpci_minor = 1;
35 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
38 struct device *dev; /* Device mapping is for. */
39 unsigned long prot; /* IOMMU page protections */
40 unsigned long entry; /* Index into IOTSB. */
41 u64 *pglist; /* List of physical pages */
42 unsigned long npages; /* Number of pages in list. */
45 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
46 static int iommu_batch_initialized;
48 /* Interrupts must be disabled. */
49 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
51 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
59 /* Interrupts must be disabled. */
60 static long iommu_batch_flush(struct iommu_batch *p)
62 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
63 unsigned long devhandle = pbm->devhandle;
64 unsigned long prot = p->prot;
65 unsigned long entry = p->entry;
66 u64 *pglist = p->pglist;
67 unsigned long npages = p->npages;
72 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
73 npages, prot, __pa(pglist));
74 if (unlikely(num < 0)) {
75 if (printk_ratelimit())
76 printk("iommu_batch_flush: IOMMU map of "
77 "[%08lx:%08llx:%lx:%lx:%lx] failed with "
79 devhandle, HV_PCI_TSBID(0, entry),
80 npages, prot, __pa(pglist), num);
95 static inline void iommu_batch_new_entry(unsigned long entry)
97 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
99 if (p->entry + p->npages == entry)
101 if (p->entry != ~0UL)
102 iommu_batch_flush(p);
106 /* Interrupts must be disabled. */
107 static inline long iommu_batch_add(u64 phys_page)
109 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
111 BUG_ON(p->npages >= PGLIST_NENTS);
113 p->pglist[p->npages++] = phys_page;
114 if (p->npages == PGLIST_NENTS)
115 return iommu_batch_flush(p);
120 /* Interrupts must be disabled. */
121 static inline long iommu_batch_end(void)
123 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
125 BUG_ON(p->npages >= PGLIST_NENTS);
127 return iommu_batch_flush(p);
130 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
131 dma_addr_t *dma_addrp, gfp_t gfp,
132 struct dma_attrs *attrs)
134 unsigned long flags, order, first_page, npages, n;
141 size = IO_PAGE_ALIGN(size);
142 order = get_order(size);
143 if (unlikely(order >= MAX_ORDER))
146 npages = size >> IO_PAGE_SHIFT;
148 nid = dev->archdata.numa_node;
149 page = alloc_pages_node(nid, gfp, order);
153 first_page = (unsigned long) page_address(page);
154 memset((char *)first_page, 0, PAGE_SIZE << order);
156 iommu = dev->archdata.iommu;
158 spin_lock_irqsave(&iommu->lock, flags);
159 entry = iommu_range_alloc(dev, iommu, npages, NULL);
160 spin_unlock_irqrestore(&iommu->lock, flags);
162 if (unlikely(entry == DMA_ERROR_CODE))
163 goto range_alloc_fail;
165 *dma_addrp = (iommu->page_table_map_base +
166 (entry << IO_PAGE_SHIFT));
167 ret = (void *) first_page;
168 first_page = __pa(first_page);
170 local_irq_save(flags);
172 iommu_batch_start(dev,
173 (HV_PCI_MAP_ATTR_READ |
174 HV_PCI_MAP_ATTR_WRITE),
177 for (n = 0; n < npages; n++) {
178 long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
179 if (unlikely(err < 0L))
183 if (unlikely(iommu_batch_end() < 0L))
186 local_irq_restore(flags);
191 /* Interrupts are disabled. */
192 spin_lock(&iommu->lock);
193 iommu_range_free(iommu, *dma_addrp, npages);
194 spin_unlock_irqrestore(&iommu->lock, flags);
197 free_pages(first_page, order);
201 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
202 dma_addr_t dvma, struct dma_attrs *attrs)
204 struct pci_pbm_info *pbm;
206 unsigned long flags, order, npages, entry;
209 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
210 iommu = dev->archdata.iommu;
211 pbm = dev->archdata.host_controller;
212 devhandle = pbm->devhandle;
213 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
215 spin_lock_irqsave(&iommu->lock, flags);
217 iommu_range_free(iommu, dvma, npages);
222 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
226 } while (npages != 0);
228 spin_unlock_irqrestore(&iommu->lock, flags);
230 order = get_order(size);
232 free_pages((unsigned long)cpu, order);
235 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
236 unsigned long offset, size_t sz,
237 enum dma_data_direction direction,
238 struct dma_attrs *attrs)
241 unsigned long flags, npages, oaddr;
242 unsigned long i, base_paddr;
247 iommu = dev->archdata.iommu;
249 if (unlikely(direction == DMA_NONE))
252 oaddr = (unsigned long)(page_address(page) + offset);
253 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
254 npages >>= IO_PAGE_SHIFT;
256 spin_lock_irqsave(&iommu->lock, flags);
257 entry = iommu_range_alloc(dev, iommu, npages, NULL);
258 spin_unlock_irqrestore(&iommu->lock, flags);
260 if (unlikely(entry == DMA_ERROR_CODE))
263 bus_addr = (iommu->page_table_map_base +
264 (entry << IO_PAGE_SHIFT));
265 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
266 base_paddr = __pa(oaddr & IO_PAGE_MASK);
267 prot = HV_PCI_MAP_ATTR_READ;
268 if (direction != DMA_TO_DEVICE)
269 prot |= HV_PCI_MAP_ATTR_WRITE;
271 local_irq_save(flags);
273 iommu_batch_start(dev, prot, entry);
275 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
276 long err = iommu_batch_add(base_paddr);
277 if (unlikely(err < 0L))
280 if (unlikely(iommu_batch_end() < 0L))
283 local_irq_restore(flags);
288 if (printk_ratelimit())
290 return DMA_ERROR_CODE;
293 /* Interrupts are disabled. */
294 spin_lock(&iommu->lock);
295 iommu_range_free(iommu, bus_addr, npages);
296 spin_unlock_irqrestore(&iommu->lock, flags);
298 return DMA_ERROR_CODE;
301 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
302 size_t sz, enum dma_data_direction direction,
303 struct dma_attrs *attrs)
305 struct pci_pbm_info *pbm;
307 unsigned long flags, npages;
311 if (unlikely(direction == DMA_NONE)) {
312 if (printk_ratelimit())
317 iommu = dev->archdata.iommu;
318 pbm = dev->archdata.host_controller;
319 devhandle = pbm->devhandle;
321 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
322 npages >>= IO_PAGE_SHIFT;
323 bus_addr &= IO_PAGE_MASK;
325 spin_lock_irqsave(&iommu->lock, flags);
327 iommu_range_free(iommu, bus_addr, npages);
329 entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
333 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
337 } while (npages != 0);
339 spin_unlock_irqrestore(&iommu->lock, flags);
342 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
343 int nelems, enum dma_data_direction direction,
344 struct dma_attrs *attrs)
346 struct scatterlist *s, *outs, *segstart;
347 unsigned long flags, handle, prot;
348 dma_addr_t dma_next = 0, dma_addr;
349 unsigned int max_seg_size;
350 unsigned long seg_boundary_size;
351 int outcount, incount, i;
353 unsigned long base_shift;
356 BUG_ON(direction == DMA_NONE);
358 iommu = dev->archdata.iommu;
359 if (nelems == 0 || !iommu)
362 prot = HV_PCI_MAP_ATTR_READ;
363 if (direction != DMA_TO_DEVICE)
364 prot |= HV_PCI_MAP_ATTR_WRITE;
366 outs = s = segstart = &sglist[0];
371 /* Init first segment length for backout at failure */
372 outs->dma_length = 0;
374 spin_lock_irqsave(&iommu->lock, flags);
376 iommu_batch_start(dev, prot, ~0UL);
378 max_seg_size = dma_get_max_seg_size(dev);
379 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
380 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
381 base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
382 for_each_sg(sglist, s, nelems, i) {
383 unsigned long paddr, npages, entry, out_entry = 0, slen;
391 /* Allocate iommu entries for that segment */
392 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
393 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
394 entry = iommu_range_alloc(dev, iommu, npages, &handle);
397 if (unlikely(entry == DMA_ERROR_CODE)) {
398 if (printk_ratelimit())
399 printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
400 " npages %lx\n", iommu, paddr, npages);
401 goto iommu_map_failed;
404 iommu_batch_new_entry(entry);
406 /* Convert entry to a dma_addr_t */
407 dma_addr = iommu->page_table_map_base +
408 (entry << IO_PAGE_SHIFT);
409 dma_addr |= (s->offset & ~IO_PAGE_MASK);
411 /* Insert into HW table */
412 paddr &= IO_PAGE_MASK;
414 err = iommu_batch_add(paddr);
415 if (unlikely(err < 0L))
416 goto iommu_map_failed;
417 paddr += IO_PAGE_SIZE;
420 /* If we are in an open segment, try merging */
422 /* We cannot merge if:
423 * - allocated dma_addr isn't contiguous to previous allocation
425 if ((dma_addr != dma_next) ||
426 (outs->dma_length + s->length > max_seg_size) ||
427 (is_span_boundary(out_entry, base_shift,
428 seg_boundary_size, outs, s))) {
429 /* Can't merge: create a new segment */
432 outs = sg_next(outs);
434 outs->dma_length += s->length;
439 /* This is a new segment, fill entries */
440 outs->dma_address = dma_addr;
441 outs->dma_length = slen;
445 /* Calculate next page pointer for contiguous check */
446 dma_next = dma_addr + slen;
449 err = iommu_batch_end();
451 if (unlikely(err < 0L))
452 goto iommu_map_failed;
454 spin_unlock_irqrestore(&iommu->lock, flags);
456 if (outcount < incount) {
457 outs = sg_next(outs);
458 outs->dma_address = DMA_ERROR_CODE;
459 outs->dma_length = 0;
465 for_each_sg(sglist, s, nelems, i) {
466 if (s->dma_length != 0) {
467 unsigned long vaddr, npages;
469 vaddr = s->dma_address & IO_PAGE_MASK;
470 npages = iommu_num_pages(s->dma_address, s->dma_length,
472 iommu_range_free(iommu, vaddr, npages);
474 s->dma_address = DMA_ERROR_CODE;
480 spin_unlock_irqrestore(&iommu->lock, flags);
485 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
486 int nelems, enum dma_data_direction direction,
487 struct dma_attrs *attrs)
489 struct pci_pbm_info *pbm;
490 struct scatterlist *sg;
495 BUG_ON(direction == DMA_NONE);
497 iommu = dev->archdata.iommu;
498 pbm = dev->archdata.host_controller;
499 devhandle = pbm->devhandle;
501 spin_lock_irqsave(&iommu->lock, flags);
505 dma_addr_t dma_handle = sg->dma_address;
506 unsigned int len = sg->dma_length;
507 unsigned long npages, entry;
511 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
512 iommu_range_free(iommu, dma_handle, npages);
514 entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
518 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
527 spin_unlock_irqrestore(&iommu->lock, flags);
530 static struct dma_map_ops sun4v_dma_ops = {
531 .alloc = dma_4v_alloc_coherent,
532 .free = dma_4v_free_coherent,
533 .map_page = dma_4v_map_page,
534 .unmap_page = dma_4v_unmap_page,
535 .map_sg = dma_4v_map_sg,
536 .unmap_sg = dma_4v_unmap_sg,
539 static void __devinit pci_sun4v_scan_bus(struct pci_pbm_info *pbm,
540 struct device *parent)
542 struct property *prop;
543 struct device_node *dp;
545 dp = pbm->op->dev.of_node;
546 prop = of_find_property(dp, "66mhz-capable", NULL);
547 pbm->is_66mhz_capable = (prop != NULL);
548 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
550 /* XXX register error interrupt handlers XXX */
553 static unsigned long __devinit probe_existing_entries(struct pci_pbm_info *pbm,
556 struct iommu_arena *arena = &iommu->arena;
557 unsigned long i, cnt = 0;
560 devhandle = pbm->devhandle;
561 for (i = 0; i < arena->limit; i++) {
562 unsigned long ret, io_attrs, ra;
564 ret = pci_sun4v_iommu_getmap(devhandle,
568 if (page_in_phys_avail(ra)) {
569 pci_sun4v_iommu_demap(devhandle,
570 HV_PCI_TSBID(0, i), 1);
573 __set_bit(i, arena->map);
581 static int __devinit pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
583 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
584 struct iommu *iommu = pbm->iommu;
585 unsigned long num_tsb_entries, sz;
586 u32 dma_mask, dma_offset;
589 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
593 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
594 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
599 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
600 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
602 dma_offset = vdma[0];
604 /* Setup initial software IOMMU state. */
605 spin_lock_init(&iommu->lock);
606 iommu->ctx_lowest_free = 1;
607 iommu->page_table_map_base = dma_offset;
608 iommu->dma_addr_mask = dma_mask;
610 /* Allocate and initialize the free area map. */
611 sz = (num_tsb_entries + 7) / 8;
612 sz = (sz + 7UL) & ~7UL;
613 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
614 if (!iommu->arena.map) {
615 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
618 iommu->arena.limit = num_tsb_entries;
620 sz = probe_existing_entries(pbm, iommu);
622 printk("%s: Imported %lu TSB entries from OBP\n",
628 #ifdef CONFIG_PCI_MSI
629 struct pci_sun4v_msiq_entry {
631 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
632 #define MSIQ_VERSION_SHIFT 32
633 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
634 #define MSIQ_TYPE_SHIFT 0
635 #define MSIQ_TYPE_NONE 0x00
636 #define MSIQ_TYPE_MSG 0x01
637 #define MSIQ_TYPE_MSI32 0x02
638 #define MSIQ_TYPE_MSI64 0x03
639 #define MSIQ_TYPE_INTX 0x08
640 #define MSIQ_TYPE_NONE2 0xff
645 u64 req_id; /* bus/device/func */
646 #define MSIQ_REQID_BUS_MASK 0xff00UL
647 #define MSIQ_REQID_BUS_SHIFT 8
648 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
649 #define MSIQ_REQID_DEVICE_SHIFT 3
650 #define MSIQ_REQID_FUNC_MASK 0x0007UL
651 #define MSIQ_REQID_FUNC_SHIFT 0
655 /* The format of this value is message type dependent.
656 * For MSI bits 15:0 are the data from the MSI packet.
657 * For MSI-X bits 31:0 are the data from the MSI packet.
658 * For MSG, the message code and message routing code where:
659 * bits 39:32 is the bus/device/fn of the msg target-id
660 * bits 18:16 is the message routing code
661 * bits 7:0 is the message code
662 * For INTx the low order 2-bits are:
673 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
676 unsigned long err, limit;
678 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
682 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
683 if (unlikely(*head >= limit))
689 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
690 unsigned long msiqid, unsigned long *head,
693 struct pci_sun4v_msiq_entry *ep;
694 unsigned long err, type;
696 /* Note: void pointer arithmetic, 'head' is a byte offset */
697 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
698 (pbm->msiq_ent_count *
699 sizeof(struct pci_sun4v_msiq_entry))) +
702 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
705 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
706 if (unlikely(type != MSIQ_TYPE_MSI32 &&
707 type != MSIQ_TYPE_MSI64))
712 err = pci_sun4v_msi_setstate(pbm->devhandle,
713 ep->msi_data /* msi_num */,
718 /* Clear the entry. */
719 ep->version_type &= ~MSIQ_TYPE_MASK;
721 (*head) += sizeof(struct pci_sun4v_msiq_entry);
723 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
729 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
734 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
741 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
742 unsigned long msi, int is_msi64)
744 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
746 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
748 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
750 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
755 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
757 unsigned long err, msiqid;
759 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
763 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
768 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
770 unsigned long q_size, alloc_size, pages, order;
773 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
774 alloc_size = (pbm->msiq_num * q_size);
775 order = get_order(alloc_size);
776 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
778 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
782 memset((char *)pages, 0, PAGE_SIZE << order);
783 pbm->msi_queues = (void *) pages;
785 for (i = 0; i < pbm->msiq_num; i++) {
786 unsigned long err, base = __pa(pages + (i * q_size));
787 unsigned long ret1, ret2;
789 err = pci_sun4v_msiq_conf(pbm->devhandle,
791 base, pbm->msiq_ent_count);
793 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
798 err = pci_sun4v_msiq_info(pbm->devhandle,
802 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
806 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
807 printk(KERN_ERR "MSI: Bogus qconf "
808 "expected[%lx:%x] got[%lx:%lx]\n",
809 base, pbm->msiq_ent_count,
818 free_pages(pages, order);
822 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
824 unsigned long q_size, alloc_size, pages, order;
827 for (i = 0; i < pbm->msiq_num; i++) {
828 unsigned long msiqid = pbm->msiq_first + i;
830 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
833 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
834 alloc_size = (pbm->msiq_num * q_size);
835 order = get_order(alloc_size);
837 pages = (unsigned long) pbm->msi_queues;
839 free_pages(pages, order);
841 pbm->msi_queues = NULL;
844 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
845 unsigned long msiqid,
846 unsigned long devino)
848 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
853 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
855 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
861 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
862 .get_head = pci_sun4v_get_head,
863 .dequeue_msi = pci_sun4v_dequeue_msi,
864 .set_head = pci_sun4v_set_head,
865 .msi_setup = pci_sun4v_msi_setup,
866 .msi_teardown = pci_sun4v_msi_teardown,
867 .msiq_alloc = pci_sun4v_msiq_alloc,
868 .msiq_free = pci_sun4v_msiq_free,
869 .msiq_build_irq = pci_sun4v_msiq_build_irq,
872 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
874 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
876 #else /* CONFIG_PCI_MSI */
877 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
880 #endif /* !(CONFIG_PCI_MSI) */
882 static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
883 struct platform_device *op, u32 devhandle)
885 struct device_node *dp = op->dev.of_node;
888 pbm->numa_node = of_node_to_nid(dp);
890 pbm->pci_ops = &sun4v_pci_ops;
891 pbm->config_space_reg_bits = 12;
893 pbm->index = pci_num_pbms++;
897 pbm->devhandle = devhandle;
899 pbm->name = dp->full_name;
901 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
902 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
904 pci_determine_mem_io_space(pbm);
906 pci_get_pbm_props(pbm);
908 err = pci_sun4v_iommu_init(pbm);
912 pci_sun4v_msi_init(pbm);
914 pci_sun4v_scan_bus(pbm, &op->dev);
916 pbm->next = pci_pbm_root;
922 static int __devinit pci_sun4v_probe(struct platform_device *op)
924 const struct linux_prom64_registers *regs;
925 static int hvapi_negotiated = 0;
926 struct pci_pbm_info *pbm;
927 struct device_node *dp;
932 dp = op->dev.of_node;
934 if (!hvapi_negotiated++) {
935 err = sun4v_hvapi_register(HV_GRP_PCI,
940 printk(KERN_ERR PFX "Could not register hvapi, "
944 printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n",
945 vpci_major, vpci_minor);
947 dma_ops = &sun4v_dma_ops;
950 regs = of_get_property(dp, "reg", NULL);
953 printk(KERN_ERR PFX "Could not find config registers\n");
956 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
959 if (!iommu_batch_initialized) {
960 for_each_possible_cpu(i) {
961 unsigned long page = get_zeroed_page(GFP_KERNEL);
966 per_cpu(iommu_batch, i).pglist = (u64 *) page;
968 iommu_batch_initialized = 1;
971 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
973 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
977 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
979 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
980 goto out_free_controller;
985 err = pci_sun4v_pbm_init(pbm, op, devhandle);
989 dev_set_drvdata(&op->dev, pbm);
1003 static const struct of_device_id pci_sun4v_match[] = {
1006 .compatible = "SUNW,sun4v-pci",
1011 static struct platform_driver pci_sun4v_driver = {
1013 .name = DRIVER_NAME,
1014 .owner = THIS_MODULE,
1015 .of_match_table = pci_sun4v_match,
1017 .probe = pci_sun4v_probe,
1020 static int __init pci_sun4v_init(void)
1022 return platform_driver_register(&pci_sun4v_driver);
1025 subsys_initcall(pci_sun4v_init);