arch/sparc/kernel/time_32.c

   1 /* linux/arch/sparc/kernel/time.c
   2  *
   3  * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
   5  *
   6  * Chris Davis (cdavis@cois.on.ca) 03/27/1998
   7  * Added support for the intersil on the sun4/4200
   8  *
   9  * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
  10  * Support for MicroSPARC-IIep, PCI CPU.
  11  *
  12  * This file handles the Sparc specific time handling details.
  13  *
  14  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
  15  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  16  */
  17 #include <linux/errno.h>
  18 #include <linux/module.h>
  19 #include <linux/sched.h>
  20 #include <linux/kernel.h>
  21 #include <linux/param.h>
  22 #include <linux/string.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/time.h>
  26 #include <linux/rtc/m48t59.h>
  27 #include <linux/timex.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/ioport.h>
  33 #include <linux/profile.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/platform_device.h>
  37
  38 #include <asm/mc146818rtc.h>
  39 #include <asm/oplib.h>
  40 #include <asm/timex.h>
  41 #include <asm/timer.h>
  42 #include <asm/irq.h>
  43 #include <asm/io.h>
  44 #include <asm/idprom.h>
  45 #include <asm/page.h>
  46 #include <asm/pcic.h>
  47 #include <asm/irq_regs.h>
  48 #include <asm/setup.h>
  49
  50 #include "kernel.h"
  51 #include "irq.h"
  52
  53 static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
  54 static __volatile__ u64 timer_cs_internal_counter = 0;
  55 static char timer_cs_enabled = 0;
  56
  57 static struct clock_event_device timer_ce;
  58 static char timer_ce_enabled = 0;
  59
  60 #ifdef CONFIG_SMP
  61 DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
  62 #endif
  63
  64 DEFINE_SPINLOCK(rtc_lock);
  65 EXPORT_SYMBOL(rtc_lock);
  66
  67 unsigned long profile_pc(struct pt_regs *regs)
  68 {
  69         extern char __copy_user_begin[], __copy_user_end[];
  70         extern char __bzero_begin[], __bzero_end[];
  71
  72         unsigned long pc = regs->pc;
  73
  74         if (in_lock_functions(pc) ||
  75             (pc >= (unsigned long) __copy_user_begin &&
  76              pc < (unsigned long) __copy_user_end) ||
  77             (pc >= (unsigned long) __bzero_begin &&
  78              pc < (unsigned long) __bzero_end))
  79                 pc = regs->u_regs[UREG_RETPC];
  80         return pc;
  81 }
  82
  83 EXPORT_SYMBOL(profile_pc);
  84
  85 volatile u32 __iomem *master_l10_counter;
  86
  87 irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
  88 {
  89         if (timer_cs_enabled) {
  90                 write_seqlock(&timer_cs_lock);
  91                 timer_cs_internal_counter++;
  92                 sparc_config.clear_clock_irq();
  93                 write_sequnlock(&timer_cs_lock);
  94         } else {
  95                 sparc_config.clear_clock_irq();
  96         }
  97
  98         if (timer_ce_enabled)
  99                 timer_ce.event_handler(&timer_ce);
 100
 101         return IRQ_HANDLED;
 102 }
 103
 104 static void timer_ce_set_mode(enum clock_event_mode mode,
 105                               struct clock_event_device *evt)
 106 {
 107         switch (mode) {
 108                 case CLOCK_EVT_MODE_PERIODIC:
 109                 case CLOCK_EVT_MODE_RESUME:
 110                         timer_ce_enabled = 1;
 111                         break;
 112                 case CLOCK_EVT_MODE_SHUTDOWN:
 113                         timer_ce_enabled = 0;
 114                         break;
 115                 default:
 116                         break;
 117         }
 118         smp_mb();
 119 }
 120
 121 static __init void setup_timer_ce(void)
 122 {
 123         struct clock_event_device *ce = &timer_ce;
 124
 125         BUG_ON(smp_processor_id() != boot_cpu_id);
 126
 127         ce->name     = "timer_ce";
 128         ce->rating   = 100;
 129         ce->features = CLOCK_EVT_FEAT_PERIODIC;
 130         ce->set_mode = timer_ce_set_mode;
 131         ce->cpumask  = cpu_possible_mask;
 132         ce->shift    = 32;
 133         ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
 134                               ce->shift);
 135         clockevents_register_device(ce);
 136 }
 137
 138 static unsigned int sbus_cycles_offset(void)
 139 {
 140         u32 val, offset;
 141
 142         val = sbus_readl(master_l10_counter);
 143         offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
 144
 145         /* Limit hit? */
 146         if (val & TIMER_LIMIT_BIT)
 147                 offset += sparc_config.cs_period;
 148
 149         return offset;
 150 }
 151
 152 static cycle_t timer_cs_read(struct clocksource *cs)
 153 {
 154         unsigned int seq, offset;
 155         u64 cycles;
 156
 157         do {
 158                 seq = read_seqbegin(&timer_cs_lock);
 159
 160                 cycles = timer_cs_internal_counter;
 161                 offset = sparc_config.get_cycles_offset();
 162         } while (read_seqretry(&timer_cs_lock, seq));
 163
 164         /* Count absolute cycles */
 165         cycles *= sparc_config.cs_period;
 166         cycles += offset;
 167
 168         return cycles;
 169 }
 170
 171 static struct clocksource timer_cs = {
 172         .name   = "timer_cs",
 173         .rating = 100,
 174         .read   = timer_cs_read,
 175         .mask   = CLOCKSOURCE_MASK(64),
 176         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 177 };
 178
 179 static __init int setup_timer_cs(void)
 180 {
 181         timer_cs_enabled = 1;
 182         return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
 183 }
 184
 185 #ifdef CONFIG_SMP
 186 static void percpu_ce_setup(enum clock_event_mode mode,
 187                         struct clock_event_device *evt)
 188 {
 189         int cpu = cpumask_first(evt->cpumask);
 190
 191         switch (mode) {
 192                 case CLOCK_EVT_MODE_PERIODIC:
 193                         sparc_config.load_profile_irq(cpu,
 194                                                       SBUS_CLOCK_RATE / HZ);
 195                         break;
 196                 case CLOCK_EVT_MODE_ONESHOT:
 197                 case CLOCK_EVT_MODE_SHUTDOWN:
 198                 case CLOCK_EVT_MODE_UNUSED:
 199                         sparc_config.load_profile_irq(cpu, 0);
 200                         break;
 201                 default:
 202                         break;
 203         }
 204 }
 205
 206 static int percpu_ce_set_next_event(unsigned long delta,
 207                                     struct clock_event_device *evt)
 208 {
 209         int cpu = cpumask_first(evt->cpumask);
 210         unsigned int next = (unsigned int)delta;
 211
 212         sparc_config.load_profile_irq(cpu, next);
 213         return 0;
 214 }
 215
 216 void register_percpu_ce(int cpu)
 217 {
 218         struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
 219         unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
 220
 221         if (sparc_config.features & FEAT_L14_ONESHOT)
 222                 features |= CLOCK_EVT_FEAT_ONESHOT;
 223
 224         ce->name           = "percpu_ce";
 225         ce->rating         = 200;
 226         ce->features       = features;
 227         ce->set_mode       = percpu_ce_setup;
 228         ce->set_next_event = percpu_ce_set_next_event;
 229         ce->cpumask        = cpumask_of(cpu);
 230         ce->shift          = 32;
 231         ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
 232                                     ce->shift);
 233         ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
 234         ce->min_delta_ns   = clockevent_delta2ns(100, ce);
 235
 236         clockevents_register_device(ce);
 237 }
 238 #endif
 239
 240 static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
 241 {
 242         struct platform_device *pdev = to_platform_device(dev);
 243         struct m48t59_plat_data *pdata = pdev->dev.platform_data;
 244
 245         return readb(pdata->ioaddr + ofs);
 246 }
 247
 248 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
 249 {
 250         struct platform_device *pdev = to_platform_device(dev);
 251         struct m48t59_plat_data *pdata = pdev->dev.platform_data;
 252
 253         writeb(val, pdata->ioaddr + ofs);
 254 }
 255
 256 static struct m48t59_plat_data m48t59_data = {
 257         .read_byte = mostek_read_byte,
 258         .write_byte = mostek_write_byte,
 259 };
 260
 261 /* resource is set at runtime */
 262 static struct platform_device m48t59_rtc = {
 263         .name           = "rtc-m48t59",
 264         .id             = 0,
 265         .num_resources  = 1,
 266         .dev    = {
 267                 .platform_data = &m48t59_data,
 268         },
 269 };
 270
 271 static int clock_probe(struct platform_device *op)
 272 {
 273         struct device_node *dp = op->dev.of_node;
 274         const char *model = of_get_property(dp, "model", NULL);
 275
 276         if (!model)
 277                 return -ENODEV;
 278
 279         /* Only the primary RTC has an address property */
 280         if (!of_find_property(dp, "address", NULL))
 281                 return -ENODEV;
 282
 283         m48t59_rtc.resource = &op->resource[0];
 284         if (!strcmp(model, "mk48t02")) {
 285                 /* Map the clock register io area read-only */
 286                 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
 287                                                 2048, "rtc-m48t59");
 288                 m48t59_data.type = M48T59RTC_TYPE_M48T02;
 289         } else if (!strcmp(model, "mk48t08")) {
 290                 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
 291                                                 8192, "rtc-m48t59");
 292                 m48t59_data.type = M48T59RTC_TYPE_M48T08;
 293         } else
 294                 return -ENODEV;
 295
 296         if (platform_device_register(&m48t59_rtc) < 0)
 297                 printk(KERN_ERR "Registering RTC device failed\n");
 298
 299         return 0;
 300 }
 301
 302 static struct of_device_id clock_match[] = {
 303         {
 304                 .name = "eeprom",
 305         },
 306         {},
 307 };
 308
 309 static struct platform_driver clock_driver = {
 310         .probe          = clock_probe,
 311         .driver = {
 312                 .name = "rtc",
 313                 .of_match_table = clock_match,
 314         },
 315 };
 316
 317
 318 /* Probe for the mostek real time clock chip. */
 319 static int __init clock_init(void)
 320 {
 321         return platform_driver_register(&clock_driver);
 322 }
 323 /* Must be after subsys_initcall() so that busses are probed.  Must
 324  * be before device_initcall() because things like the RTC driver
 325  * need to see the clock registers.
 326  */
 327 fs_initcall(clock_init);
 328
 329 static void __init sparc32_late_time_init(void)
 330 {
 331         if (sparc_config.features & FEAT_L10_CLOCKEVENT)
 332                 setup_timer_ce();
 333         if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
 334                 setup_timer_cs();
 335 #ifdef CONFIG_SMP
 336         register_percpu_ce(smp_processor_id());
 337 #endif
 338 }
 339
 340 static void __init sbus_time_init(void)
 341 {
 342         sparc_config.get_cycles_offset = sbus_cycles_offset;
 343         sparc_config.init_timers();
 344 }
 345
 346 void __init time_init(void)
 347 {
 348         sparc_config.features = 0;
 349         late_time_init = sparc32_late_time_init;
 350
 351         if (pcic_present())
 352                 pci_time_init();
 353         else
 354                 sbus_time_init();
 355 }
 356