1 /* visemul.c: Emulation of VIS instructions.
3 * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
5 #include <linux/kernel.h>
6 #include <linux/errno.h>
7 #include <linux/thread_info.h>
8 #include <linux/perf_event.h>
10 #include <asm/ptrace.h>
11 #include <asm/pstate.h>
12 #include <asm/fpumacro.h>
13 #include <asm/uaccess.h>
14 #include <asm/cacheflush.h>
16 /* OPF field of various VIS instructions. */
18 /* 000111011 - four 16-bit packs */
19 #define FPACK16_OPF 0x03b
21 /* 000111010 - two 32-bit packs */
22 #define FPACK32_OPF 0x03a
24 /* 000111101 - four 16-bit packs */
25 #define FPACKFIX_OPF 0x03d
27 /* 001001101 - four 16-bit expands */
28 #define FEXPAND_OPF 0x04d
30 /* 001001011 - two 32-bit merges */
31 #define FPMERGE_OPF 0x04b
33 /* 000110001 - 8-by-16-bit partitoned product */
34 #define FMUL8x16_OPF 0x031
36 /* 000110011 - 8-by-16-bit upper alpha partitioned product */
37 #define FMUL8x16AU_OPF 0x033
39 /* 000110101 - 8-by-16-bit lower alpha partitioned product */
40 #define FMUL8x16AL_OPF 0x035
42 /* 000110110 - upper 8-by-16-bit partitioned product */
43 #define FMUL8SUx16_OPF 0x036
45 /* 000110111 - lower 8-by-16-bit partitioned product */
46 #define FMUL8ULx16_OPF 0x037
48 /* 000111000 - upper 8-by-16-bit partitioned product */
49 #define FMULD8SUx16_OPF 0x038
51 /* 000111001 - lower unsigned 8-by-16-bit partitioned product */
52 #define FMULD8ULx16_OPF 0x039
54 /* 000101000 - four 16-bit compare; set rd if src1 > src2 */
55 #define FCMPGT16_OPF 0x028
57 /* 000101100 - two 32-bit compare; set rd if src1 > src2 */
58 #define FCMPGT32_OPF 0x02c
60 /* 000100000 - four 16-bit compare; set rd if src1 <= src2 */
61 #define FCMPLE16_OPF 0x020
63 /* 000100100 - two 32-bit compare; set rd if src1 <= src2 */
64 #define FCMPLE32_OPF 0x024
66 /* 000100010 - four 16-bit compare; set rd if src1 != src2 */
67 #define FCMPNE16_OPF 0x022
69 /* 000100110 - two 32-bit compare; set rd if src1 != src2 */
70 #define FCMPNE32_OPF 0x026
72 /* 000101010 - four 16-bit compare; set rd if src1 == src2 */
73 #define FCMPEQ16_OPF 0x02a
75 /* 000101110 - two 32-bit compare; set rd if src1 == src2 */
76 #define FCMPEQ32_OPF 0x02e
78 /* 000000000 - Eight 8-bit edge boundary processing */
79 #define EDGE8_OPF 0x000
81 /* 000000001 - Eight 8-bit edge boundary processing, no CC */
82 #define EDGE8N_OPF 0x001
84 /* 000000010 - Eight 8-bit edge boundary processing, little-endian */
85 #define EDGE8L_OPF 0x002
87 /* 000000011 - Eight 8-bit edge boundary processing, little-endian, no CC */
88 #define EDGE8LN_OPF 0x003
90 /* 000000100 - Four 16-bit edge boundary processing */
91 #define EDGE16_OPF 0x004
93 /* 000000101 - Four 16-bit edge boundary processing, no CC */
94 #define EDGE16N_OPF 0x005
96 /* 000000110 - Four 16-bit edge boundary processing, little-endian */
97 #define EDGE16L_OPF 0x006
99 /* 000000111 - Four 16-bit edge boundary processing, little-endian, no CC */
100 #define EDGE16LN_OPF 0x007
102 /* 000001000 - Two 32-bit edge boundary processing */
103 #define EDGE32_OPF 0x008
105 /* 000001001 - Two 32-bit edge boundary processing, no CC */
106 #define EDGE32N_OPF 0x009
108 /* 000001010 - Two 32-bit edge boundary processing, little-endian */
109 #define EDGE32L_OPF 0x00a
111 /* 000001011 - Two 32-bit edge boundary processing, little-endian, no CC */
112 #define EDGE32LN_OPF 0x00b
114 /* 000111110 - distance between 8 8-bit components */
115 #define PDIST_OPF 0x03e
117 /* 000010000 - convert 8-bit 3-D address to blocked byte address */
118 #define ARRAY8_OPF 0x010
120 /* 000010010 - convert 16-bit 3-D address to blocked byte address */
121 #define ARRAY16_OPF 0x012
123 /* 000010100 - convert 32-bit 3-D address to blocked byte address */
124 #define ARRAY32_OPF 0x014
126 /* 000011001 - Set the GSR.MASK field in preparation for a BSHUFFLE */
127 #define BMASK_OPF 0x019
129 /* 001001100 - Permute bytes as specified by GSR.MASK */
130 #define BSHUFFLE_OPF 0x04c
132 #define VIS_OPF_SHIFT 5
133 #define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT)
135 #define RS1(INSN) (((INSN) >> 14) & 0x1f)
136 #define RS2(INSN) (((INSN) >> 0) & 0x1f)
137 #define RD(INSN) (((INSN) >> 25) & 0x1f)
139 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
140 unsigned int rd, int from_kernel)
142 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) {
143 if (from_kernel != 0)
144 __asm__ __volatile__("flushw");
150 static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
155 return (!reg ? 0 : regs->u_regs[reg]);
156 if (regs->tstate & TSTATE_PRIV) {
157 struct reg_window *win;
158 win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
159 value = win->locals[reg - 16];
160 } else if (test_thread_flag(TIF_32BIT)) {
161 struct reg_window32 __user *win32;
162 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
163 get_user(value, &win32->locals[reg - 16]);
165 struct reg_window __user *win;
166 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
167 get_user(value, &win->locals[reg - 16]);
172 static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg,
173 struct pt_regs *regs)
176 BUG_ON(regs->tstate & TSTATE_PRIV);
178 if (test_thread_flag(TIF_32BIT)) {
179 struct reg_window32 __user *win32;
180 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
181 return (unsigned long __user *)&win32->locals[reg - 16];
183 struct reg_window __user *win;
184 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
185 return &win->locals[reg - 16];
189 static inline unsigned long *__fetch_reg_addr_kern(unsigned int reg,
190 struct pt_regs *regs)
193 BUG_ON(regs->tstate & TSTATE_PRIV);
195 return ®s->u_regs[reg];
198 static void store_reg(struct pt_regs *regs, unsigned long val, unsigned long rd)
201 unsigned long *rd_kern = __fetch_reg_addr_kern(rd, regs);
205 unsigned long __user *rd_user = __fetch_reg_addr_user(rd, regs);
207 if (test_thread_flag(TIF_32BIT))
208 __put_user((u32)val, (u32 __user *)rd_user);
210 __put_user(val, rd_user);
214 static inline unsigned long fpd_regval(struct fpustate *f,
215 unsigned int insn_regnum)
217 insn_regnum = (((insn_regnum & 1) << 5) |
218 (insn_regnum & 0x1e));
220 return *(unsigned long *) &f->regs[insn_regnum];
223 static inline unsigned long *fpd_regaddr(struct fpustate *f,
224 unsigned int insn_regnum)
226 insn_regnum = (((insn_regnum & 1) << 5) |
227 (insn_regnum & 0x1e));
229 return (unsigned long *) &f->regs[insn_regnum];
232 static inline unsigned int fps_regval(struct fpustate *f,
233 unsigned int insn_regnum)
235 return f->regs[insn_regnum];
238 static inline unsigned int *fps_regaddr(struct fpustate *f,
239 unsigned int insn_regnum)
241 return &f->regs[insn_regnum];
247 static struct edge_tab edge8_tab[8] = {
257 static struct edge_tab edge8_tab_l[8] = {
267 static struct edge_tab edge16_tab[4] = {
273 static struct edge_tab edge16_tab_l[4] = {
279 static struct edge_tab edge32_tab[2] = {
283 static struct edge_tab edge32_tab_l[2] = {
288 static void edge(struct pt_regs *regs, unsigned int insn, unsigned int opf)
290 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val;
293 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
294 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs);
295 orig_rs2 = rs2 = fetch_reg(RS2(insn), regs);
297 if (test_thread_flag(TIF_32BIT)) {
298 rs1 = rs1 & 0xffffffff;
299 rs2 = rs2 & 0xffffffff;
305 left = edge8_tab[rs1 & 0x7].left;
306 right = edge8_tab[rs2 & 0x7].right;
310 left = edge8_tab_l[rs1 & 0x7].left;
311 right = edge8_tab_l[rs2 & 0x7].right;
316 left = edge16_tab[(rs1 >> 1) & 0x3].left;
317 right = edge16_tab[(rs2 >> 1) & 0x3].right;
322 left = edge16_tab_l[(rs1 >> 1) & 0x3].left;
323 right = edge16_tab_l[(rs2 >> 1) & 0x3].right;
328 left = edge32_tab[(rs1 >> 2) & 0x1].left;
329 right = edge32_tab[(rs2 >> 2) & 0x1].right;
334 left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
335 right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
339 if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
340 rd_val = right & left;
344 store_reg(regs, rd_val, RD(insn));
353 unsigned long ccr, tstate;
355 __asm__ __volatile__("subcc %1, %2, %%g0\n\t"
358 : "r" (orig_rs1), "r" (orig_rs2)
360 tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
361 regs->tstate = tstate | (ccr << 32UL);
366 static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
368 unsigned long rs1, rs2, rd_val;
369 unsigned int bits, bits_mask;
371 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
372 rs1 = fetch_reg(RS1(insn), regs);
373 rs2 = fetch_reg(RS2(insn), regs);
375 bits = (rs2 > 5 ? 5 : rs2);
376 bits_mask = (1UL << bits) - 1UL;
378 rd_val = ((((rs1 >> 11) & 0x3) << 0) |
379 (((rs1 >> 33) & 0x3) << 2) |
380 (((rs1 >> 55) & 0x1) << 4) |
381 (((rs1 >> 13) & 0xf) << 5) |
382 (((rs1 >> 35) & 0xf) << 9) |
383 (((rs1 >> 56) & 0xf) << 13) |
384 (((rs1 >> 17) & bits_mask) << 17) |
385 (((rs1 >> 39) & bits_mask) << (17 + bits)) |
386 (((rs1 >> 60) & 0xf) << (17 + (2*bits))));
397 store_reg(regs, rd_val, RD(insn));
400 static void bmask(struct pt_regs *regs, unsigned int insn)
402 unsigned long rs1, rs2, rd_val, gsr;
404 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
405 rs1 = fetch_reg(RS1(insn), regs);
406 rs2 = fetch_reg(RS2(insn), regs);
409 store_reg(regs, rd_val, RD(insn));
411 gsr = current_thread_info()->gsr[0] & 0xffffffff;
412 gsr |= rd_val << 32UL;
413 current_thread_info()->gsr[0] = gsr;
416 static void bshuffle(struct pt_regs *regs, unsigned int insn)
418 struct fpustate *f = FPUSTATE;
419 unsigned long rs1, rs2, rd_val;
420 unsigned long bmask, i;
422 bmask = current_thread_info()->gsr[0] >> 32UL;
424 rs1 = fpd_regval(f, RS1(insn));
425 rs2 = fpd_regval(f, RS2(insn));
428 for (i = 0; i < 8; i++) {
429 unsigned long which = (bmask >> (i * 4)) & 0xf;
433 byte = (rs1 >> (which * 8)) & 0xff;
435 byte = (rs2 >> ((which-8)*8)) & 0xff;
436 rd_val |= (byte << (i * 8));
439 *fpd_regaddr(f, RD(insn)) = rd_val;
442 static void pdist(struct pt_regs *regs, unsigned int insn)
444 struct fpustate *f = FPUSTATE;
445 unsigned long rs1, rs2, *rd, rd_val;
448 rs1 = fpd_regval(f, RS1(insn));
449 rs2 = fpd_regval(f, RS2(insn));
450 rd = fpd_regaddr(f, RD(insn));
454 for (i = 0; i < 8; i++) {
457 s1 = (rs1 >> (56 - (i * 8))) & 0xff;
458 s2 = (rs2 >> (56 - (i * 8))) & 0xff;
460 /* Absolute value of difference. */
471 static void pformat(struct pt_regs *regs, unsigned int insn, unsigned int opf)
473 struct fpustate *f = FPUSTATE;
474 unsigned long rs1, rs2, gsr, scale, rd_val;
476 gsr = current_thread_info()->gsr[0];
477 scale = (gsr >> 3) & (opf == FPACK16_OPF ? 0xf : 0x1f);
482 rs2 = fpd_regval(f, RS2(insn));
484 for (byte = 0; byte < 4; byte++) {
486 s16 src = (rs2 >> (byte * 16UL)) & 0xffffUL;
487 int scaled = src << scale;
488 int from_fixed = scaled >> 7;
490 val = ((from_fixed < 0) ?
495 rd_val |= (val << (8 * byte));
497 *fps_regaddr(f, RD(insn)) = rd_val;
504 rs1 = fpd_regval(f, RS1(insn));
505 rs2 = fpd_regval(f, RS2(insn));
506 rd_val = (rs1 << 8) & ~(0x000000ff000000ffUL);
507 for (word = 0; word < 2; word++) {
509 s32 src = (rs2 >> (word * 32UL));
510 s64 scaled = src << scale;
511 s64 from_fixed = scaled >> 23;
513 val = ((from_fixed < 0) ?
518 rd_val |= (val << (32 * word));
520 *fpd_regaddr(f, RD(insn)) = rd_val;
527 rs2 = fpd_regval(f, RS2(insn));
530 for (word = 0; word < 2; word++) {
532 s32 src = (rs2 >> (word * 32UL));
533 s64 scaled = src << scale;
534 s64 from_fixed = scaled >> 16;
536 val = ((from_fixed < -32768) ?
538 (from_fixed > 32767) ?
541 rd_val |= ((val & 0xffff) << (word * 16));
543 *fps_regaddr(f, RD(insn)) = rd_val;
550 rs2 = fps_regval(f, RS2(insn));
553 for (byte = 0; byte < 4; byte++) {
555 u8 src = (rs2 >> (byte * 8)) & 0xff;
559 rd_val |= (val << (byte * 16));
561 *fpd_regaddr(f, RD(insn)) = rd_val;
566 rs1 = fps_regval(f, RS1(insn));
567 rs2 = fps_regval(f, RS2(insn));
569 rd_val = (((rs2 & 0x000000ff) << 0) |
570 ((rs1 & 0x000000ff) << 8) |
571 ((rs2 & 0x0000ff00) << 8) |
572 ((rs1 & 0x0000ff00) << 16) |
573 ((rs2 & 0x00ff0000) << 16) |
574 ((rs1 & 0x00ff0000) << 24) |
575 ((rs2 & 0xff000000) << 24) |
576 ((rs1 & 0xff000000) << 32));
577 *fpd_regaddr(f, RD(insn)) = rd_val;
583 static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
585 struct fpustate *f = FPUSTATE;
586 unsigned long rs1, rs2, rd_val;
592 rs1 = fps_regval(f, RS1(insn));
593 rs2 = fpd_regval(f, RS2(insn));
596 for (byte = 0; byte < 4; byte++) {
597 u16 src1 = (rs1 >> (byte * 8)) & 0x00ff;
598 s16 src2 = (rs2 >> (byte * 16)) & 0xffff;
599 u32 prod = src1 * src2;
600 u16 scaled = ((prod & 0x00ffff00) >> 8);
605 rd_val |= ((scaled & 0xffffUL) << (byte * 16UL));
608 *fpd_regaddr(f, RD(insn)) = rd_val;
613 case FMUL8x16AL_OPF: {
617 rs1 = fps_regval(f, RS1(insn));
618 rs2 = fps_regval(f, RS2(insn));
621 src2 = rs2 >> (opf == FMUL8x16AU_OPF ? 16 : 0);
622 for (byte = 0; byte < 4; byte++) {
623 u16 src1 = (rs1 >> (byte * 8)) & 0x00ff;
624 u32 prod = src1 * src2;
625 u16 scaled = ((prod & 0x00ffff00) >> 8);
630 rd_val |= ((scaled & 0xffffUL) << (byte * 16UL));
633 *fpd_regaddr(f, RD(insn)) = rd_val;
638 case FMUL8ULx16_OPF: {
639 unsigned long byte, ushift;
641 rs1 = fpd_regval(f, RS1(insn));
642 rs2 = fpd_regval(f, RS2(insn));
645 ushift = (opf == FMUL8SUx16_OPF) ? 8 : 0;
646 for (byte = 0; byte < 4; byte++) {
652 src1 = ((rs1 >> ((16 * byte) + ushift)) & 0x00ff);
653 src2 = ((rs2 >> (16 * byte)) & 0xffff);
655 scaled = ((prod & 0x00ffff00) >> 8);
660 rd_val |= ((scaled & 0xffffUL) << (byte * 16UL));
663 *fpd_regaddr(f, RD(insn)) = rd_val;
667 case FMULD8SUx16_OPF:
668 case FMULD8ULx16_OPF: {
669 unsigned long byte, ushift;
671 rs1 = fps_regval(f, RS1(insn));
672 rs2 = fps_regval(f, RS2(insn));
675 ushift = (opf == FMULD8SUx16_OPF) ? 8 : 0;
676 for (byte = 0; byte < 2; byte++) {
682 src1 = ((rs1 >> ((16 * byte) + ushift)) & 0x00ff);
683 src2 = ((rs2 >> (16 * byte)) & 0xffff);
685 scaled = ((prod & 0x00ffff00) >> 8);
690 rd_val |= ((scaled & 0xffffUL) <<
691 ((byte * 32UL) + 7UL));
693 *fpd_regaddr(f, RD(insn)) = rd_val;
699 static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
701 struct fpustate *f = FPUSTATE;
702 unsigned long rs1, rs2, rd_val, i;
704 rs1 = fpd_regval(f, RS1(insn));
705 rs2 = fpd_regval(f, RS2(insn));
711 for (i = 0; i < 4; i++) {
712 s16 a = (rs1 >> (i * 16)) & 0xffff;
713 s16 b = (rs2 >> (i * 16)) & 0xffff;
721 for (i = 0; i < 2; i++) {
722 s32 a = (rs1 >> (i * 32)) & 0xffffffff;
723 s32 b = (rs2 >> (i * 32)) & 0xffffffff;
731 for (i = 0; i < 4; i++) {
732 s16 a = (rs1 >> (i * 16)) & 0xffff;
733 s16 b = (rs2 >> (i * 16)) & 0xffff;
741 for (i = 0; i < 2; i++) {
742 s32 a = (rs1 >> (i * 32)) & 0xffffffff;
743 s32 b = (rs2 >> (i * 32)) & 0xffffffff;
751 for (i = 0; i < 4; i++) {
752 s16 a = (rs1 >> (i * 16)) & 0xffff;
753 s16 b = (rs2 >> (i * 16)) & 0xffff;
761 for (i = 0; i < 2; i++) {
762 s32 a = (rs1 >> (i * 32)) & 0xffffffff;
763 s32 b = (rs2 >> (i * 32)) & 0xffffffff;
771 for (i = 0; i < 4; i++) {
772 s16 a = (rs1 >> (i * 16)) & 0xffff;
773 s16 b = (rs2 >> (i * 16)) & 0xffff;
781 for (i = 0; i < 2; i++) {
782 s32 a = (rs1 >> (i * 32)) & 0xffffffff;
783 s32 b = (rs2 >> (i * 32)) & 0xffffffff;
791 maybe_flush_windows(0, 0, RD(insn), 0);
792 store_reg(regs, rd_val, RD(insn));
795 /* Emulate the VIS instructions which are not implemented in
796 * hardware on Niagara.
798 int vis_emul(struct pt_regs *regs, unsigned int insn)
800 unsigned long pc = regs->tpc;
803 BUG_ON(regs->tstate & TSTATE_PRIV);
805 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
807 if (test_thread_flag(TIF_32BIT))
810 if (get_user(insn, (u32 __user *) pc))
813 save_and_clear_fpu();
815 opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT;
820 /* Pixel Formatting Instructions. */
826 pformat(regs, insn, opf);
829 /* Partitioned Multiply Instructions */
835 case FMULD8SUx16_OPF:
836 case FMULD8ULx16_OPF:
837 pmul(regs, insn, opf);
840 /* Pixel Compare Instructions */
849 pcmp(regs, insn, opf);
852 /* Edge Handling Instructions */
865 edge(regs, insn, opf);
868 /* Pixel Component Distance */
873 /* Three-Dimensional Array Addressing Instructions */
877 array(regs, insn, opf);
880 /* Byte Mask and Shuffle Instructions */
886 bshuffle(regs, insn);
890 regs->tpc = regs->tnpc;