1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/atomic.h>
28 #include <asm/system.h>
32 #include <asm/iommu.h>
34 #include <asm/oplib.h>
35 #include <asm/timer.h>
37 #include <asm/starfire.h>
38 #include <asm/uaccess.h>
39 #include <asm/cache.h>
40 #include <asm/cpudata.h>
41 #include <asm/auxio.h>
45 static void distribute_irqs(void);
48 /* UPA nodes send interrupt packet to UltraSparc with first data reg
49 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
50 * delivered. We must translate this into a non-vector IRQ so we can
51 * set the softint on this cpu.
53 * To make processing these packets efficient and race free we use
54 * an array of irq buckets below. The interrupt vector handler in
55 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
56 * The IVEC handler does not need to act atomically, the PIL dispatch
57 * code uses CAS to get an atomic snapshot of the list and clear it
61 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
63 /* This has to be in the main kernel image, it cannot be
64 * turned into per-cpu data. The reason is that the main
65 * kernel image is locked into the TLB and this structure
66 * is accessed from the vectored interrupt trap handler. If
67 * access to this structure takes a TLB miss it could cause
68 * the 5-level sparc v9 trap stack to overflow.
70 struct irq_work_struct {
71 unsigned int irq_worklists[16];
73 struct irq_work_struct __irq_work[NR_CPUS];
74 #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
76 static struct irqaction *irq_action[NR_IRQS+1];
78 /* This only synchronizes entities which modify IRQ handler
79 * state and some selected user-level spots that want to
80 * read things in the table. IRQ handler processing orders
81 * its' accesses such that no locking is needed.
83 static DEFINE_SPINLOCK(irq_action_lock);
85 static void register_irq_proc (unsigned int irq);
88 * Upper 2b of irqaction->flags holds the ino.
89 * irqaction->mask holds the smp affinity information.
91 #define put_ino_in_irqaction(action, irq) \
92 action->flags &= 0xffffffffffffUL; \
93 if (__bucket(irq) == &pil0_dummy_bucket) \
94 action->flags |= 0xdeadUL << 48; \
96 action->flags |= __irq_ino(irq) << 48;
97 #define get_ino_in_irqaction(action) (action->flags >> 48)
99 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
100 #define get_smpaff_in_irqaction(action) ((action)->mask)
102 int show_interrupts(struct seq_file *p, void *v)
105 int i = *(loff_t *) v;
106 struct irqaction *action;
111 spin_lock_irqsave(&irq_action_lock, flags);
113 if (!(action = *(i + irq_action)))
115 seq_printf(p, "%3d: ", i);
117 seq_printf(p, "%10u ", kstat_irqs(i));
119 for (j = 0; j < NR_CPUS; j++) {
122 seq_printf(p, "%10u ",
123 kstat_cpu(j).irqs[i]);
126 seq_printf(p, " %s:%lx", action->name,
127 get_ino_in_irqaction(action));
128 for (action = action->next; action; action = action->next) {
129 seq_printf(p, ", %s:%lx", action->name,
130 get_ino_in_irqaction(action));
135 spin_unlock_irqrestore(&irq_action_lock, flags);
140 /* Now these are always passed a true fully specified sun4u INO. */
141 void enable_irq(unsigned int irq)
143 struct ino_bucket *bucket = __bucket(irq);
153 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
156 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
157 if ((ver >> 32) == __JALAPENO_ID ||
158 (ver >> 32) == __SERRANO_ID) {
159 /* We set it to our JBUS ID. */
160 __asm__ __volatile__("ldxa [%%g0] %1, %0"
162 : "i" (ASI_JBUS_CONFIG));
163 tid = ((tid & (0x1fUL<<17)) << 9);
164 tid &= IMAP_TID_JBUS;
166 /* We set it to our Safari AID. */
167 __asm__ __volatile__("ldxa [%%g0] %1, %0"
169 : "i" (ASI_SAFARI_CONFIG));
170 tid = ((tid & (0x3ffUL<<17)) << 9);
171 tid &= IMAP_AID_SAFARI;
173 } else if (this_is_starfire == 0) {
174 /* We set it to our UPA MID. */
175 __asm__ __volatile__("ldxa [%%g0] %1, %0"
177 : "i" (ASI_UPA_CONFIG));
178 tid = ((tid & UPA_CONFIG_MID) << 9);
181 tid = (starfire_translate(imap, smp_processor_id()) << 26);
185 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
186 * of this SYSIO's preconfigured IGN in the SYSIO Control
187 * Register, the hardware just mirrors that value here.
188 * However for Graphics and UPA Slave devices the full
189 * IMAP_INR field can be set by the programmer here.
191 * Things like FFB can now be handled via the new IRQ mechanism.
193 upa_writel(tid | IMAP_VALID, imap);
198 /* This now gets passed true ino's as well. */
199 void disable_irq(unsigned int irq)
201 struct ino_bucket *bucket = __bucket(irq);
208 /* NOTE: We do not want to futz with the IRQ clear registers
209 * and move the state to IDLE, the SCSI code does call
210 * disable_irq() to assure atomicity in the queue cmd
211 * SCSI adapter driver code. Thus we'd lose interrupts.
213 tmp = upa_readl(imap);
215 upa_writel(tmp, imap);
219 /* The timer is the one "weird" interrupt which is generated by
220 * the CPU %tick register and not by some normal vectored interrupt
221 * source. To handle this special case, we use this dummy INO bucket.
223 static struct irq_desc pil0_dummy_desc;
224 static struct ino_bucket pil0_dummy_bucket = {
225 .irq_info = &pil0_dummy_desc,
228 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
229 unsigned long iclr, unsigned long imap,
230 struct ino_bucket *bucket)
232 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
233 "(%d:%d:%016lx:%016lx), halting...\n",
234 ino, bucket->pil, bucket->iclr, bucket->imap,
235 pil, inofixup, iclr, imap);
239 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
241 struct ino_bucket *bucket;
245 if (iclr != 0UL || imap != 0UL) {
246 prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
250 return __irq(&pil0_dummy_bucket);
253 /* RULE: Both must be specified in all other cases. */
254 if (iclr == 0UL || imap == 0UL) {
255 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
256 pil, inofixup, iclr, imap);
260 ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
261 if (ino > NUM_IVECS) {
262 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
263 ino, pil, inofixup, iclr, imap);
267 bucket = &ivector_table[ino];
268 if (bucket->flags & IBF_ACTIVE)
269 build_irq_error("IRQ: Trying to build active INO bucket.\n",
270 ino, pil, inofixup, iclr, imap, bucket);
272 if (bucket->irq_info) {
273 if (bucket->imap != imap || bucket->iclr != iclr)
274 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
275 ino, pil, inofixup, iclr, imap, bucket);
280 bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
281 if (!bucket->irq_info) {
282 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
285 memset(bucket->irq_info, 0, sizeof(struct irq_desc));
287 /* Ok, looks good, set it up. Don't touch the irq_chain or
296 return __irq(bucket);
299 static void atomic_bucket_insert(struct ino_bucket *bucket)
301 unsigned long pstate;
304 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
305 __asm__ __volatile__("wrpr %0, %1, %%pstate"
306 : : "r" (pstate), "i" (PSTATE_IE));
307 ent = irq_work(smp_processor_id(), bucket->pil);
308 bucket->irq_chain = *ent;
309 *ent = __irq(bucket);
310 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
313 static int check_irq_sharing(int pil, unsigned long irqflags)
315 struct irqaction *action, *tmp;
317 action = *(irq_action + pil);
319 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
320 for (tmp = action; tmp->next; tmp = tmp->next)
329 static void append_irq_action(int pil, struct irqaction *action)
331 struct irqaction **pp = irq_action + pil;
338 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
340 struct irq_desc *desc = bucket->irq_info;
344 if (bucket->flags & IBF_PCI)
345 max_irq = MAX_IRQ_DESC_ACTION;
346 for (i = 0; i < max_irq; i++) {
347 struct irqaction *p = &desc->action[i];
350 if (desc->action_active_mask & mask)
353 desc->action_active_mask |= mask;
359 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
360 unsigned long irqflags, const char *name, void *dev_id)
362 struct irqaction *action;
363 struct ino_bucket *bucket = __bucket(irq);
367 if (unlikely(!handler))
370 if (unlikely(!bucket->irq_info))
373 if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
375 * This function might sleep, we want to call it first,
376 * outside of the atomic block. In SA_STATIC_ALLOC case,
377 * random driver's kmalloc will fail, but it is safe.
378 * If already initialized, random driver will not reinit.
379 * Yes, this might clear the entropy pool if the wrong
380 * driver is attempted to be loaded, without actually
381 * installing a new handler, but is this really a problem,
382 * only the sysadmin is able to do this.
384 rand_initialize_irq(irq);
387 spin_lock_irqsave(&irq_action_lock, flags);
389 if (check_irq_sharing(bucket->pil, irqflags)) {
390 spin_unlock_irqrestore(&irq_action_lock, flags);
394 action = get_action_slot(bucket);
396 spin_unlock_irqrestore(&irq_action_lock, flags);
400 bucket->flags |= IBF_ACTIVE;
402 if (bucket != &pil0_dummy_bucket) {
403 pending = bucket->pending;
408 action->handler = handler;
409 action->flags = irqflags;
412 action->dev_id = dev_id;
413 put_ino_in_irqaction(action, irq);
414 put_smpaff_in_irqaction(action, CPU_MASK_NONE);
416 append_irq_action(bucket->pil, action);
420 /* We ate the IVEC already, this makes sure it does not get lost. */
422 atomic_bucket_insert(bucket);
423 set_softint(1 << bucket->pil);
426 spin_unlock_irqrestore(&irq_action_lock, flags);
428 if (bucket != &pil0_dummy_bucket)
429 register_irq_proc(__irq_ino(irq));
437 EXPORT_SYMBOL(request_irq);
439 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
441 struct ino_bucket *bucket = __bucket(irq);
442 struct irqaction *action, **pp;
444 pp = irq_action + bucket->pil;
446 if (unlikely(!action))
449 if (unlikely(!action->handler)) {
450 printk("Freeing free IRQ %d\n", bucket->pil);
454 while (action && action->dev_id != dev_id) {
465 void free_irq(unsigned int irq, void *dev_id)
467 struct irqaction *action;
468 struct ino_bucket *bucket;
471 spin_lock_irqsave(&irq_action_lock, flags);
473 action = unlink_irq_action(irq, dev_id);
475 spin_unlock_irqrestore(&irq_action_lock, flags);
477 if (unlikely(!action))
480 synchronize_irq(irq);
482 spin_lock_irqsave(&irq_action_lock, flags);
484 bucket = __bucket(irq);
485 if (bucket != &pil0_dummy_bucket) {
486 struct irq_desc *desc = bucket->irq_info;
487 unsigned long imap = bucket->imap;
490 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
491 struct irqaction *p = &desc->action[i];
494 desc->action_active_mask &= ~(1 << i);
499 if (!desc->action_active_mask) {
500 /* This unique interrupt source is now inactive. */
501 bucket->flags &= ~IBF_ACTIVE;
503 /* See if any other buckets share this bucket's IMAP
504 * and are still active.
506 for (ent = 0; ent < NUM_IVECS; ent++) {
507 struct ino_bucket *bp = &ivector_table[ent];
510 (bp->flags & IBF_ACTIVE) != 0)
514 /* Only disable when no other sub-irq levels of
515 * the same IMAP are active.
517 if (ent == NUM_IVECS)
522 spin_unlock_irqrestore(&irq_action_lock, flags);
525 EXPORT_SYMBOL(free_irq);
528 void synchronize_irq(unsigned int irq)
530 struct ino_bucket *bucket = __bucket(irq);
533 /* The following is how I wish I could implement this.
534 * Unfortunately the ICLR registers are read-only, you can
535 * only write ICLR_foo values to them. To get the current
536 * IRQ status you would need to get at the IRQ diag registers
537 * in the PCI/SBUS controller and the layout of those vary
538 * from one controller to the next, sigh... -DaveM
540 unsigned long iclr = bucket->iclr;
543 u32 tmp = upa_readl(iclr);
545 if (tmp == ICLR_TRANSMIT ||
546 tmp == ICLR_PENDING) {
553 /* So we have to do this with a INPROGRESS bit just like x86. */
554 while (bucket->flags & IBF_INPROGRESS)
558 #endif /* CONFIG_SMP */
560 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
562 struct irq_desc *desc = bp->irq_info;
563 unsigned char flags = bp->flags;
567 bp->flags |= IBF_INPROGRESS;
569 if (unlikely(!(flags & IBF_ACTIVE))) {
574 if (desc->pre_handler)
575 desc->pre_handler(bp,
576 desc->pre_handler_arg1,
577 desc->pre_handler_arg2);
579 action_mask = desc->action_active_mask;
581 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
582 struct irqaction *p = &desc->action[i];
585 if (!(action_mask & mask))
588 action_mask &= ~mask;
590 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
597 upa_writel(ICLR_IDLE, bp->iclr);
598 /* Test and add entropy */
599 if (random & SA_SAMPLE_RANDOM)
600 add_interrupt_randomness(irq);
603 bp->flags &= ~IBF_INPROGRESS;
606 void handler_irq(int irq, struct pt_regs *regs)
608 struct ino_bucket *bp;
609 int cpu = smp_processor_id();
613 * Check for TICK_INT on level 14 softint.
616 unsigned long clr_mask = 1 << irq;
617 unsigned long tick_mask = tick_ops->softint_mask;
619 if ((irq == 14) && (get_softint() & tick_mask)) {
621 clr_mask = tick_mask;
623 clear_softint(clr_mask);
626 clear_softint(1 << irq);
630 kstat_this_cpu.irqs[irq]++;
635 __bucket(xchg32(irq_work(cpu, irq), 0)) :
638 bp = __bucket(xchg32(irq_work(cpu, irq), 0));
641 struct ino_bucket *nbp = __bucket(bp->irq_chain);
644 process_bucket(irq, bp, regs);
650 #ifdef CONFIG_BLK_DEV_FD
651 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
653 /* XXX No easy way to include asm/floppy.h XXX */
654 extern unsigned char *pdma_vaddr;
655 extern unsigned long pdma_size;
656 extern volatile int doing_pdma;
657 extern unsigned long fdc_status;
659 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
661 if (likely(doing_pdma)) {
662 void __iomem *stat = (void __iomem *) fdc_status;
663 unsigned char *vaddr = pdma_vaddr;
664 unsigned long size = pdma_size;
669 if (unlikely(!(val & 0x80))) {
674 if (unlikely(!(val & 0x20))) {
682 *vaddr++ = readb(stat + 1);
684 unsigned char data = *vaddr++;
687 writeb(data, stat + 1);
695 /* Send Terminal Count pulse to floppy controller. */
696 val = readb(auxio_register);
697 val |= AUXIO_AUX1_FTCNT;
698 writeb(val, auxio_register);
699 val &= ~AUXIO_AUX1_FTCNT;
700 writeb(val, auxio_register);
706 return floppy_interrupt(irq, dev_cookie, regs);
708 EXPORT_SYMBOL(sparc_floppy_irq);
711 /* We really don't need these at all on the Sparc. We only have
712 * stubs here because they are exported to modules.
714 unsigned long probe_irq_on(void)
719 EXPORT_SYMBOL(probe_irq_on);
721 int probe_irq_off(unsigned long mask)
726 EXPORT_SYMBOL(probe_irq_off);
729 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
731 struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
732 unsigned long imap = bucket->imap;
735 while (!cpu_online(goal_cpu)) {
736 if (++goal_cpu >= NR_CPUS)
740 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
741 tid = goal_cpu << 26;
742 tid &= IMAP_AID_SAFARI;
743 } else if (this_is_starfire == 0) {
744 tid = goal_cpu << 26;
747 tid = (starfire_translate(imap, goal_cpu) << 26);
750 upa_writel(tid | IMAP_VALID, imap);
753 if (++goal_cpu >= NR_CPUS)
755 } while (!cpu_online(goal_cpu));
760 /* Called from request_irq. */
761 static void distribute_irqs(void)
766 spin_lock_irqsave(&irq_action_lock, flags);
770 * Skip the timer at [0], and very rare error/power intrs at [15].
771 * Also level [12], it causes problems on Ex000 systems.
773 for (level = 1; level < NR_IRQS; level++) {
774 struct irqaction *p = irq_action[level];
780 cpu = retarget_one_irq(p, cpu);
784 spin_unlock_irqrestore(&irq_action_lock, flags);
795 static struct sun5_timer *prom_timers;
796 static u64 prom_limit0, prom_limit1;
798 static void map_prom_timers(void)
800 unsigned int addr[3];
803 /* PROM timer node hangs out in the top level of device siblings... */
804 tnode = prom_finddevice("/counter-timer");
806 /* Assume if node is not present, PROM uses different tick mechanism
807 * which we should not care about.
809 if (tnode == 0 || tnode == -1) {
810 prom_timers = (struct sun5_timer *) 0;
814 /* If PROM is really using this, it must be mapped by him. */
815 err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
817 prom_printf("PROM does not have timer mapped, trying to continue.\n");
818 prom_timers = (struct sun5_timer *) 0;
821 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
824 static void kill_prom_timer(void)
829 /* Save them away for later. */
830 prom_limit0 = prom_timers->limit0;
831 prom_limit1 = prom_timers->limit1;
833 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
834 * We turn both off here just to be paranoid.
836 prom_timers->limit0 = 0;
837 prom_timers->limit1 = 0;
839 /* Wheee, eat the interrupt packet too... */
840 __asm__ __volatile__(
842 " ldxa [%%g0] %0, %%g1\n"
843 " ldxa [%%g2] %1, %%g1\n"
844 " stxa %%g0, [%%g0] %0\n"
847 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
851 void init_irqwork_curcpu(void)
853 int cpu = hard_smp_processor_id();
855 memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
858 static void __cpuinit init_one_mondo(unsigned long *pa_ptr, unsigned long type)
860 register unsigned long func __asm__("%o0");
861 register unsigned long arg0 __asm__("%o1");
862 register unsigned long arg1 __asm__("%o2");
863 register unsigned long arg2 __asm__("%o3");
864 unsigned long page = get_zeroed_page(GFP_ATOMIC);
867 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
871 *pa_ptr = __pa(page);
873 func = HV_FAST_CPU_QCONF;
876 arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */
877 __asm__ __volatile__("ta %8"
878 : "=&r" (func), "=&r" (arg0),
879 "=&r" (arg1), "=&r" (arg2)
880 : "0" (func), "1" (arg0),
881 "2" (arg1), "3" (arg2),
884 if (func != HV_EOK) {
885 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
891 static void __cpuinit init_one_kbuf(unsigned long *pa_ptr)
893 unsigned long page = get_zeroed_page(GFP_ATOMIC);
896 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
900 *pa_ptr = __pa(page);
903 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb)
908 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
910 page = get_zeroed_page(GFP_ATOMIC);
912 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
916 tb->cpu_mondo_block_pa = __pa(page);
917 tb->cpu_list_pa = __pa(page + 64);
921 /* Allocate and init the mondo and error queues for this cpu. */
922 void __cpuinit sun4v_init_mondo_queues(void)
924 int cpu = hard_smp_processor_id();
925 struct trap_per_cpu *tb = &trap_block[cpu];
927 init_one_mondo(&tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
928 init_one_mondo(&tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
930 init_one_mondo(&tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
931 init_one_kbuf(&tb->resum_kernel_buf_pa);
933 init_one_mondo(&tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
934 init_one_kbuf(&tb->nonresum_kernel_buf_pa);
936 init_cpu_send_mondo_info(tb);
939 /* Only invoked on boot processor. */
940 void __init init_IRQ(void)
944 memset(&ivector_table[0], 0, sizeof(ivector_table));
946 if (tlb_type == hypervisor)
947 sun4v_init_mondo_queues();
949 /* We need to clear any IRQ's pending in the soft interrupt
950 * registers, a spurious one could be left around from the
951 * PROM timer which we just disabled.
953 clear_softint(get_softint());
955 /* Now that ivector table is initialized, it is safe
956 * to receive IRQ vector traps. We will normally take
957 * one or two right now, in case some device PROM used
958 * to boot us wants to speak to us. We just ignore them.
960 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
961 "or %%g1, %0, %%g1\n\t"
962 "wrpr %%g1, 0x0, %%pstate"
968 static struct proc_dir_entry * root_irq_dir;
969 static struct proc_dir_entry * irq_dir [NUM_IVECS];
973 static int irq_affinity_read_proc (char *page, char **start, off_t off,
974 int count, int *eof, void *data)
976 struct ino_bucket *bp = ivector_table + (long)data;
977 struct irq_desc *desc = bp->irq_info;
978 struct irqaction *ap = desc->action;
982 mask = get_smpaff_in_irqaction(ap);
983 if (cpus_empty(mask))
984 mask = cpu_online_map;
986 len = cpumask_scnprintf(page, count, mask);
989 len += sprintf(page + len, "\n");
993 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
995 struct ino_bucket *bp = ivector_table + irq;
996 struct irq_desc *desc = bp->irq_info;
997 struct irqaction *ap = desc->action;
999 /* Users specify affinity in terms of hw cpu ids.
1000 * As soon as we do this, handler_irq() might see and take action.
1002 put_smpaff_in_irqaction(ap, hw_aff);
1004 /* Migration is simply done by the next cpu to service this
1009 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1010 unsigned long count, void *data)
1012 int irq = (long) data, full_count = count, err;
1013 cpumask_t new_value;
1015 err = cpumask_parse(buffer, count, new_value);
1018 * Do not allow disabling IRQs completely - it's a too easy
1019 * way to make the system unusable accidentally :-) At least
1020 * one online CPU still has to be targeted.
1022 cpus_and(new_value, new_value, cpu_online_map);
1023 if (cpus_empty(new_value))
1026 set_intr_affinity(irq, new_value);
1033 #define MAX_NAMELEN 10
1035 static void register_irq_proc (unsigned int irq)
1037 char name [MAX_NAMELEN];
1039 if (!root_irq_dir || irq_dir[irq])
1042 memset(name, 0, MAX_NAMELEN);
1043 sprintf(name, "%x", irq);
1045 /* create /proc/irq/1234 */
1046 irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1049 /* XXX SMP affinity not supported on starfire yet. */
1050 if (this_is_starfire == 0) {
1051 struct proc_dir_entry *entry;
1053 /* create /proc/irq/1234/smp_affinity */
1054 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1058 entry->data = (void *)(long)irq;
1059 entry->read_proc = irq_affinity_read_proc;
1060 entry->write_proc = irq_affinity_write_proc;
1066 void init_irq_proc (void)
1068 /* create /proc/irq */
1069 root_irq_dir = proc_mkdir("irq", NULL);