2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 /* Machine-generated file; do not edit. */
17 #ifndef __ARCH_MPIPE_H__
18 #define __ARCH_MPIPE_H__
21 #include <arch/mpipe_def.h>
26 * MMIO Ingress DMA Release Region Address.
27 * This is a description of the physical addresses used to manipulate ingress
28 * credit counters. Accesses to this address space should use an address of
29 * this form and a value like that specified in IDMA_RELEASE_REGION_VAL.
37 #ifndef __BIG_ENDIAN__
39 uint_reg_t __reserved_0 : 3;
40 /* NotifRing to be released */
42 /* Bucket to be released */
43 uint_reg_t bucket : 13;
44 /* Enable NotifRing release */
45 uint_reg_t ring_enable : 1;
46 /* Enable Bucket release */
47 uint_reg_t bucket_enable : 1;
49 * This field of the address selects the region (address space) to be
50 * accessed. For the iDMA release region, this field must be 4.
52 uint_reg_t region : 3;
54 uint_reg_t __reserved_1 : 6;
55 /* This field of the address indexes the 32 entry service domain table. */
56 uint_reg_t svc_dom : 5;
58 uint_reg_t __reserved_2 : 24;
59 #else /* __BIG_ENDIAN__ */
60 uint_reg_t __reserved_2 : 24;
61 uint_reg_t svc_dom : 5;
62 uint_reg_t __reserved_1 : 6;
63 uint_reg_t region : 3;
64 uint_reg_t bucket_enable : 1;
65 uint_reg_t ring_enable : 1;
66 uint_reg_t bucket : 13;
68 uint_reg_t __reserved_0 : 3;
73 } MPIPE_IDMA_RELEASE_REGION_ADDR_t;
76 * MMIO Ingress DMA Release Region Value - Release NotifRing and/or Bucket.
77 * Provides release of the associated NotifRing. The address of the MMIO
78 * operation is described in IDMA_RELEASE_REGION_ADDR.
86 #ifndef __BIG_ENDIAN__
88 * Number of packets being released. The load balancer's count of
89 * inflight packets will be decremented by this amount for the associated
90 * Bucket and/or NotifRing
92 uint_reg_t count : 16;
94 uint_reg_t __reserved : 48;
95 #else /* __BIG_ENDIAN__ */
96 uint_reg_t __reserved : 48;
97 uint_reg_t count : 16;
102 } MPIPE_IDMA_RELEASE_REGION_VAL_t;
105 * MMIO Buffer Stack Manager Region Address.
106 * This MMIO region is used for posting or fetching buffers to/from the
107 * buffer stack manager. On an MMIO load, this pops a buffer descriptor from
108 * the top of stack if one is available. On an MMIO store, this pushes a
109 * buffer to the stack. The value read or written is described in
118 #ifndef __BIG_ENDIAN__
120 uint_reg_t __reserved_0 : 3;
121 /* BufferStack being accessed. */
122 uint_reg_t stack : 5;
124 uint_reg_t __reserved_1 : 18;
126 * This field of the address selects the region (address space) to be
127 * accessed. For the buffer stack manager region, this field must be 6.
129 uint_reg_t region : 3;
131 uint_reg_t __reserved_2 : 6;
132 /* This field of the address indexes the 32 entry service domain table. */
133 uint_reg_t svc_dom : 5;
135 uint_reg_t __reserved_3 : 24;
136 #else /* __BIG_ENDIAN__ */
137 uint_reg_t __reserved_3 : 24;
138 uint_reg_t svc_dom : 5;
139 uint_reg_t __reserved_2 : 6;
140 uint_reg_t region : 3;
141 uint_reg_t __reserved_1 : 18;
142 uint_reg_t stack : 5;
143 uint_reg_t __reserved_0 : 3;
148 } MPIPE_BSM_REGION_ADDR_t;
151 * MMIO Buffer Stack Manager Region Value.
152 * This MMIO region is used for posting or fetching buffers to/from the
153 * buffer stack manager. On an MMIO load, this pops a buffer descriptor from
154 * the top of stack if one is available. On an MMIO store, this pushes a
155 * buffer to the stack. The address of the MMIO operation is described in
164 #ifndef __BIG_ENDIAN__
166 uint_reg_t __reserved_0 : 7;
168 * Base virtual address of the buffer. Must be sign extended by consumer.
172 uint_reg_t __reserved_1 : 6;
174 * Index of the buffer stack to which this buffer belongs. Ignored on
175 * writes since the offset bits specify the stack being accessed.
177 uint_reg_t stack_idx : 5;
179 uint_reg_t __reserved_2 : 3;
181 * Instance ID. For devices that support automatic buffer return between
182 * mPIPE instances, this field indicates the buffer owner. If the INST
183 * field does not match the mPIPE's instance number when a packet is
184 * egressed, buffers with HWB set will be returned to the other mPIPE
185 * instance. Note that not all devices support multi-mPIPE buffer
186 * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
187 * whether the INST field in the buffer descriptor is populated by iDMA
188 * hardware. This field is ignored on writes.
192 * Reads as one to indicate that this is a hardware managed buffer.
193 * Ignored on writes since all buffers on a given stack are the same size.
197 * Encoded size of buffer (ignored on writes):
209 * Valid indication for the buffer. Ignored on writes.
210 * 0 : Valid buffer descriptor popped from stack.
211 * 3 : Could not pop a buffer from the stack. Either the stack is empty,
212 * or the hardware's prefetch buffer is empty for this stack.
215 #else /* __BIG_ENDIAN__ */
220 uint_reg_t __reserved_2 : 3;
221 uint_reg_t stack_idx : 5;
222 uint_reg_t __reserved_1 : 6;
224 uint_reg_t __reserved_0 : 7;
229 } MPIPE_BSM_REGION_VAL_t;
232 * MMIO Egress DMA Post Region Address.
233 * Used to post descriptor locations to the eDMA descriptor engine. The
234 * value to be written is described in EDMA_POST_REGION_VAL
242 #ifndef __BIG_ENDIAN__
244 uint_reg_t __reserved_0 : 3;
245 /* eDMA ring being accessed */
248 uint_reg_t __reserved_1 : 17;
250 * This field of the address selects the region (address space) to be
251 * accessed. For the egress DMA post region, this field must be 5.
253 uint_reg_t region : 3;
255 uint_reg_t __reserved_2 : 6;
256 /* This field of the address indexes the 32 entry service domain table. */
257 uint_reg_t svc_dom : 5;
259 uint_reg_t __reserved_3 : 24;
260 #else /* __BIG_ENDIAN__ */
261 uint_reg_t __reserved_3 : 24;
262 uint_reg_t svc_dom : 5;
263 uint_reg_t __reserved_2 : 6;
264 uint_reg_t region : 3;
265 uint_reg_t __reserved_1 : 17;
267 uint_reg_t __reserved_0 : 3;
272 } MPIPE_EDMA_POST_REGION_ADDR_t;
275 * MMIO Egress DMA Post Region Value.
276 * Used to post descriptor locations to the eDMA descriptor engine. The
277 * address is described in EDMA_POST_REGION_ADDR.
285 #ifndef __BIG_ENDIAN__
287 * For writes, this specifies the current ring tail pointer prior to any
288 * post. For example, to post 1 or more descriptors starting at location
289 * 23, this would contain 23 (not 24). On writes, this index must be
290 * masked based on the ring size. The new tail pointer after this post
291 * is COUNT+RING_IDX (masked by the ring size).
293 * For reads, this provides the hardware descriptor fetcher's head
294 * pointer. The descriptors prior to the head pointer, however, may not
295 * yet have been processed so this indicator is only used to determine
296 * how full the ring is and if software may post more descriptors.
298 uint_reg_t ring_idx : 16;
300 * For writes, this specifies number of contiguous descriptors that are
301 * being posted. Software may post up to RingSize descriptors with a
302 * single MMIO store. A zero in this field on a write will "wake up" an
303 * eDMA ring and cause it fetch descriptors regardless of the hardware's
304 * current view of the state of the tail pointer.
306 * For reads, this field provides a rolling count of the number of
307 * descriptors that have been completely processed. This may be used by
308 * software to determine when buffers associated with a descriptor may be
309 * returned or reused. When the ring's flush bit is cleared by software
310 * (after having been set by HW or SW), the COUNT will be cleared.
312 uint_reg_t count : 16;
314 * For writes, this specifies the generation number of the tail being
315 * posted. Note that if tail+cnt wraps to the beginning of the ring, the
316 * eDMA hardware assumes that the descriptors posted at the beginning of
317 * the ring are also valid so it is okay to post around the wrap point.
319 * For reads, this is the current generation number. Valid descriptors
320 * will have the inverse of this generation number.
324 uint_reg_t __reserved : 31;
325 #else /* __BIG_ENDIAN__ */
326 uint_reg_t __reserved : 31;
328 uint_reg_t count : 16;
329 uint_reg_t ring_idx : 16;
334 } MPIPE_EDMA_POST_REGION_VAL_t;
337 * Load Balancer Bucket Status Data.
338 * Read/Write data for load balancer Bucket-Status Table. 4160 entries
339 * indexed by LBL_INIT_CTL.IDX when LBL_INIT_CTL.STRUCT_SEL is BSTS_TBL
347 #ifndef __BIG_ENDIAN__
348 /* NotifRing currently assigned to this bucket. */
349 uint_reg_t notifring : 8;
350 /* Current reference count. */
351 uint_reg_t count : 16;
352 /* Group associated with this bucket. */
353 uint_reg_t group : 5;
354 /* Mode select for this bucket. */
357 uint_reg_t __reserved : 32;
358 #else /* __BIG_ENDIAN__ */
359 uint_reg_t __reserved : 32;
361 uint_reg_t group : 5;
362 uint_reg_t count : 16;
363 uint_reg_t notifring : 8;
368 } MPIPE_LBL_INIT_DAT_BSTS_TBL_t;
369 #endif /* !defined(__ASSEMBLER__) */
371 #endif /* !defined(__ARCH_MPIPE_H__) */