2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 /* Machine-generated file; do not edit. */
18 #ifndef __ARCH_MPIPE_SHM_H__
19 #define __ARCH_MPIPE_SHM_H__
22 #include <arch/mpipe_shm_def.h>
26 * MPIPE eDMA Descriptor.
27 * The eDMA descriptor is written by software and consumed by hardware. It
28 * is used to specify the location of egress packet data to be sent out of
29 * the chip via one of the packet interfaces.
39 #ifndef __BIG_ENDIAN__
41 * Generation number. Used to indicate a valid descriptor in ring. When
42 * a new descriptor is written into the ring, software must toggle this
43 * bit. The net effect is that the GEN bit being written into new
44 * descriptors toggles each time the ring tail pointer wraps.
47 /** Reserved. Must be zero. */
49 /** Checksum generation enabled for this transfer. */
52 * Nothing to be sent. Used, for example, when software has dropped a
53 * packet but still wishes to return all of the associated buffers.
57 * Notification interrupt will be delivered when packet has been egressed.
61 * Boundary indicator. When 1, this transfer includes the EOP for this
62 * command. Must be clear on all but the last descriptor for an egress
66 /** Reserved. Must be zero. */
69 * Number of bytes to be sent for this descriptor. When zero, no data
70 * will be moved and the buffer descriptor will be ignored. If the
71 * buffer descriptor indicates that it is chained, the low 7 bits of the
72 * VA indicate the offset within the first buffer (e.g. 127 bytes is the
73 * maximum offset into the first buffer). If the size exceeds a single
74 * buffer, subsequent buffer descriptors will be fetched prior to
75 * processing the next eDMA descriptor in the ring.
77 uint_reg_t xfer_size : 14;
78 /** Reserved. Must be zero. */
81 * Destination of checksum relative to CSUM_START relative to the first
82 * byte moved by this descriptor. Must be zero if CSUM=0 in this
83 * descriptor. Must be less than XFER_SIZE (e.g. the first byte of the
84 * CSUM_DEST must be within the span of this descriptor).
86 uint_reg_t csum_dest : 8;
88 * Start byte of checksum relative to the first byte moved by this
89 * descriptor. If this is not the first descriptor for the egress
90 * packet, CSUM_START is still relative to the first byte in this
91 * descriptor. Must be zero if CSUM=0 in this descriptor.
93 uint_reg_t csum_start : 8;
95 * Initial value for 16-bit 1's compliment checksum if enabled via CSUM.
96 * Specified in network order. That is, bits[7:0] will be added to the
97 * byte pointed to by CSUM_START and bits[15:8] will be added to the byte
98 * pointed to by CSUM_START+1 (with appropriate 1's compliment carries).
99 * Must be zero if CSUM=0 in this descriptor.
101 uint_reg_t csum_seed : 16;
102 #else /* __BIG_ENDIAN__ */
103 uint_reg_t csum_seed : 16;
104 uint_reg_t csum_start : 8;
105 uint_reg_t csum_dest : 8;
107 uint_reg_t xfer_size : 14;
109 uint_reg_t bound : 1;
110 uint_reg_t notif : 1;
119 #ifndef __BIG_ENDIAN__
120 /** Virtual address. Must be sign extended by consumer. */
123 uint_reg_t __reserved_0 : 6;
124 /** Index of the buffer stack to which this buffer belongs. */
125 uint_reg_t stack_idx : 5;
127 uint_reg_t __reserved_1 : 3;
129 * Instance ID. For devices that support more than one mPIPE instance,
130 * this field indicates the buffer owner. If the INST field does not
131 * match the mPIPE's instance number when a packet is egressed, buffers
132 * with HWB set will be returned to the other mPIPE instance.
136 uint_reg_t __reserved_2 : 1;
138 * Always set to one by hardware in iDMA packet descriptors. For eDMA,
139 * indicates whether the buffer will be released to the buffer stack
140 * manager. When 0, software is responsible for releasing the buffer.
144 * Encoded size of buffer. Set by the ingress hardware for iDMA packet
145 * descriptors. For eDMA descriptors, indicates the buffer size if .c
146 * indicates a chained packet. If an eDMA descriptor is not chained and
147 * the .hwb bit is not set, this field is ignored and the size is
148 * specified by the .xfer_size field.
160 * Chaining configuration for the buffer. Indicates that an ingress
161 * packet or egress command is chained across multiple buffers, with each
162 * buffer's size indicated by the .size field.
165 #else /* __BIG_ENDIAN__ */
169 uint_reg_t __reserved_2 : 1;
171 uint_reg_t __reserved_1 : 3;
172 uint_reg_t stack_idx : 5;
173 uint_reg_t __reserved_0 : 6;
184 * MPIPE Packet Descriptor.
185 * The packet descriptor is filled by the mPIPE's classification,
186 * load-balancing, and buffer management services. Some fields are consumed
187 * by mPIPE hardware, and others are consumed by Tile software.
197 #ifndef __BIG_ENDIAN__
199 * Notification ring into which this packet descriptor is written.
200 * Typically written by load balancer, but can be overridden by
201 * classification program if NR is asserted.
203 uint_reg_t notif_ring : 8;
204 /** Source channel for this packet. Written by mPIPE DMA hardware. */
205 uint_reg_t channel : 5;
207 uint_reg_t __reserved_0 : 1;
210 * Generated by the MAC interface. Asserted if there was an overrun of
211 * the MAC's receive FIFO. This condition generally only occurs if the
212 * mPIPE clock is running too slowly.
217 * Written by the iDMA hardware. Asserted if packet was truncated due to
218 * insufficient space in iPkt buffer
222 * Written by the iDMA hardware. Indicates the number of bytes written
223 * to Tile memory. In general, this is the actual size of the packet as
224 * received from the MAC. But if the packet is truncated due to running
225 * out of buffers or due to the iPkt buffer filling up, then the L2_SIZE
226 * will be reduced to reflect the actual number of valid bytes written to
229 uint_reg_t l2_size : 14;
232 * Generated by the MAC. Asserted if MAC indicated an L2 CRC error or
233 * other L2 error (bad length etc.) on the packet.
238 * Written by the iDMA hardware. Asserted if packet was not completely
239 * received before being sent to classifier. L2_Size will indicate
240 * number of bytes received so far.
244 * Written by the classification program. Used by the load balancer to
245 * select the ring into which this packet descriptor is written.
247 uint_reg_t bucket_id : 13;
249 uint_reg_t __reserved_1 : 3;
252 * Written by classification program. When 1, the checksum engine will
253 * perform checksum based on the CSUM_SEED, CSUM_START, and CSUM_BYTES
254 * fields. The result will be placed in CSUM_VAL.
258 * Notification Ring Select.
259 * Written by the classification program. When 1, the NotifRingIDX is
260 * set by classification program rather than being set by load balancer.
264 * Written by classification program. Indicates whether packet and
265 * descriptor should both be dropped, both be delivered, or only the
266 * descriptor should be delivered.
270 * General Purpose Sequence Number Enable.
271 * Written by the classification program. When 1, the GP_SQN_SEL field
272 * contains the sequence number selector and the GP_SQN field will be
273 * replaced with the associated sequence number. When clear, the GP_SQN
274 * field is left intact and be used as "Custom" bytes.
279 * Enable TimeStamp insertion. When clear, timestamp field may be filled
280 * with custom data by classifier. When set, hardware inserts the
281 * timestamp when the start of packet is received from the MAC.
285 * Packet Sequence Number Enable.
286 * Enable PacketSQN insertion. When clear, PacketSQN field may be filled
287 * with custom data by classifier. When set, hardware inserts the packet
288 * sequence number when the packet descriptor is written to a
294 * Written by the iDMA hardware. Asserted if iDMA ran out of buffers
295 * while writing the packet. Software must still return any buffer
296 * descriptors whose C field indicates a valid descriptor was consumed.
300 * Written by the classification program. The associated counter is
301 * incremented when the packet is sent.
305 uint_reg_t __reserved_2 : 3;
306 #else /* __BIG_ENDIAN__ */
307 uint_reg_t __reserved_2 : 3;
316 uint_reg_t __reserved_1 : 3;
317 uint_reg_t bucket_id : 13;
320 uint_reg_t l2_size : 14;
323 uint_reg_t __reserved_0 : 1;
324 uint_reg_t channel : 5;
325 uint_reg_t notif_ring : 8;
330 #ifndef __BIG_ENDIAN__
332 * Written by the classification program. The associated counter is
333 * incremented when the packet is sent.
337 uint_reg_t __reserved_3 : 3;
339 * Written by classification program. Indicates the start byte for
340 * checksum. Relative to 1st byte received from MAC.
342 uint_reg_t csum_start : 8;
344 * Checksum seed written by classification program. Overwritten with
345 * resultant checksum if CS bit is asserted. The endianness of the CSUM
346 * value bits when viewed by Tile software match the packet byte order.
347 * That is, bits[7:0] of the resulting checksum value correspond to
348 * earlier (more significant) bytes in the packet. To avoid classifier
349 * software from having to byte swap the CSUM_SEED, the iDMA checksum
350 * engine byte swaps the classifier's result before seeding the checksum
351 * calculation. Thus, the CSUM_START byte of packet data is added to
352 * bits[15:8] of the CSUM_SEED field generated by the classifier. This
353 * byte swap will be visible to Tile software if the CS bit is clear.
355 uint_reg_t csum_seed_val : 16;
357 * Written by the classification program. Not interpreted by mPIPE
360 uint_reg_t custom0 : 32;
361 #else /* __BIG_ENDIAN__ */
362 uint_reg_t custom0 : 32;
363 uint_reg_t csum_seed_val : 16;
364 uint_reg_t csum_start : 8;
365 uint_reg_t __reserved_3 : 3;
371 #ifndef __BIG_ENDIAN__
373 * Written by the classification program. Not interpreted by mPIPE
376 uint_reg_t custom1 : 64;
377 #else /* __BIG_ENDIAN__ */
378 uint_reg_t custom1 : 64;
383 #ifndef __BIG_ENDIAN__
385 * Written by the classification program. Not interpreted by mPIPE
388 uint_reg_t custom2 : 64;
389 #else /* __BIG_ENDIAN__ */
390 uint_reg_t custom2 : 64;
395 #ifndef __BIG_ENDIAN__
397 * Written by the classification program. Not interpreted by mPIPE
400 uint_reg_t custom3 : 64;
401 #else /* __BIG_ENDIAN__ */
402 uint_reg_t custom3 : 64;
407 #ifndef __BIG_ENDIAN__
409 * Sequence number applied when packet is distributed. Classifier
410 * selects which sequence number is to be applied by writing the 13-bit
411 * SQN-selector into this field.
413 uint_reg_t gp_sqn : 16;
415 * Written by notification hardware. The packet sequence number is
416 * incremented for each packet that wasn't dropped.
418 uint_reg_t packet_sqn : 48;
419 #else /* __BIG_ENDIAN__ */
420 uint_reg_t packet_sqn : 48;
421 uint_reg_t gp_sqn : 16;
426 #ifndef __BIG_ENDIAN__
428 * Written by hardware when the start-of-packet is received by the mPIPE
429 * from the MAC. This is the nanoseconds part of the packet timestamp.
431 uint_reg_t time_stamp_ns : 32;
433 * Written by hardware when the start-of-packet is received by the mPIPE
434 * from the MAC. This is the seconds part of the packet timestamp.
436 uint_reg_t time_stamp_sec : 32;
437 #else /* __BIG_ENDIAN__ */
438 uint_reg_t time_stamp_sec : 32;
439 uint_reg_t time_stamp_ns : 32;
444 #ifndef __BIG_ENDIAN__
445 /** Virtual address. Must be sign extended by consumer. */
448 uint_reg_t __reserved_4 : 6;
449 /** Index of the buffer stack to which this buffer belongs. */
450 uint_reg_t stack_idx : 5;
452 uint_reg_t __reserved_5 : 3;
454 * Instance ID. For devices that support more than one mPIPE instance,
455 * this field indicates the buffer owner. If the INST field does not
456 * match the mPIPE's instance number when a packet is egressed, buffers
457 * with HWB set will be returned to the other mPIPE instance.
461 uint_reg_t __reserved_6 : 1;
463 * Always set to one by hardware in iDMA packet descriptors. For eDMA,
464 * indicates whether the buffer will be released to the buffer stack
465 * manager. When 0, software is responsible for releasing the buffer.
469 * Encoded size of buffer. Set by the ingress hardware for iDMA packet
470 * descriptors. For eDMA descriptors, indicates the buffer size if .c
471 * indicates a chained packet. If an eDMA descriptor is not chained and
472 * the .hwb bit is not set, this field is ignored and the size is
473 * specified by the .xfer_size field.
485 * Chaining configuration for the buffer. Indicates that an ingress
486 * packet or egress command is chained across multiple buffers, with each
487 * buffer's size indicated by the .size field.
490 #else /* __BIG_ENDIAN__ */
494 uint_reg_t __reserved_6 : 1;
496 uint_reg_t __reserved_5 : 3;
497 uint_reg_t stack_idx : 5;
498 uint_reg_t __reserved_4 : 6;
507 #endif /* !defined(__ASSEMBLER__) */
509 #endif /* !defined(__ARCH_MPIPE_SHM_H__) */