2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_IRQFLAGS_H
16 #define _ASM_TILE_IRQFLAGS_H
18 #include <arch/interrupts.h>
19 #include <arch/chip.h>
22 * The set of interrupts we want to allow when interrupts are nominally
23 * disabled. The remainder are effectively "NMI" interrupts from
24 * the point of view of the generic Linux code. Note that synchronous
25 * interrupts (aka "non-queued") are not blocked by the mask in any case.
27 #define LINUX_MASKABLE_INTERRUPTS \
28 (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
30 #if CHIP_HAS_SPLIT_INTR_MASK()
31 /* The same macro, but for the two 32-bit SPRs separately. */
32 #define LINUX_MASKABLE_INTERRUPTS_LO (-1)
33 #define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
39 /* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
40 #include <asm/percpu.h>
41 #include <arch/spr_def.h>
43 /* Set and clear kernel interrupt masks. */
44 #if CHIP_HAS_SPLIT_INTR_MASK()
45 #if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32 || INT_MEM_ERROR >= 32
46 # error Fix assumptions about which word various interrupts are in
48 #define interrupt_mask_set(n) do { \
50 int __mask = 1 << (__n & 0x1f); \
52 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
54 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
56 #define interrupt_mask_reset(n) do { \
58 int __mask = 1 << (__n & 0x1f); \
60 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
62 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
64 #define interrupt_mask_check(n) ({ \
67 __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
68 __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
69 >> (__n & 0x1f)) & 1; \
71 #define interrupt_mask_set_mask(mask) do { \
72 unsigned long long __m = (mask); \
73 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
74 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
76 #define interrupt_mask_reset_mask(mask) do { \
77 unsigned long long __m = (mask); \
78 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
79 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
81 #define interrupt_mask_save_mask() \
82 (__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_0) | \
83 (((unsigned long long)__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_1))<<32))
84 #define interrupt_mask_restore_mask(mask) do { \
85 unsigned long long __m = (mask); \
86 __insn_mtspr(SPR_INTERRUPT_MASK_K_0, (unsigned long)(__m)); \
87 __insn_mtspr(SPR_INTERRUPT_MASK_K_1, (unsigned long)(__m>>32)); \
90 #define interrupt_mask_set(n) \
91 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
92 #define interrupt_mask_reset(n) \
93 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
94 #define interrupt_mask_check(n) \
95 ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
96 #define interrupt_mask_set_mask(mask) \
97 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
98 #define interrupt_mask_reset_mask(mask) \
99 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
100 #define interrupt_mask_save_mask() \
101 __insn_mfspr(SPR_INTERRUPT_MASK_K)
102 #define interrupt_mask_restore_mask(mask) \
103 __insn_mtspr(SPR_INTERRUPT_MASK_K, (mask))
107 * The set of interrupts we want active if irqs are enabled.
108 * Note that in particular, the tile timer interrupt comes and goes
109 * from this set, since we have no other way to turn off the timer.
110 * Likewise, INTCTRL_K is removed and re-added during device
111 * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
112 * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
113 * is always claimed as an "active interrupt" so we can query that bit
114 * to know our current state.
116 DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
117 #define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
119 /* Disable interrupts. */
120 #define arch_local_irq_disable() \
121 interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
123 /* Disable all interrupts, including NMIs. */
124 #define arch_local_irq_disable_all() \
125 interrupt_mask_set_mask(-1ULL)
127 /* Re-enable all maskable interrupts. */
128 #define arch_local_irq_enable() \
129 interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
131 /* Disable or enable interrupts based on flag argument. */
132 #define arch_local_irq_restore(disabled) do { \
134 arch_local_irq_disable(); \
136 arch_local_irq_enable(); \
139 /* Return true if "flags" argument means interrupts are disabled. */
140 #define arch_irqs_disabled_flags(flags) ((flags) != 0)
142 /* Return true if interrupts are currently disabled. */
143 #define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
145 /* Save whether interrupts are currently disabled. */
146 #define arch_local_save_flags() arch_irqs_disabled()
148 /* Save whether interrupts are currently disabled, then disable them. */
149 #define arch_local_irq_save() ({ \
150 unsigned long __flags = arch_local_save_flags(); \
151 arch_local_irq_disable(); \
154 /* Prevent the given interrupt from being enabled next time we enable irqs. */
155 #define arch_local_irq_mask(interrupt) \
156 (__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
158 /* Prevent the given interrupt from being enabled immediately. */
159 #define arch_local_irq_mask_now(interrupt) do { \
160 arch_local_irq_mask(interrupt); \
161 interrupt_mask_set(interrupt); \
164 /* Allow the given interrupt to be enabled next time we enable irqs. */
165 #define arch_local_irq_unmask(interrupt) \
166 (__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
168 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
169 #define arch_local_irq_unmask_now(interrupt) do { \
170 arch_local_irq_unmask(interrupt); \
171 if (!irqs_disabled()) \
172 interrupt_mask_reset(interrupt); \
175 #else /* __ASSEMBLY__ */
177 /* We provide a somewhat more restricted set for assembly. */
181 #if INT_MEM_ERROR != 0
182 # error Fix IRQS_DISABLED() macro
185 /* Return 0 or 1 to indicate whether interrupts are currently disabled. */
186 #define IRQS_DISABLED(tmp) \
187 mfspr tmp, SPR_INTERRUPT_MASK_K; \
190 /* Load up a pointer to &interrupts_enabled_mask. */
191 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
192 moveli reg, hw2_last(interrupts_enabled_mask); \
193 shl16insli reg, reg, hw1(interrupts_enabled_mask); \
194 shl16insli reg, reg, hw0(interrupts_enabled_mask); \
197 /* Disable interrupts. */
198 #define IRQ_DISABLE(tmp0, tmp1) \
199 moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \
200 shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \
201 shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \
202 mtspr SPR_INTERRUPT_MASK_SET_K, tmp0
204 /* Disable ALL synchronous interrupts (used by NMI entry). */
205 #define IRQ_DISABLE_ALL(tmp) \
207 mtspr SPR_INTERRUPT_MASK_SET_K, tmp
209 /* Enable interrupts. */
210 #define IRQ_ENABLE_LOAD(tmp0, tmp1) \
211 GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
213 #define IRQ_ENABLE_APPLY(tmp0, tmp1) \
214 mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0
216 #else /* !__tilegx__ */
219 * Return 0 or 1 to indicate whether interrupts are currently disabled.
220 * Note that it's important that we use a bit from the "low" mask word,
221 * since when we are enabling, that is the word we write first, so if we
222 * are interrupted after only writing half of the mask, the interrupt
223 * handler will correctly observe that we have interrupts enabled, and
224 * will enable interrupts itself on return from the interrupt handler
225 * (making the original code's write of the "high" mask word idempotent).
227 #define IRQS_DISABLED(tmp) \
228 mfspr tmp, SPR_INTERRUPT_MASK_K_0; \
229 shri tmp, tmp, INT_MEM_ERROR; \
232 /* Load up a pointer to &interrupts_enabled_mask. */
233 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
234 moveli reg, lo16(interrupts_enabled_mask); \
235 auli reg, reg, ha16(interrupts_enabled_mask); \
238 /* Disable interrupts. */
239 #define IRQ_DISABLE(tmp0, tmp1) \
241 movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
242 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
245 mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \
246 auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI) \
248 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1
250 /* Disable ALL synchronous interrupts (used by NMI entry). */
251 #define IRQ_DISABLE_ALL(tmp) \
253 mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \
254 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp
256 /* Enable interrupts. */
257 #define IRQ_ENABLE_LOAD(tmp0, tmp1) \
258 GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
264 #define IRQ_ENABLE_APPLY(tmp0, tmp1) \
265 mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \
266 mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1
269 #define IRQ_ENABLE(tmp0, tmp1) \
270 IRQ_ENABLE_LOAD(tmp0, tmp1); \
271 IRQ_ENABLE_APPLY(tmp0, tmp1)
274 * Do the CPU's IRQ-state tracing from assembly code. We call a
275 * C function, but almost everywhere we do, we don't mind clobbering
276 * all the caller-saved registers.
278 #ifdef CONFIG_TRACE_IRQFLAGS
279 # define TRACE_IRQS_ON jal trace_hardirqs_on
280 # define TRACE_IRQS_OFF jal trace_hardirqs_off
282 # define TRACE_IRQS_ON
283 # define TRACE_IRQS_OFF
286 #endif /* __ASSEMBLY__ */
288 #endif /* _ASM_TILE_IRQFLAGS_H */