2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
14 * Linux interrupt vectors.
17 #include <linux/linkage.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/init.h>
21 #include <asm/ptrace.h>
22 #include <asm/thread_info.h>
23 #include <asm/irqflags.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/types.h>
26 #include <asm/traps.h>
27 #include <asm/signal.h>
28 #include <hv/hypervisor.h>
30 #include <arch/interrupts.h>
31 #include <arch/spr_def.h>
34 # error "No support for kernel preemption currently"
37 #define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
39 #define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
42 .macro push_reg reg, ptr=sp, delta=-8
45 addli \ptr, \ptr, \delta
49 .macro pop_reg reg, ptr=sp, delta=8
52 addli \ptr, \ptr, \delta
56 .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
60 addi \ptr, \ptr, \delta
64 .macro push_extra_callee_saves reg
65 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
83 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
87 .pushsection .rodata, "a"
92 moveli r0, hw2_last(1b)
95 shl16insli r0, r0, hw1(1b)
98 shl16insli r0, r0, hw0(1b)
104 * Unalign data exception fast handling: In order to handle
105 * unaligned data access, a fast JIT version is generated and stored
106 * in a specific area in user space. We first need to do a quick poke
107 * to see if the JIT is available. We use certain bits in the fault
108 * PC (3 to 9 is used for 16KB page size) as index to address the JIT
109 * code area. The first 64bit word is the fault PC, and the 2nd one is
110 * the fault bundle itself. If these 2 words both match, then we
111 * directly "iret" to JIT code. If not, a slow path is invoked to
112 * generate new JIT code. Note: the current JIT code WILL be
113 * overwritten if it existed. So, ideally we can handle 128 unalign
114 * fixups via JIT. For lookup efficiency and to effectively support
115 * tight loops with multiple unaligned reference, a simple
116 * direct-mapped cache is used.
118 * SPR_EX_CONTEXT_K_0 is modified to return to JIT code.
119 * SPR_EX_CONTEXT_K_1 has ICS set.
120 * SPR_EX_CONTEXT_0_0 is setup to user program's next PC.
121 * SPR_EX_CONTEXT_0_1 = 0.
123 .macro int_hand_unalign_fast vecnum, vecname
126 /* Put r3 in SPR_SYSTEM_SAVE_K_1. */
127 mtspr SPR_SYSTEM_SAVE_K_1, r3
129 mfspr r3, SPR_EX_CONTEXT_K_1
131 * Examine if exception comes from user without ICS set.
132 * If not, just go directly to the slow path.
134 bnez r3, hand_unalign_slow_nonuser
136 mfspr r3, SPR_SYSTEM_SAVE_K_0
138 /* Get &thread_info->unalign_jit_tmp[0] in r3. */
139 mm r3, zero, LOG2_THREAD_SIZE, 63
140 #if THREAD_SIZE < 65536
141 addli r3, r3, -(PAGE_SIZE - THREAD_INFO_UNALIGN_JIT_TMP_OFFSET)
143 addli r3, r3, -(PAGE_SIZE/2)
144 addli r3, r3, -(PAGE_SIZE/2 - THREAD_INFO_UNALIGN_JIT_TMP_OFFSET)
148 * Save r0, r1, r2 into thread_info array r3 points to
149 * from low to high memory in order.
158 /* Save stored r3 value so we can revert it on a page fault. */
159 mfspr r1, SPR_SYSTEM_SAVE_K_1
163 /* Generate a SIGBUS if sp is not 8-byte aligned. */
164 bnez r2, hand_unalign_slow_badsp
168 * Get the thread_info in r0; load r1 with pc. Set the low bit of sp
169 * as an indicator to the page fault code in case we fault.
173 mfspr r1, SPR_EX_CONTEXT_K_0
176 /* Add the jit_info offset in thread_info; extract r1 [3:9] into r2. */
178 addli r0, r3, THREAD_INFO_UNALIGN_JIT_BASE_OFFSET - \
179 (THREAD_INFO_UNALIGN_JIT_TMP_OFFSET + (3 * 8))
180 bfextu r2, r1, 3, (2 + PAGE_SHIFT - UNALIGN_JIT_SHIFT)
183 /* Load the jit_info; multiply r2 by 128. */
186 shli r2, r2, UNALIGN_JIT_SHIFT
190 * If r0 is NULL, the JIT page is not mapped, so go to slow path;
191 * add offset r2 to r0 at the same time.
194 beqz r0, hand_unalign_slow
199 * We are loading from userspace (both the JIT info PC and
200 * instruction word, and the instruction word we executed)
201 * and since either could fault while holding the interrupt
202 * critical section, we must tag this region and check it in
203 * do_page_fault() to handle it properly.
205 ENTRY(__start_unalign_asm_code)
207 /* Load first word of JIT in r0 and increment r2 by 8. */
211 * Compare the PC with the 1st word in JIT; load the fault bundle
219 /* Go to slow path if PC doesn't match. */
220 beqz r0, hand_unalign_slow
223 * Load the 2nd word of JIT, which is supposed to be the fault
224 * bundle for a cache hit. Increment r2; after this bundle r2 will
225 * point to the potential start of the JIT code we want to run.
229 /* No further accesses to userspace are done after this point. */
230 ENTRY(__end_unalign_asm_code)
232 /* Compare the real bundle with what is saved in the JIT area. */
235 mtspr SPR_EX_CONTEXT_0_1, zero
238 /* Go to slow path if the fault bundle does not match. */
239 beqz r0, hand_unalign_slow
242 * A cache hit is found.
243 * r2 points to start of JIT code (3rd word).
244 * r0 is the fault pc.
245 * r1 is the fault bundle.
246 * Reset the low bit of sp.
249 mfspr r0, SPR_EX_CONTEXT_K_0
253 /* Write r2 into EX_CONTEXT_K_0 and increment PC. */
255 mtspr SPR_EX_CONTEXT_K_0, r2
260 * Set ICS on kernel EX_CONTEXT_K_1 in order to "iret" to
261 * user with ICS set. This way, if the JIT fixup causes another
262 * unalign exception (which shouldn't be possible) the user
263 * process will be terminated with SIGBUS. Also, our fixup will
264 * run without interleaving with external interrupts.
265 * Each fixup is at most 14 bundles, so it won't hold ICS for long.
268 movei r1, PL_ICS_EX1(USER_PL, 1)
269 mtspr SPR_EX_CONTEXT_0_0, r0
273 mtspr SPR_EX_CONTEXT_K_1, r1
274 addi r3, r3, -(3 * 8)
277 /* Restore r0..r3. */
284 ENDPROC(intvec_\vecname)
287 #ifdef __COLLECT_LINKER_FEEDBACK__
288 .pushsection .text.intvec_feedback,"ax"
294 * Default interrupt handler.
296 * vecnum is where we'll put this code.
297 * c_routine is the C routine we'll call.
299 * The C routine is passed two arguments:
300 * - A pointer to the pt_regs state.
301 * - The interrupt vector number.
303 * The "processing" argument specifies the code for processing
304 * the interrupt. Defaults to "handle_interrupt".
306 .macro __int_hand vecnum, vecname, c_routine,processing=handle_interrupt
308 /* Temporarily save a register so we have somewhere to work. */
310 mtspr SPR_SYSTEM_SAVE_K_1, r0
311 mfspr r0, SPR_EX_CONTEXT_K_1
314 * The unalign data fastpath code sets the low bit in sp to
315 * force us to reset it here on fault.
319 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
322 .ifc \vecnum, INT_DOUBLE_FAULT
324 * For double-faults from user-space, fall through to the normal
325 * register save and stack setup path. Otherwise, it's the
326 * hypervisor giving us one last chance to dump diagnostics, and we
327 * branch to the kernel_double_fault routine to do so.
330 j _kernel_double_fault
334 * If we're coming from user-space, then set sp to the top of
335 * the kernel stack. Otherwise, assume sp is already valid.
343 .ifc \c_routine, do_page_fault
345 * The page_fault handler may be downcalled directly by the
346 * hypervisor even when Linux is running and has ICS set.
348 * In this case the contents of EX_CONTEXT_K_1 reflect the
349 * previous fault and can't be relied on to choose whether or
350 * not to reinitialize the stack pointer. So we add a test
351 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
352 * and if so we don't reinitialize sp, since we must be coming
353 * from Linux. (In fact the precise case is !(val & ~1),
354 * but any Linux PC has to have the high bit set.)
356 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
357 * any path that turns into a downcall to one of our TLB handlers.
359 * FIXME: if we end up never using this path, perhaps we should
360 * prevent the hypervisor from generating downcalls in this case.
361 * The advantage of getting a downcall is we can panic in Linux.
363 mfspr r0, SPR_SYSTEM_SAVE_K_2
365 bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
372 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
373 * the current stack top in the higher bits. So we recover
374 * our stack top by just masking off the low bits, then
375 * point sp at the top aligned address on the actual stack page.
377 mfspr r0, SPR_SYSTEM_SAVE_K_0
378 mm r0, zero, LOG2_THREAD_SIZE, 63
382 * Align the stack mod 64 so we can properly predict what
383 * cache lines we need to write-hint to reduce memory fetch
384 * latency as we enter the kernel. The layout of memory is
385 * as follows, with cache line 0 at the lowest VA, and cache
386 * line 8 just below the r0 value this "andi" computes.
387 * Note that we never write to cache line 8, and we skip
388 * cache lines 1-3 for syscalls.
390 * cache line 8: ptregs padding (two words)
391 * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
392 * cache line 6: r46...r53 (tp)
393 * cache line 5: r38...r45
394 * cache line 4: r30...r37
395 * cache line 3: r22...r29
396 * cache line 2: r14...r21
397 * cache line 1: r6...r13
398 * cache line 0: 2 x frame, r0..r5
403 * Push the first four registers on the stack, so that we can set
404 * them to vector-unique values before we jump to the common code.
406 * Registers are pushed on the stack as a struct pt_regs,
407 * with the sp initially just above the struct, and when we're
408 * done, sp points to the base of the struct, minus
409 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
411 * This routine saves just the first four registers, plus the
412 * stack context so we can do proper backtracing right away,
413 * and defers to handle_interrupt to save the rest.
414 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum,
415 * and needs sp set to its final location at the bottom of
418 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
419 wh64 r0 /* cache line 7 */
422 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
426 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
428 wh64 sp /* cache line 6 */
431 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
433 wh64 sp /* cache line 0 */
436 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
440 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
444 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
446 mfspr r0, SPR_EX_CONTEXT_K_0
447 .ifc \processing,handle_syscall
449 * Bump the saved PC by one bundle so that when we return, we won't
450 * execute the same swint instruction again. We need to do this while
451 * we're in the critical section.
457 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
459 mfspr r0, SPR_EX_CONTEXT_K_1
462 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
464 * Use r0 for syscalls so it's a temporary; use r1 for interrupts
465 * so that it gets passed through unchanged to the handler routine.
466 * Note that the .if conditional confusingly spans bundles.
468 .ifc \processing,handle_syscall
479 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
481 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
484 addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
487 st sp, zero /* write zero into "Next SP" frame pointer */
488 addi sp, sp, -8 /* leave SP pointing at bottom of frame */
490 .ifc \processing,handle_syscall
493 /* Capture per-interrupt SPR context to registers. */
494 .ifc \c_routine, do_page_fault
495 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
496 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
498 .ifc \vecnum, INT_ILL_TRANS
499 mfspr r2, ILL_TRANS_REASON
501 .ifc \vecnum, INT_DOUBLE_FAULT
502 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
504 .ifc \c_routine, do_trap
507 .ifc \c_routine, op_handle_perf_interrupt
508 mfspr r2, PERF_COUNT_STS
509 #if CHIP_HAS_AUX_PERF_COUNTERS()
511 .ifc \c_routine, op_handle_aux_perf_interrupt
512 mfspr r2, AUX_PERF_COUNT_STS
520 /* Put function pointer in r0 */
521 moveli r0, hw2_last(\c_routine)
522 shl16insli r0, r0, hw1(\c_routine)
524 shl16insli r0, r0, hw0(\c_routine)
528 ENDPROC(intvec_\vecname)
530 #ifdef __COLLECT_LINKER_FEEDBACK__
531 .pushsection .text.intvec_feedback,"ax"
533 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
542 * Save the rest of the registers that we didn't save in the actual
543 * vector itself. We can't use r0-r10 inclusive here.
545 .macro finish_interrupt_save, function
547 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
548 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
550 .ifc \function,handle_syscall
555 PTREGS_PTR(r52, PTREGS_OFFSET_TP)
559 mfspr tp, CMPEXCH_VALUE
560 PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
564 * For ordinary syscalls, we save neither caller- nor callee-
565 * save registers, since the syscall invoker doesn't expect the
566 * caller-saves to be saved, and the called kernel functions will
567 * take care of saving the callee-saves for us.
569 * For interrupts we save just the caller-save registers. Saving
570 * them is required (since the "caller" can't save them). Again,
571 * the called kernel functions will restore the callee-save
572 * registers for us appropriately.
574 * On return, we normally restore nothing special for syscalls,
575 * and just the caller-save registers for interrupts.
577 * However, there are some important caveats to all this:
579 * - We always save a few callee-save registers to give us
580 * some scratchpad registers to carry across function calls.
582 * - fork/vfork/etc require us to save all the callee-save
583 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
585 * - We always save r0..r5 and r10 for syscalls, since we need
586 * to reload them a bit later for the actual kernel call, and
587 * since we might need them for -ERESTARTNOINTR, etc.
589 * - Before invoking a signal handler, we save the unsaved
590 * callee-save registers so they are visible to the
591 * signal handler or any ptracer.
593 * - If the unsaved callee-save registers are modified, we set
594 * a bit in pt_regs so we know to reload them from pt_regs
595 * and not just rely on the kernel function unwinding.
596 * (Done for ptrace register writes and SA_SIGINFO handler.)
600 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
602 wh64 r52 /* cache line 4 */
606 .ifc \function,handle_syscall
607 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
608 push_reg TREG_SYSCALL_NR_NAME, r52, \
609 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
612 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
613 wh64 r52 /* cache line 3 */
622 wh64 r52 /* cache line 2 */
631 wh64 r52 /* cache line 1 */
647 * If we will be returning to the kernel, we will need to
648 * reset the interrupt masks to the state they had before.
649 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
651 mfspr r32, SPR_EX_CONTEXT_K_1
653 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
654 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
656 beqzt r32, 1f /* zero if from user space */
657 IRQS_DISABLED(r32) /* zero if irqs enabled */
658 #if PT_FLAGS_DISABLE_IRQ != 1
659 # error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
662 .ifnc \function,handle_syscall
663 /* Record the fact that we saved the caller-save registers above. */
664 ori r32, r32, PT_FLAGS_CALLER_SAVES
669 * we've captured enough state to the stack (including in
670 * particular our EX_CONTEXT state) that we can now release
671 * the interrupt critical section and replace it with our
672 * standard "interrupts disabled" mask value. This allows
673 * synchronous interrupts (and profile interrupts) to punch
674 * through from this point onwards.
676 * It's important that no code before this point touch memory
677 * other than our own stack (to keep the invariant that this
678 * is all that gets touched under ICS), and that no code after
679 * this point reference any interrupt-specific SPR, in particular
680 * the EX_CONTEXT_K_ values.
682 .ifc \function,handle_nmi
685 IRQ_DISABLE(r20, r21)
687 mtspr INTERRUPT_CRITICAL_SECTION, zero
689 /* Load tp with our per-cpu offset. */
692 mfspr r20, SPR_SYSTEM_SAVE_K_0
693 moveli r21, hw2_last(__per_cpu_offset)
696 shl16insli r21, r21, hw1(__per_cpu_offset)
697 bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
699 shl16insli r21, r21, hw0(__per_cpu_offset)
700 shl3add r20, r20, r21
706 #ifdef __COLLECT_LINKER_FEEDBACK__
708 * Notify the feedback routines that we were in the
709 * appropriate fixed interrupt vector area. Note that we
710 * still have ICS set at this point, so we can't invoke any
711 * atomic operations or we will panic. The feedback
712 * routines internally preserve r0..r10 and r30 up.
714 .ifnc \function,handle_syscall
717 moveli r20, INT_SWINT_1 << 5
719 moveli r21, hw2_last(intvec_feedback)
720 shl16insli r21, r21, hw1(intvec_feedback)
721 shl16insli r21, r21, hw0(intvec_feedback)
725 /* And now notify the feedback routines that we are here. */
726 FEEDBACK_ENTER(\function)
730 * Prepare the first 256 stack bytes to be rapidly accessible
731 * without having to fetch the background data.
748 #ifdef CONFIG_TRACE_IRQFLAGS
749 .ifnc \function,handle_nmi
751 * We finally have enough state set up to notify the irq
752 * tracing code that irqs were disabled on entry to the handler.
753 * The TRACE_IRQS_OFF call clobbers registers r0-r29.
754 * For syscalls, we already have the register state saved away
755 * on the stack, so we don't bother to do any register saves here,
756 * and later we pop the registers back off the kernel stack.
757 * For interrupt handlers, save r0-r3 in callee-saved registers.
759 .ifnc \function,handle_syscall
760 { move r30, r0; move r31, r1 }
761 { move r32, r2; move r33, r3 }
764 .ifnc \function,handle_syscall
765 { move r0, r30; move r1, r31 }
766 { move r2, r32; move r3, r33 }
774 * Redispatch a downcall.
776 .macro dc_dispatch vecnum, vecname
779 j hv_downcall_dispatch
780 ENDPROC(intvec_\vecname)
784 * Common code for most interrupts. The C function we're eventually
785 * going to is in r0, and the faultnum is in r1; the original
786 * values for those registers are on the stack.
788 .pushsection .text.handle_interrupt,"ax"
790 finish_interrupt_save handle_interrupt
792 /* Jump to the C routine; it should enable irqs as soon as possible. */
795 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
797 FEEDBACK_REENTER(handle_interrupt)
799 movei r30, 0 /* not an NMI */
802 STD_ENDPROC(handle_interrupt)
805 * This routine takes a boolean in r30 indicating if this is an NMI.
806 * If so, we also expect a boolean in r31 indicating whether to
807 * re-enable the oprofile interrupts.
809 * Note that .Lresume_userspace is jumped to directly in several
810 * places, and we need to make sure r30 is set correctly in those
813 STD_ENTRY(interrupt_return)
814 /* If we're resuming to kernel space, don't check thread flags. */
816 bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
817 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
820 andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
822 beqzt r29, .Lresume_userspace
823 PTREGS_PTR(r29, PTREGS_OFFSET_PC)
826 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
827 moveli r27, hw2_last(_cpu_idle_nap)
830 shl16insli r27, r27, hw1(_cpu_idle_nap)
833 shl16insli r27, r27, hw0(_cpu_idle_nap)
839 blbc r27, .Lrestore_all
846 FEEDBACK_REENTER(interrupt_return)
849 * Use r33 to hold whether we have already loaded the callee-saves
850 * into ptregs. We don't want to do it twice in this loop, since
851 * then we'd clobber whatever changes are made by ptrace, etc.
858 /* Get base of stack in r32. */
859 EXTRACT_THREAD_INFO(r32)
861 .Lretry_work_pending:
863 * Disable interrupts so as to make sure we don't
864 * miss an interrupt that sets any of the thread flags (like
865 * need_resched or sigpending) between sampling and the iret.
866 * Routines like schedule() or do_signal() may re-enable
867 * interrupts before returning.
869 IRQ_DISABLE(r20, r21)
870 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
873 /* Check to see if there is any work to do before returning to user. */
875 addi r29, r32, THREAD_INFO_FLAGS_OFFSET
876 moveli r1, hw1_last(_TIF_ALLWORK_MASK)
880 shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
883 beqzt r1, .Lrestore_all
886 * Make sure we have all the registers saved for signal
887 * handling or notify-resume. Call out to C code to figure out
888 * exactly what we need to do for each flag bit, then if
889 * necessary, reload the flags and recheck.
892 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
895 push_extra_callee_saves r0
897 1: jal do_work_pending
898 bnez r0, .Lretry_work_pending
902 * omit the call to single_process_check_nohz, which normally checks
903 * to see if we should start or stop the scheduler tick, because
904 * we can't call arbitrary Linux code from an NMI context.
905 * We always call the homecache TLB deferral code to re-trigger
906 * the deferral mechanism.
908 * The other chunk of responsibility this code has is to reset the
909 * interrupt masks appropriately to reset irqs and NMIs. We have
910 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
911 * lockdep-type stuff, but we can't set ICS until afterwards, since
912 * ICS can only be used in very tight chunks of code to avoid
913 * tripping over various assertions that it is off.
916 PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
919 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
922 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
927 #if PT_FLAGS_DISABLE_IRQ != 1
928 # error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
934 mtspr INTERRUPT_CRITICAL_SECTION, r0
935 beqzt r30, .Lrestore_regs
938 IRQ_ENABLE_LOAD(r20, r21)
940 mtspr INTERRUPT_CRITICAL_SECTION, r0
941 IRQ_ENABLE_APPLY(r20, r21)
942 beqzt r30, .Lrestore_regs
947 * We now commit to returning from this interrupt, since we will be
948 * doing things like setting EX_CONTEXT SPRs and unwinding the stack
949 * frame. No calls should be made to any other code after this point.
950 * This code should only be entered with ICS set.
951 * r32 must still be set to ptregs.flags.
952 * We launch loads to each cache line separately first, so we can
953 * get some parallelism out of the memory subsystem.
954 * We start zeroing caller-saved registers throughout, since
955 * that will save some cycles if this turns out to be a syscall.
960 * Rotate so we have one high bit and one low bit to test.
961 * - low bit says whether to restore all the callee-saved registers,
962 * or just r30-r33, and r52 up.
963 * - high bit (i.e. sign bit) says whether to restore all the
964 * caller-saved registers, or just r0.
966 #if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
967 # error Rotate trick does not work :-)
971 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
975 * Load cache lines 0, 4, 6 and 7, in that order, then use
976 * the last loaded value, which makes it likely that the other
977 * cache lines have also loaded, at which point we should be
978 * able to safely read all the remaining words on those cache
979 * lines without waiting for the memory subsystem.
981 pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
982 pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
983 pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
984 pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
985 pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
987 mtspr CMPEXCH_VALUE, r21
990 pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
992 mtspr SPR_EX_CONTEXT_K_1, lr
993 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
996 mtspr SPR_EX_CONTEXT_K_0, r21
1000 /* Restore callee-saveds that we actually use. */
1001 pop_reg_zero r31, r6
1002 pop_reg_zero r32, r7
1003 pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
1006 * If we modified other callee-saveds, restore them now.
1007 * This is rare, but could be via ptrace or signal handler.
1011 blbs r20, .Lrestore_callees
1013 .Lcontinue_restore_regs:
1015 /* Check if we're returning from a syscall. */
1018 bltzt r20, 1f /* no, so go restore callee-save registers */
1022 * Check if we're returning to userspace.
1023 * Note that if we're not, we don't worry about zeroing everything.
1026 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
1027 bnez lr, .Lkernel_return
1031 * On return from syscall, we've restored r0 from pt_regs, but we
1032 * clear the remainder of the caller-saved registers. We could
1033 * restore the syscall arguments, but there's not much point,
1034 * and it ensures user programs aren't trying to use the
1035 * caller-saves if we clear them, as well as avoiding leaking
1036 * kernel pointers into userspace.
1038 pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
1039 pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
1045 { move r15, zero; move r16, zero }
1046 { move r17, zero; move r18, zero }
1047 { move r19, zero; move r20, zero }
1048 { move r21, zero; move r22, zero }
1049 { move r23, zero; move r24, zero }
1050 { move r25, zero; move r26, zero }
1052 /* Set r1 to errno if we are returning an error, otherwise zero. */
1068 * Not a syscall, so restore caller-saved registers.
1069 * First kick off loads for cache lines 1-3, which we're touching
1070 * for the first time here.
1073 1: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
1074 pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
1075 pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
1088 /* r13 already restored above */
1096 /* r21 already restored above */
1103 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
1104 /* r29 already restored above */
1105 bnez lr, .Lkernel_return
1106 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
1107 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
1112 * We can't restore tp when in kernel mode, since a thread might
1113 * have migrated from another cpu and brought a stale tp value.
1116 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
1120 /* Restore callee-saved registers from r34 to r51. */
1122 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
1140 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
1141 j .Lcontinue_restore_regs
1142 STD_ENDPROC(interrupt_return)
1145 * "NMI" interrupts mask ALL interrupts before calling the
1146 * handler, and don't check thread flags, etc., on the way
1147 * back out. In general, the only things we do here for NMIs
1148 * are register save/restore and dataplane kernel-TLB management.
1149 * We don't (for example) deal with start/stop of the sched tick.
1151 .pushsection .text.handle_nmi,"ax"
1153 finish_interrupt_save handle_nmi
1156 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1158 FEEDBACK_REENTER(handle_nmi)
1164 STD_ENDPROC(handle_nmi)
1167 * Parallel code for syscalls to handle_interrupt.
1169 .pushsection .text.handle_syscall,"ax"
1171 finish_interrupt_save handle_syscall
1175 IRQ_ENABLE(r20, r21)
1177 /* Bump the counter for syscalls made on this tile. */
1178 moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1179 shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1180 shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1189 EXTRACT_THREAD_INFO(r31)
1192 /* Trace syscalls, if requested. */
1193 addi r31, r31, THREAD_INFO_FLAGS_OFFSET
1196 moveli r32, _TIF_SYSCALL_ENTRY_WORK
1200 addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
1201 beqzt r30, .Lrestore_syscall_regs
1204 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1205 jal do_syscall_trace_enter
1207 FEEDBACK_REENTER(handle_syscall)
1210 * We always reload our registers from the stack at this
1211 * point. They might be valid, if we didn't build with
1212 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
1213 * doing syscall tracing, but there are enough cases now that it
1214 * seems simplest just to do the reload unconditionally.
1216 .Lrestore_syscall_regs:
1219 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
1226 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
1228 ld TREG_SYSCALL_NR_NAME, r11
1229 moveli r21, __NR_syscalls
1232 /* Ensure that the syscall number is within the legal range. */
1234 moveli r20, hw2(sys_call_table)
1235 #ifdef CONFIG_COMPAT
1236 blbs r30, .Lcompat_syscall
1240 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1241 shl16insli r20, r20, hw1(sys_call_table)
1244 blbc r21, .Linvalid_syscall
1245 shl16insli r20, r20, hw0(sys_call_table)
1247 .Lload_syscall_pointer:
1248 shl3add r20, TREG_SYSCALL_NR_NAME, r20
1251 /* Jump to syscall handler. */
1253 .Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1256 * Write our r0 onto the stack so it gets restored instead
1257 * of whatever the user had there before.
1258 * In compat mode, sign-extend r0 before storing it.
1261 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1267 .Lsyscall_sigreturn_skip:
1268 FEEDBACK_REENTER(handle_syscall)
1270 /* Do syscall trace again, if requested. */
1273 moveli r32, _TIF_SYSCALL_EXIT_WORK
1277 andi r0, r30, _TIF_SINGLESTEP
1281 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1282 jal do_syscall_trace_exit
1284 FEEDBACK_REENTER(handle_syscall)
1285 andi r0, r30, _TIF_SINGLESTEP
1289 /* Single stepping -- notify ptrace. */
1294 FEEDBACK_REENTER(handle_syscall)
1297 movei r30, 0 /* not an NMI */
1298 j .Lresume_userspace /* jump into middle of interrupt_return */
1301 #ifdef CONFIG_COMPAT
1304 * Load the base of the compat syscall table in r20, and
1305 * range-check the syscall number (duplicated from 64-bit path).
1306 * Sign-extend all the user's passed arguments to make them consistent.
1307 * Also save the original "r(n)" values away in "r(11+n)" in
1308 * case the syscall table entry wants to validate them.
1310 moveli r20, hw2(compat_sys_call_table)
1312 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1313 shl16insli r20, r20, hw1(compat_sys_call_table)
1316 blbc r21, .Linvalid_syscall
1317 shl16insli r20, r20, hw0(compat_sys_call_table)
1319 { move r11, r0; addxi r0, r0, 0 }
1320 { move r12, r1; addxi r1, r1, 0 }
1321 { move r13, r2; addxi r2, r2, 0 }
1322 { move r14, r3; addxi r3, r3, 0 }
1323 { move r15, r4; addxi r4, r4, 0 }
1324 { move r16, r5; addxi r5, r5, 0 }
1325 j .Lload_syscall_pointer
1329 /* Report an invalid syscall back to the user program */
1331 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1336 movei r30, 0 /* not an NMI */
1337 j .Lresume_userspace /* jump into middle of interrupt_return */
1339 STD_ENDPROC(handle_syscall)
1341 /* Return the address for oprofile to suppress in backtraces. */
1342 STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
1345 addli r0, r0, .Lhandle_syscall_link - .
1348 STD_ENDPROC(handle_syscall_link_address)
1350 STD_ENTRY(ret_from_fork)
1353 FEEDBACK_REENTER(ret_from_fork)
1355 movei r30, 0 /* not an NMI */
1356 j .Lresume_userspace /* jump into middle of interrupt_return */
1358 STD_ENDPROC(ret_from_fork)
1360 STD_ENTRY(ret_from_kernel_thread)
1363 FEEDBACK_REENTER(ret_from_fork)
1368 FEEDBACK_REENTER(ret_from_kernel_thread)
1370 movei r30, 0 /* not an NMI */
1371 j .Lresume_userspace /* jump into middle of interrupt_return */
1373 STD_ENDPROC(ret_from_kernel_thread)
1375 /* Various stub interrupt handlers and syscall handlers */
1377 STD_ENTRY_LOCAL(_kernel_double_fault)
1378 mfspr r1, SPR_EX_CONTEXT_K_0
1382 addi sp, sp, -C_ABI_SAVE_AREA_SIZE
1383 j kernel_double_fault
1384 STD_ENDPROC(_kernel_double_fault)
1386 STD_ENTRY_LOCAL(bad_intr)
1387 mfspr r2, SPR_EX_CONTEXT_K_0
1388 panic "Unhandled interrupt %#x: PC %#lx"
1389 STD_ENDPROC(bad_intr)
1392 * Special-case sigreturn to not write r0 to the stack on return.
1393 * This is technically more efficient, but it also avoids difficulties
1394 * in the 64-bit OS when handling 32-bit compat code, since we must not
1395 * sign-extend r0 for the sigreturn return-value case.
1397 #define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1399 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1401 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1406 PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1407 #ifdef CONFIG_COMPAT
1408 PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
1411 /* Save additional callee-saves to pt_regs and jump to standard function. */
1412 STD_ENTRY(_sys_clone)
1413 push_extra_callee_saves r4
1415 STD_ENDPROC(_sys_clone)
1418 * Recover r3, r2, r1 and r0 here saved by unalign fast vector.
1419 * The vector area limit is 32 bundles, so we handle the reload here.
1420 * r0, r1, r2 are in thread_info from low to high memory in order.
1421 * r3 points to location the original r3 was saved.
1422 * We put this code in the __HEAD section so it can be reached
1423 * via a conditional branch from the fast path.
1428 hand_unalign_slow_badsp:
1429 addi r3, r3, -(3 * 8)
1433 hand_unalign_slow_nonuser:
1434 mfspr r3, SPR_SYSTEM_SAVE_K_1
1435 __int_hand INT_UNALIGN_DATA, UNALIGN_DATA_SLOW, int_unalign
1437 /* The unaligned data support needs to read all the registers. */
1439 push_extra_callee_saves r0
1441 ENDPROC(hand_unalign_slow)
1443 /* Fill the return address stack with nonzero entries. */
1444 STD_ENTRY(fill_ra_stack)
1453 STD_ENDPROC(fill_ra_stack)
1455 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
1457 __int_hand \vecnum, \vecname, \c_routine, \processing
1460 /* Include .intrpt1 array of interrupt vectors */
1461 .section ".intrpt1", "ax"
1463 #define op_handle_perf_interrupt bad_intr
1464 #define op_handle_aux_perf_interrupt bad_intr
1466 #ifndef CONFIG_HARDWALL
1467 #define do_hardwall_trap bad_intr
1470 int_hand INT_MEM_ERROR, MEM_ERROR, do_trap
1471 int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
1472 #if CONFIG_KERNEL_PL == 2
1473 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
1474 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
1476 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
1477 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
1479 int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
1480 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
1481 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
1482 int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
1483 int_hand INT_ILL, ILL, do_trap
1484 int_hand INT_GPV, GPV, do_trap
1485 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
1486 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
1487 int_hand INT_SWINT_3, SWINT_3, do_trap
1488 int_hand INT_SWINT_2, SWINT_2, do_trap
1489 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
1490 int_hand INT_SWINT_0, SWINT_0, do_trap
1491 int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
1492 int_hand_unalign_fast INT_UNALIGN_DATA, UNALIGN_DATA
1493 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
1494 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
1495 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, do_hardwall_trap
1496 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
1497 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
1498 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
1499 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
1500 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
1501 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
1502 int_hand INT_IPI_3, IPI_3, bad_intr
1503 #if CONFIG_KERNEL_PL == 2
1504 int_hand INT_IPI_2, IPI_2, tile_dev_intr
1505 int_hand INT_IPI_1, IPI_1, bad_intr
1507 int_hand INT_IPI_2, IPI_2, bad_intr
1508 int_hand INT_IPI_1, IPI_1, tile_dev_intr
1510 int_hand INT_IPI_0, IPI_0, bad_intr
1511 int_hand INT_PERF_COUNT, PERF_COUNT, \
1512 op_handle_perf_interrupt, handle_nmi
1513 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
1514 op_handle_perf_interrupt, handle_nmi
1515 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
1516 #if CONFIG_KERNEL_PL == 2
1517 dc_dispatch INT_INTCTRL_2, INTCTRL_2
1518 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
1520 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
1521 dc_dispatch INT_INTCTRL_1, INTCTRL_1
1523 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
1524 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
1526 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
1527 int_hand INT_I_ASID, I_ASID, bad_intr
1528 int_hand INT_D_ASID, D_ASID, bad_intr
1529 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
1531 /* Synthetic interrupt delivered only by the simulator */
1532 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint