2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
14 * Linux interrupt vectors.
17 #include <linux/linkage.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/init.h>
21 #include <asm/ptrace.h>
22 #include <asm/thread_info.h>
23 #include <asm/irqflags.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/types.h>
26 #include <asm/traps.h>
27 #include <asm/signal.h>
28 #include <hv/hypervisor.h>
30 #include <arch/interrupts.h>
31 #include <arch/spr_def.h>
33 #define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
35 #define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
38 .macro push_reg reg, ptr=sp, delta=-8
41 addli \ptr, \ptr, \delta
45 .macro pop_reg reg, ptr=sp, delta=8
48 addli \ptr, \ptr, \delta
52 .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
56 addi \ptr, \ptr, \delta
60 .macro push_extra_callee_saves reg
61 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
79 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
83 .pushsection .rodata, "a"
88 moveli r0, hw2_last(1b)
91 shl16insli r0, r0, hw1(1b)
94 shl16insli r0, r0, hw0(1b)
100 * Unalign data exception fast handling: In order to handle
101 * unaligned data access, a fast JIT version is generated and stored
102 * in a specific area in user space. We first need to do a quick poke
103 * to see if the JIT is available. We use certain bits in the fault
104 * PC (3 to 9 is used for 16KB page size) as index to address the JIT
105 * code area. The first 64bit word is the fault PC, and the 2nd one is
106 * the fault bundle itself. If these 2 words both match, then we
107 * directly "iret" to JIT code. If not, a slow path is invoked to
108 * generate new JIT code. Note: the current JIT code WILL be
109 * overwritten if it existed. So, ideally we can handle 128 unalign
110 * fixups via JIT. For lookup efficiency and to effectively support
111 * tight loops with multiple unaligned reference, a simple
112 * direct-mapped cache is used.
114 * SPR_EX_CONTEXT_K_0 is modified to return to JIT code.
115 * SPR_EX_CONTEXT_K_1 has ICS set.
116 * SPR_EX_CONTEXT_0_0 is setup to user program's next PC.
117 * SPR_EX_CONTEXT_0_1 = 0.
119 .macro int_hand_unalign_fast vecnum, vecname
122 /* Put r3 in SPR_SYSTEM_SAVE_K_1. */
123 mtspr SPR_SYSTEM_SAVE_K_1, r3
125 mfspr r3, SPR_EX_CONTEXT_K_1
127 * Examine if exception comes from user without ICS set.
128 * If not, just go directly to the slow path.
130 bnez r3, hand_unalign_slow_nonuser
132 mfspr r3, SPR_SYSTEM_SAVE_K_0
134 /* Get &thread_info->unalign_jit_tmp[0] in r3. */
135 mm r3, zero, LOG2_THREAD_SIZE, 63
136 #if THREAD_SIZE < 65536
137 addli r3, r3, -(PAGE_SIZE - THREAD_INFO_UNALIGN_JIT_TMP_OFFSET)
139 addli r3, r3, -(PAGE_SIZE/2)
140 addli r3, r3, -(PAGE_SIZE/2 - THREAD_INFO_UNALIGN_JIT_TMP_OFFSET)
144 * Save r0, r1, r2 into thread_info array r3 points to
145 * from low to high memory in order.
154 /* Save stored r3 value so we can revert it on a page fault. */
155 mfspr r1, SPR_SYSTEM_SAVE_K_1
159 /* Generate a SIGBUS if sp is not 8-byte aligned. */
160 bnez r2, hand_unalign_slow_badsp
164 * Get the thread_info in r0; load r1 with pc. Set the low bit of sp
165 * as an indicator to the page fault code in case we fault.
169 mfspr r1, SPR_EX_CONTEXT_K_0
172 /* Add the jit_info offset in thread_info; extract r1 [3:9] into r2. */
174 addli r0, r3, THREAD_INFO_UNALIGN_JIT_BASE_OFFSET - \
175 (THREAD_INFO_UNALIGN_JIT_TMP_OFFSET + (3 * 8))
176 bfextu r2, r1, 3, (2 + PAGE_SHIFT - UNALIGN_JIT_SHIFT)
179 /* Load the jit_info; multiply r2 by 128. */
182 shli r2, r2, UNALIGN_JIT_SHIFT
186 * If r0 is NULL, the JIT page is not mapped, so go to slow path;
187 * add offset r2 to r0 at the same time.
190 beqz r0, hand_unalign_slow
195 * We are loading from userspace (both the JIT info PC and
196 * instruction word, and the instruction word we executed)
197 * and since either could fault while holding the interrupt
198 * critical section, we must tag this region and check it in
199 * do_page_fault() to handle it properly.
201 ENTRY(__start_unalign_asm_code)
203 /* Load first word of JIT in r0 and increment r2 by 8. */
207 * Compare the PC with the 1st word in JIT; load the fault bundle
215 /* Go to slow path if PC doesn't match. */
216 beqz r0, hand_unalign_slow
219 * Load the 2nd word of JIT, which is supposed to be the fault
220 * bundle for a cache hit. Increment r2; after this bundle r2 will
221 * point to the potential start of the JIT code we want to run.
225 /* No further accesses to userspace are done after this point. */
226 ENTRY(__end_unalign_asm_code)
228 /* Compare the real bundle with what is saved in the JIT area. */
231 mtspr SPR_EX_CONTEXT_0_1, zero
234 /* Go to slow path if the fault bundle does not match. */
235 beqz r0, hand_unalign_slow
238 * A cache hit is found.
239 * r2 points to start of JIT code (3rd word).
240 * r0 is the fault pc.
241 * r1 is the fault bundle.
242 * Reset the low bit of sp.
245 mfspr r0, SPR_EX_CONTEXT_K_0
249 /* Write r2 into EX_CONTEXT_K_0 and increment PC. */
251 mtspr SPR_EX_CONTEXT_K_0, r2
256 * Set ICS on kernel EX_CONTEXT_K_1 in order to "iret" to
257 * user with ICS set. This way, if the JIT fixup causes another
258 * unalign exception (which shouldn't be possible) the user
259 * process will be terminated with SIGBUS. Also, our fixup will
260 * run without interleaving with external interrupts.
261 * Each fixup is at most 14 bundles, so it won't hold ICS for long.
264 movei r1, PL_ICS_EX1(USER_PL, 1)
265 mtspr SPR_EX_CONTEXT_0_0, r0
269 mtspr SPR_EX_CONTEXT_K_1, r1
270 addi r3, r3, -(3 * 8)
273 /* Restore r0..r3. */
280 ENDPROC(intvec_\vecname)
283 #ifdef __COLLECT_LINKER_FEEDBACK__
284 .pushsection .text.intvec_feedback,"ax"
290 * Default interrupt handler.
292 * vecnum is where we'll put this code.
293 * c_routine is the C routine we'll call.
295 * The C routine is passed two arguments:
296 * - A pointer to the pt_regs state.
297 * - The interrupt vector number.
299 * The "processing" argument specifies the code for processing
300 * the interrupt. Defaults to "handle_interrupt".
302 .macro __int_hand vecnum, vecname, c_routine,processing=handle_interrupt
304 /* Temporarily save a register so we have somewhere to work. */
306 mtspr SPR_SYSTEM_SAVE_K_1, r0
307 mfspr r0, SPR_EX_CONTEXT_K_1
310 * The unalign data fastpath code sets the low bit in sp to
311 * force us to reset it here on fault.
315 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
318 .ifc \vecnum, INT_DOUBLE_FAULT
320 * For double-faults from user-space, fall through to the normal
321 * register save and stack setup path. Otherwise, it's the
322 * hypervisor giving us one last chance to dump diagnostics, and we
323 * branch to the kernel_double_fault routine to do so.
326 j _kernel_double_fault
330 * If we're coming from user-space, then set sp to the top of
331 * the kernel stack. Otherwise, assume sp is already valid.
339 .ifc \c_routine, do_page_fault
341 * The page_fault handler may be downcalled directly by the
342 * hypervisor even when Linux is running and has ICS set.
344 * In this case the contents of EX_CONTEXT_K_1 reflect the
345 * previous fault and can't be relied on to choose whether or
346 * not to reinitialize the stack pointer. So we add a test
347 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
348 * and if so we don't reinitialize sp, since we must be coming
349 * from Linux. (In fact the precise case is !(val & ~1),
350 * but any Linux PC has to have the high bit set.)
352 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
353 * any path that turns into a downcall to one of our TLB handlers.
355 * FIXME: if we end up never using this path, perhaps we should
356 * prevent the hypervisor from generating downcalls in this case.
357 * The advantage of getting a downcall is we can panic in Linux.
359 mfspr r0, SPR_SYSTEM_SAVE_K_2
361 bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
368 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
369 * the current stack top in the higher bits. So we recover
370 * our stack top by just masking off the low bits, then
371 * point sp at the top aligned address on the actual stack page.
373 mfspr r0, SPR_SYSTEM_SAVE_K_0
374 mm r0, zero, LOG2_THREAD_SIZE, 63
378 * Align the stack mod 64 so we can properly predict what
379 * cache lines we need to write-hint to reduce memory fetch
380 * latency as we enter the kernel. The layout of memory is
381 * as follows, with cache line 0 at the lowest VA, and cache
382 * line 8 just below the r0 value this "andi" computes.
383 * Note that we never write to cache line 8, and we skip
384 * cache lines 1-3 for syscalls.
386 * cache line 8: ptregs padding (two words)
387 * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
388 * cache line 6: r46...r53 (tp)
389 * cache line 5: r38...r45
390 * cache line 4: r30...r37
391 * cache line 3: r22...r29
392 * cache line 2: r14...r21
393 * cache line 1: r6...r13
394 * cache line 0: 2 x frame, r0..r5
399 * Push the first four registers on the stack, so that we can set
400 * them to vector-unique values before we jump to the common code.
402 * Registers are pushed on the stack as a struct pt_regs,
403 * with the sp initially just above the struct, and when we're
404 * done, sp points to the base of the struct, minus
405 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
407 * This routine saves just the first four registers, plus the
408 * stack context so we can do proper backtracing right away,
409 * and defers to handle_interrupt to save the rest.
410 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum,
411 * and needs sp set to its final location at the bottom of
414 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
415 wh64 r0 /* cache line 7 */
418 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
422 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
424 wh64 sp /* cache line 6 */
427 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
429 wh64 sp /* cache line 0 */
432 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
436 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
440 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
442 mfspr r0, SPR_EX_CONTEXT_K_0
443 .ifc \processing,handle_syscall
445 * Bump the saved PC by one bundle so that when we return, we won't
446 * execute the same swint instruction again. We need to do this while
447 * we're in the critical section.
453 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
455 mfspr r0, SPR_EX_CONTEXT_K_1
458 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
460 * Use r0 for syscalls so it's a temporary; use r1 for interrupts
461 * so that it gets passed through unchanged to the handler routine.
462 * Note that the .if conditional confusingly spans bundles.
464 .ifc \processing,handle_syscall
475 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
477 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
480 addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
483 st sp, zero /* write zero into "Next SP" frame pointer */
484 addi sp, sp, -8 /* leave SP pointing at bottom of frame */
486 .ifc \processing,handle_syscall
489 /* Capture per-interrupt SPR context to registers. */
490 .ifc \c_routine, do_page_fault
491 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
492 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
494 .ifc \vecnum, INT_ILL_TRANS
497 .ifc \vecnum, INT_DOUBLE_FAULT
498 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
500 .ifc \c_routine, do_trap
503 .ifc \c_routine, op_handle_perf_interrupt
504 mfspr r2, PERF_COUNT_STS
505 #if CHIP_HAS_AUX_PERF_COUNTERS()
507 .ifc \c_routine, op_handle_aux_perf_interrupt
508 mfspr r2, AUX_PERF_COUNT_STS
516 /* Put function pointer in r0 */
517 moveli r0, hw2_last(\c_routine)
518 shl16insli r0, r0, hw1(\c_routine)
520 shl16insli r0, r0, hw0(\c_routine)
524 ENDPROC(intvec_\vecname)
526 #ifdef __COLLECT_LINKER_FEEDBACK__
527 .pushsection .text.intvec_feedback,"ax"
529 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
538 * Save the rest of the registers that we didn't save in the actual
539 * vector itself. We can't use r0-r10 inclusive here.
541 .macro finish_interrupt_save, function
543 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
544 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
546 .ifc \function,handle_syscall
551 PTREGS_PTR(r52, PTREGS_OFFSET_TP)
555 mfspr tp, CMPEXCH_VALUE
556 PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
560 * For ordinary syscalls, we save neither caller- nor callee-
561 * save registers, since the syscall invoker doesn't expect the
562 * caller-saves to be saved, and the called kernel functions will
563 * take care of saving the callee-saves for us.
565 * For interrupts we save just the caller-save registers. Saving
566 * them is required (since the "caller" can't save them). Again,
567 * the called kernel functions will restore the callee-save
568 * registers for us appropriately.
570 * On return, we normally restore nothing special for syscalls,
571 * and just the caller-save registers for interrupts.
573 * However, there are some important caveats to all this:
575 * - We always save a few callee-save registers to give us
576 * some scratchpad registers to carry across function calls.
578 * - fork/vfork/etc require us to save all the callee-save
579 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
581 * - We always save r0..r5 and r10 for syscalls, since we need
582 * to reload them a bit later for the actual kernel call, and
583 * since we might need them for -ERESTARTNOINTR, etc.
585 * - Before invoking a signal handler, we save the unsaved
586 * callee-save registers so they are visible to the
587 * signal handler or any ptracer.
589 * - If the unsaved callee-save registers are modified, we set
590 * a bit in pt_regs so we know to reload them from pt_regs
591 * and not just rely on the kernel function unwinding.
592 * (Done for ptrace register writes and SA_SIGINFO handler.)
596 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
598 wh64 r52 /* cache line 4 */
602 .ifc \function,handle_syscall
603 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
604 push_reg TREG_SYSCALL_NR_NAME, r52, \
605 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
608 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
609 wh64 r52 /* cache line 3 */
618 wh64 r52 /* cache line 2 */
627 wh64 r52 /* cache line 1 */
643 * If we will be returning to the kernel, we will need to
644 * reset the interrupt masks to the state they had before.
645 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
647 mfspr r32, SPR_EX_CONTEXT_K_1
649 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
650 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
652 beqzt r32, 1f /* zero if from user space */
653 IRQS_DISABLED(r32) /* zero if irqs enabled */
654 #if PT_FLAGS_DISABLE_IRQ != 1
655 # error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
658 .ifnc \function,handle_syscall
659 /* Record the fact that we saved the caller-save registers above. */
660 ori r32, r32, PT_FLAGS_CALLER_SAVES
665 * we've captured enough state to the stack (including in
666 * particular our EX_CONTEXT state) that we can now release
667 * the interrupt critical section and replace it with our
668 * standard "interrupts disabled" mask value. This allows
669 * synchronous interrupts (and profile interrupts) to punch
670 * through from this point onwards.
672 * It's important that no code before this point touch memory
673 * other than our own stack (to keep the invariant that this
674 * is all that gets touched under ICS), and that no code after
675 * this point reference any interrupt-specific SPR, in particular
676 * the EX_CONTEXT_K_ values.
678 .ifc \function,handle_nmi
681 IRQ_DISABLE(r20, r21)
683 mtspr INTERRUPT_CRITICAL_SECTION, zero
685 /* Load tp with our per-cpu offset. */
688 mfspr r20, SPR_SYSTEM_SAVE_K_0
689 moveli r21, hw2_last(__per_cpu_offset)
692 shl16insli r21, r21, hw1(__per_cpu_offset)
693 bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
695 shl16insli r21, r21, hw0(__per_cpu_offset)
696 shl3add r20, r20, r21
702 #ifdef __COLLECT_LINKER_FEEDBACK__
704 * Notify the feedback routines that we were in the
705 * appropriate fixed interrupt vector area. Note that we
706 * still have ICS set at this point, so we can't invoke any
707 * atomic operations or we will panic. The feedback
708 * routines internally preserve r0..r10 and r30 up.
710 .ifnc \function,handle_syscall
713 moveli r20, INT_SWINT_1 << 5
715 moveli r21, hw2_last(intvec_feedback)
716 shl16insli r21, r21, hw1(intvec_feedback)
717 shl16insli r21, r21, hw0(intvec_feedback)
721 /* And now notify the feedback routines that we are here. */
722 FEEDBACK_ENTER(\function)
726 * Prepare the first 256 stack bytes to be rapidly accessible
727 * without having to fetch the background data.
744 #ifdef CONFIG_TRACE_IRQFLAGS
745 .ifnc \function,handle_nmi
747 * We finally have enough state set up to notify the irq
748 * tracing code that irqs were disabled on entry to the handler.
749 * The TRACE_IRQS_OFF call clobbers registers r0-r29.
750 * For syscalls, we already have the register state saved away
751 * on the stack, so we don't bother to do any register saves here,
752 * and later we pop the registers back off the kernel stack.
753 * For interrupt handlers, save r0-r3 in callee-saved registers.
755 .ifnc \function,handle_syscall
756 { move r30, r0; move r31, r1 }
757 { move r32, r2; move r33, r3 }
760 .ifnc \function,handle_syscall
761 { move r0, r30; move r1, r31 }
762 { move r2, r32; move r3, r33 }
770 * Redispatch a downcall.
772 .macro dc_dispatch vecnum, vecname
775 j hv_downcall_dispatch
776 ENDPROC(intvec_\vecname)
780 * Common code for most interrupts. The C function we're eventually
781 * going to is in r0, and the faultnum is in r1; the original
782 * values for those registers are on the stack.
784 .pushsection .text.handle_interrupt,"ax"
786 finish_interrupt_save handle_interrupt
788 /* Jump to the C routine; it should enable irqs as soon as possible. */
791 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
793 FEEDBACK_REENTER(handle_interrupt)
795 movei r30, 0 /* not an NMI */
798 STD_ENDPROC(handle_interrupt)
801 * This routine takes a boolean in r30 indicating if this is an NMI.
802 * If so, we also expect a boolean in r31 indicating whether to
803 * re-enable the oprofile interrupts.
805 * Note that .Lresume_userspace is jumped to directly in several
806 * places, and we need to make sure r30 is set correctly in those
809 STD_ENTRY(interrupt_return)
810 /* If we're resuming to kernel space, don't check thread flags. */
812 bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
813 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
816 andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
818 beqzt r29, .Lresume_userspace
822 #ifdef CONFIG_PREEMPT
823 /* Returning to kernel space. Check if we need preemption. */
824 EXTRACT_THREAD_INFO(r29)
825 addli r28, r29, THREAD_INFO_FLAGS_OFFSET
828 addli r29, r29, THREAD_INFO_PREEMPT_COUNT_OFFSET
831 andi r28, r28, _TIF_NEED_RESCHED
836 jal preempt_schedule_irq
837 FEEDBACK_REENTER(interrupt_return)
841 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
843 moveli r27, hw2_last(_cpu_idle_nap)
844 PTREGS_PTR(r29, PTREGS_OFFSET_PC)
848 shl16insli r27, r27, hw1(_cpu_idle_nap)
851 shl16insli r27, r27, hw0(_cpu_idle_nap)
857 blbc r27, .Lrestore_all
864 FEEDBACK_REENTER(interrupt_return)
867 * Use r33 to hold whether we have already loaded the callee-saves
868 * into ptregs. We don't want to do it twice in this loop, since
869 * then we'd clobber whatever changes are made by ptrace, etc.
876 /* Get base of stack in r32. */
877 EXTRACT_THREAD_INFO(r32)
879 .Lretry_work_pending:
881 * Disable interrupts so as to make sure we don't
882 * miss an interrupt that sets any of the thread flags (like
883 * need_resched or sigpending) between sampling and the iret.
884 * Routines like schedule() or do_signal() may re-enable
885 * interrupts before returning.
887 IRQ_DISABLE(r20, r21)
888 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
891 /* Check to see if there is any work to do before returning to user. */
893 addi r29, r32, THREAD_INFO_FLAGS_OFFSET
894 moveli r1, hw1_last(_TIF_ALLWORK_MASK)
898 shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
901 beqzt r1, .Lrestore_all
904 * Make sure we have all the registers saved for signal
905 * handling or notify-resume. Call out to C code to figure out
906 * exactly what we need to do for each flag bit, then if
907 * necessary, reload the flags and recheck.
910 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
913 push_extra_callee_saves r0
915 1: jal do_work_pending
916 bnez r0, .Lretry_work_pending
920 * omit the call to single_process_check_nohz, which normally checks
921 * to see if we should start or stop the scheduler tick, because
922 * we can't call arbitrary Linux code from an NMI context.
923 * We always call the homecache TLB deferral code to re-trigger
924 * the deferral mechanism.
926 * The other chunk of responsibility this code has is to reset the
927 * interrupt masks appropriately to reset irqs and NMIs. We have
928 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
929 * lockdep-type stuff, but we can't set ICS until afterwards, since
930 * ICS can only be used in very tight chunks of code to avoid
931 * tripping over various assertions that it is off.
934 PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
937 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
940 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
945 #if PT_FLAGS_DISABLE_IRQ != 1
946 # error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
952 mtspr INTERRUPT_CRITICAL_SECTION, r0
953 beqzt r30, .Lrestore_regs
956 IRQ_ENABLE_LOAD(r20, r21)
958 mtspr INTERRUPT_CRITICAL_SECTION, r0
959 IRQ_ENABLE_APPLY(r20, r21)
960 beqzt r30, .Lrestore_regs
965 * We now commit to returning from this interrupt, since we will be
966 * doing things like setting EX_CONTEXT SPRs and unwinding the stack
967 * frame. No calls should be made to any other code after this point.
968 * This code should only be entered with ICS set.
969 * r32 must still be set to ptregs.flags.
970 * We launch loads to each cache line separately first, so we can
971 * get some parallelism out of the memory subsystem.
972 * We start zeroing caller-saved registers throughout, since
973 * that will save some cycles if this turns out to be a syscall.
978 * Rotate so we have one high bit and one low bit to test.
979 * - low bit says whether to restore all the callee-saved registers,
980 * or just r30-r33, and r52 up.
981 * - high bit (i.e. sign bit) says whether to restore all the
982 * caller-saved registers, or just r0.
984 #if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
985 # error Rotate trick does not work :-)
989 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
993 * Load cache lines 0, 4, 6 and 7, in that order, then use
994 * the last loaded value, which makes it likely that the other
995 * cache lines have also loaded, at which point we should be
996 * able to safely read all the remaining words on those cache
997 * lines without waiting for the memory subsystem.
999 pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
1000 pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
1001 pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
1002 pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
1003 pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
1005 mtspr CMPEXCH_VALUE, r21
1008 pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
1010 mtspr SPR_EX_CONTEXT_K_1, lr
1011 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
1014 mtspr SPR_EX_CONTEXT_K_0, r21
1018 /* Restore callee-saveds that we actually use. */
1019 pop_reg_zero r31, r6
1020 pop_reg_zero r32, r7
1021 pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
1024 * If we modified other callee-saveds, restore them now.
1025 * This is rare, but could be via ptrace or signal handler.
1029 blbs r20, .Lrestore_callees
1031 .Lcontinue_restore_regs:
1033 /* Check if we're returning from a syscall. */
1036 bltzt r20, 1f /* no, so go restore callee-save registers */
1040 * Check if we're returning to userspace.
1041 * Note that if we're not, we don't worry about zeroing everything.
1044 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
1045 bnez lr, .Lkernel_return
1049 * On return from syscall, we've restored r0 from pt_regs, but we
1050 * clear the remainder of the caller-saved registers. We could
1051 * restore the syscall arguments, but there's not much point,
1052 * and it ensures user programs aren't trying to use the
1053 * caller-saves if we clear them, as well as avoiding leaking
1054 * kernel pointers into userspace.
1056 pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
1057 pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
1063 { move r15, zero; move r16, zero }
1064 { move r17, zero; move r18, zero }
1065 { move r19, zero; move r20, zero }
1066 { move r21, zero; move r22, zero }
1067 { move r23, zero; move r24, zero }
1068 { move r25, zero; move r26, zero }
1070 /* Set r1 to errno if we are returning an error, otherwise zero. */
1086 * Not a syscall, so restore caller-saved registers.
1087 * First kick off loads for cache lines 1-3, which we're touching
1088 * for the first time here.
1091 1: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
1092 pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
1093 pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
1106 /* r13 already restored above */
1114 /* r21 already restored above */
1121 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
1122 /* r29 already restored above */
1123 bnez lr, .Lkernel_return
1124 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
1125 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
1130 * We can't restore tp when in kernel mode, since a thread might
1131 * have migrated from another cpu and brought a stale tp value.
1134 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
1138 /* Restore callee-saved registers from r34 to r51. */
1140 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
1158 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
1159 j .Lcontinue_restore_regs
1160 STD_ENDPROC(interrupt_return)
1163 * "NMI" interrupts mask ALL interrupts before calling the
1164 * handler, and don't check thread flags, etc., on the way
1165 * back out. In general, the only things we do here for NMIs
1166 * are register save/restore and dataplane kernel-TLB management.
1167 * We don't (for example) deal with start/stop of the sched tick.
1169 .pushsection .text.handle_nmi,"ax"
1171 finish_interrupt_save handle_nmi
1174 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1176 FEEDBACK_REENTER(handle_nmi)
1182 STD_ENDPROC(handle_nmi)
1185 * Parallel code for syscalls to handle_interrupt.
1187 .pushsection .text.handle_syscall,"ax"
1189 finish_interrupt_save handle_syscall
1193 IRQ_ENABLE(r20, r21)
1195 /* Bump the counter for syscalls made on this tile. */
1196 moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1197 shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1198 shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
1207 EXTRACT_THREAD_INFO(r31)
1210 /* Trace syscalls, if requested. */
1211 addi r31, r31, THREAD_INFO_FLAGS_OFFSET
1214 moveli r32, _TIF_SYSCALL_ENTRY_WORK
1218 addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
1219 beqzt r30, .Lrestore_syscall_regs
1222 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1223 jal do_syscall_trace_enter
1225 FEEDBACK_REENTER(handle_syscall)
1228 * We always reload our registers from the stack at this
1229 * point. They might be valid, if we didn't build with
1230 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
1231 * doing syscall tracing, but there are enough cases now that it
1232 * seems simplest just to do the reload unconditionally.
1234 .Lrestore_syscall_regs:
1237 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
1244 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
1246 ld TREG_SYSCALL_NR_NAME, r11
1247 moveli r21, __NR_syscalls
1250 /* Ensure that the syscall number is within the legal range. */
1252 moveli r20, hw2(sys_call_table)
1253 #ifdef CONFIG_COMPAT
1254 blbs r30, .Lcompat_syscall
1258 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1259 shl16insli r20, r20, hw1(sys_call_table)
1262 blbc r21, .Linvalid_syscall
1263 shl16insli r20, r20, hw0(sys_call_table)
1265 .Lload_syscall_pointer:
1266 shl3add r20, TREG_SYSCALL_NR_NAME, r20
1269 /* Jump to syscall handler. */
1271 .Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1274 * Write our r0 onto the stack so it gets restored instead
1275 * of whatever the user had there before.
1276 * In compat mode, sign-extend r0 before storing it.
1279 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1285 .Lsyscall_sigreturn_skip:
1286 FEEDBACK_REENTER(handle_syscall)
1288 /* Do syscall trace again, if requested. */
1291 moveli r32, _TIF_SYSCALL_EXIT_WORK
1295 andi r0, r30, _TIF_SINGLESTEP
1299 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1300 jal do_syscall_trace_exit
1302 FEEDBACK_REENTER(handle_syscall)
1303 andi r0, r30, _TIF_SINGLESTEP
1307 /* Single stepping -- notify ptrace. */
1312 FEEDBACK_REENTER(handle_syscall)
1315 movei r30, 0 /* not an NMI */
1316 j .Lresume_userspace /* jump into middle of interrupt_return */
1319 #ifdef CONFIG_COMPAT
1322 * Load the base of the compat syscall table in r20, and
1323 * range-check the syscall number (duplicated from 64-bit path).
1324 * Sign-extend all the user's passed arguments to make them consistent.
1325 * Also save the original "r(n)" values away in "r(11+n)" in
1326 * case the syscall table entry wants to validate them.
1328 moveli r20, hw2(compat_sys_call_table)
1330 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1331 shl16insli r20, r20, hw1(compat_sys_call_table)
1334 blbc r21, .Linvalid_syscall
1335 shl16insli r20, r20, hw0(compat_sys_call_table)
1337 { move r11, r0; addxi r0, r0, 0 }
1338 { move r12, r1; addxi r1, r1, 0 }
1339 { move r13, r2; addxi r2, r2, 0 }
1340 { move r14, r3; addxi r3, r3, 0 }
1341 { move r15, r4; addxi r4, r4, 0 }
1342 { move r16, r5; addxi r5, r5, 0 }
1343 j .Lload_syscall_pointer
1347 /* Report an invalid syscall back to the user program */
1349 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1354 movei r30, 0 /* not an NMI */
1355 j .Lresume_userspace /* jump into middle of interrupt_return */
1357 STD_ENDPROC(handle_syscall)
1359 /* Return the address for oprofile to suppress in backtraces. */
1360 STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
1363 addli r0, r0, .Lhandle_syscall_link - .
1366 STD_ENDPROC(handle_syscall_link_address)
1368 STD_ENTRY(ret_from_fork)
1371 FEEDBACK_REENTER(ret_from_fork)
1373 movei r30, 0 /* not an NMI */
1374 j .Lresume_userspace /* jump into middle of interrupt_return */
1376 STD_ENDPROC(ret_from_fork)
1378 STD_ENTRY(ret_from_kernel_thread)
1381 FEEDBACK_REENTER(ret_from_fork)
1386 FEEDBACK_REENTER(ret_from_kernel_thread)
1388 movei r30, 0 /* not an NMI */
1389 j .Lresume_userspace /* jump into middle of interrupt_return */
1391 STD_ENDPROC(ret_from_kernel_thread)
1393 /* Various stub interrupt handlers and syscall handlers */
1395 STD_ENTRY_LOCAL(_kernel_double_fault)
1396 mfspr r1, SPR_EX_CONTEXT_K_0
1400 addi sp, sp, -C_ABI_SAVE_AREA_SIZE
1401 j kernel_double_fault
1402 STD_ENDPROC(_kernel_double_fault)
1404 STD_ENTRY_LOCAL(bad_intr)
1405 mfspr r2, SPR_EX_CONTEXT_K_0
1406 panic "Unhandled interrupt %#x: PC %#lx"
1407 STD_ENDPROC(bad_intr)
1410 * Special-case sigreturn to not write r0 to the stack on return.
1411 * This is technically more efficient, but it also avoids difficulties
1412 * in the 64-bit OS when handling 32-bit compat code, since we must not
1413 * sign-extend r0 for the sigreturn return-value case.
1415 #define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1417 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1419 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1424 PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1425 #ifdef CONFIG_COMPAT
1426 PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
1429 /* Save additional callee-saves to pt_regs and jump to standard function. */
1430 STD_ENTRY(_sys_clone)
1431 push_extra_callee_saves r4
1433 STD_ENDPROC(_sys_clone)
1436 * Recover r3, r2, r1 and r0 here saved by unalign fast vector.
1437 * The vector area limit is 32 bundles, so we handle the reload here.
1438 * r0, r1, r2 are in thread_info from low to high memory in order.
1439 * r3 points to location the original r3 was saved.
1440 * We put this code in the __HEAD section so it can be reached
1441 * via a conditional branch from the fast path.
1446 hand_unalign_slow_badsp:
1447 addi r3, r3, -(3 * 8)
1451 hand_unalign_slow_nonuser:
1452 mfspr r3, SPR_SYSTEM_SAVE_K_1
1453 __int_hand INT_UNALIGN_DATA, UNALIGN_DATA_SLOW, int_unalign
1455 /* The unaligned data support needs to read all the registers. */
1457 push_extra_callee_saves r0
1459 ENDPROC(hand_unalign_slow)
1461 /* Fill the return address stack with nonzero entries. */
1462 STD_ENTRY(fill_ra_stack)
1471 STD_ENDPROC(fill_ra_stack)
1473 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
1475 __int_hand \vecnum, \vecname, \c_routine, \processing
1478 /* Include .intrpt1 array of interrupt vectors */
1479 .section ".intrpt1", "ax"
1481 #define op_handle_perf_interrupt bad_intr
1482 #define op_handle_aux_perf_interrupt bad_intr
1484 #ifndef CONFIG_HARDWALL
1485 #define do_hardwall_trap bad_intr
1488 int_hand INT_MEM_ERROR, MEM_ERROR, do_trap
1489 int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
1490 #if CONFIG_KERNEL_PL == 2
1491 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
1492 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
1494 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
1495 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
1497 int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
1498 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
1499 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
1500 int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
1501 int_hand INT_ILL, ILL, do_trap
1502 int_hand INT_GPV, GPV, do_trap
1503 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
1504 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
1505 int_hand INT_SWINT_3, SWINT_3, do_trap
1506 int_hand INT_SWINT_2, SWINT_2, do_trap
1507 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
1508 int_hand INT_SWINT_0, SWINT_0, do_trap
1509 int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
1510 int_hand_unalign_fast INT_UNALIGN_DATA, UNALIGN_DATA
1511 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
1512 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
1513 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, do_hardwall_trap
1514 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
1515 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
1516 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
1517 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
1518 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
1519 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
1520 int_hand INT_IPI_3, IPI_3, bad_intr
1521 #if CONFIG_KERNEL_PL == 2
1522 int_hand INT_IPI_2, IPI_2, tile_dev_intr
1523 int_hand INT_IPI_1, IPI_1, bad_intr
1525 int_hand INT_IPI_2, IPI_2, bad_intr
1526 int_hand INT_IPI_1, IPI_1, tile_dev_intr
1528 int_hand INT_IPI_0, IPI_0, bad_intr
1529 int_hand INT_PERF_COUNT, PERF_COUNT, \
1530 op_handle_perf_interrupt, handle_nmi
1531 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
1532 op_handle_perf_interrupt, handle_nmi
1533 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
1534 #if CONFIG_KERNEL_PL == 2
1535 dc_dispatch INT_INTCTRL_2, INTCTRL_2
1536 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
1538 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
1539 dc_dispatch INT_INTCTRL_1, INTCTRL_1
1541 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
1542 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
1544 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
1545 int_hand INT_I_ASID, I_ASID, bad_intr
1546 int_hand INT_D_ASID, D_ASID, bad_intr
1547 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
1549 /* Synthetic interrupt delivered only by the simulator */
1550 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint