1 #ifndef _ASM_X86_AMD_NB_H
2 #define _ASM_X86_AMD_NB_H
4 #include <linux/ioport.h>
7 struct amd_nb_bus_dev_range {
13 extern const struct pci_device_id amd_nb_misc_ids[];
14 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
16 extern bool early_is_amd_nb(u32 value);
17 extern struct resource *amd_get_mmconfig_range(struct resource *res);
18 extern int amd_cache_northbridges(void);
19 extern void amd_flush_garts(void);
20 extern int amd_numa_init(void);
21 extern int amd_get_subcaches(int);
22 extern int amd_set_subcaches(int, int);
29 struct threshold_block {
35 bool interrupt_capable;
38 struct list_head miscj;
41 struct threshold_bank {
43 struct threshold_block *blocks;
45 /* initialized to the number of CPUs on the node sharing this bank */
49 struct amd_northbridge {
52 struct amd_l3_cache l3_cache;
53 struct threshold_bank *bank4;
56 struct amd_northbridge_info {
59 struct amd_northbridge *nb;
61 extern struct amd_northbridge_info amd_northbridges;
63 #define AMD_NB_GART BIT(0)
64 #define AMD_NB_L3_INDEX_DISABLE BIT(1)
65 #define AMD_NB_L3_PARTITIONING BIT(2)
69 static inline u16 amd_nb_num(void)
71 return amd_northbridges.num;
74 static inline bool amd_nb_has_feature(unsigned feature)
76 return ((amd_northbridges.flags & feature) == feature);
79 static inline struct amd_northbridge *node_to_amd_nb(int node)
81 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
84 static inline u16 amd_get_node_id(struct pci_dev *pdev)
89 for (i = 0; i != amd_nb_num(); i++) {
90 misc = node_to_amd_nb(i)->misc;
92 if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
93 PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
97 WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
103 #define amd_nb_num(x) 0
104 #define amd_nb_has_feature(x) false
105 #define node_to_amd_nb(x) NULL
110 #endif /* _ASM_X86_AMD_NB_H */