1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
27 * Define the default level of output to be very little
28 * This can be turned up by using apic=verbose for more
29 * information and apic=debug for _lots_ of information.
30 * apic_verbosity is defined in apic.c
32 #define apic_printk(v, s, a...) do { \
33 if ((v) <= apic_verbosity) \
38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
39 extern void generic_apic_probe(void);
41 static inline void generic_apic_probe(void)
46 #ifdef CONFIG_X86_LOCAL_APIC
48 extern unsigned int apic_verbosity;
49 extern int local_apic_timer_c2_ok;
51 extern int disable_apic;
52 extern unsigned int lapic_timer_frequency;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
76 static inline bool apic_from_smp_config(void)
78 return smp_found_config && !disable_apic;
82 * Basic functions accessing APICs.
84 #ifdef CONFIG_PARAVIRT
85 #include <asm/paravirt.h>
89 extern int is_vsmp_box(void);
91 static inline int is_vsmp_box(void)
96 extern int setup_profiling_timer(unsigned int);
98 static inline void native_apic_mem_write(u32 reg, u32 v)
100 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
102 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
103 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
104 ASM_OUTPUT2("0" (v), "m" (*addr)));
107 static inline u32 native_apic_mem_read(u32 reg)
109 return *((volatile u32 *)(APIC_BASE + reg));
112 extern void native_apic_wait_icr_idle(void);
113 extern u32 native_safe_apic_wait_icr_idle(void);
114 extern void native_apic_icr_write(u32 low, u32 id);
115 extern u64 native_apic_icr_read(void);
117 extern int x2apic_mode;
119 #ifdef CONFIG_X86_X2APIC
121 * Make previous memory operations globally visible before
122 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
125 static inline void x2apic_wrmsr_fence(void)
127 asm volatile("mfence" : : : "memory");
130 static inline void native_apic_msr_write(u32 reg, u32 v)
132 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
136 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
139 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
141 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
144 static inline u32 native_apic_msr_read(u32 reg)
151 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
155 static inline void native_x2apic_wait_icr_idle(void)
157 /* no need to wait for icr idle in x2apic */
161 static inline u32 native_safe_x2apic_wait_icr_idle(void)
163 /* no need to wait for icr idle in x2apic */
167 static inline void native_x2apic_icr_write(u32 low, u32 id)
169 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
172 static inline u64 native_x2apic_icr_read(void)
176 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
180 extern int x2apic_phys;
181 extern int x2apic_preenabled;
182 extern void check_x2apic(void);
183 extern void enable_x2apic(void);
184 static inline int x2apic_enabled(void)
191 rdmsrl(MSR_IA32_APICBASE, msr);
192 if (msr & X2APIC_ENABLE)
197 #define x2apic_supported() (cpu_has_x2apic)
198 static inline void x2apic_force_phys(void)
203 static inline void disable_x2apic(void)
206 static inline void check_x2apic(void)
209 static inline void enable_x2apic(void)
212 static inline int x2apic_enabled(void)
216 static inline void x2apic_force_phys(void)
220 #define x2apic_preenabled 0
221 #define x2apic_supported() 0
224 extern void enable_IR_x2apic(void);
226 extern int get_physical_broadcast(void);
228 extern int lapic_get_maxlvt(void);
229 extern void clear_local_APIC(void);
230 extern void connect_bsp_APIC(void);
231 extern void disconnect_bsp_APIC(int virt_wire_setup);
232 extern void disable_local_APIC(void);
233 extern void lapic_shutdown(void);
234 extern int verify_local_APIC(void);
235 extern void sync_Arb_IDs(void);
236 extern void init_bsp_APIC(void);
237 extern void setup_local_APIC(void);
238 extern void end_local_APIC_setup(void);
239 extern void bsp_end_local_APIC_setup(void);
240 extern void init_apic_mappings(void);
241 void register_lapic_address(unsigned long address);
242 extern void setup_boot_APIC_clock(void);
243 extern void setup_secondary_APIC_clock(void);
244 extern int APIC_init_uniprocessor(void);
245 extern int apic_force_enable(unsigned long addr);
248 * On 32bit this is mach-xxx local
251 extern int apic_is_clustered_box(void);
253 static inline int apic_is_clustered_box(void)
259 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
261 #else /* !CONFIG_X86_LOCAL_APIC */
262 static inline void lapic_shutdown(void) { }
263 #define local_apic_timer_c2_ok 1
264 static inline void init_apic_mappings(void) { }
265 static inline void disable_local_APIC(void) { }
266 # define setup_boot_APIC_clock x86_init_noop
267 # define setup_secondary_APIC_clock x86_init_noop
268 #endif /* !CONFIG_X86_LOCAL_APIC */
271 #define SET_APIC_ID(x) (apic->set_apic_id(x))
277 * Copyright 2004 James Cleverdon, IBM.
278 * Subject to the GNU Public License, v.2
280 * Generic APIC sub-arch data struct.
282 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
283 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
290 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
291 int (*apic_id_valid)(int apicid);
292 int (*apic_id_registered)(void);
294 u32 irq_delivery_mode;
297 const struct cpumask *(*target_cpus)(void);
302 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
303 unsigned long (*check_apicid_present)(int apicid);
305 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
306 const struct cpumask *mask);
307 void (*init_apic_ldr)(void);
309 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
311 void (*setup_apic_routing)(void);
312 int (*multi_timer_check)(int apic, int irq);
313 int (*cpu_present_to_apicid)(int mps_cpu);
314 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
315 void (*setup_portio_remap)(void);
316 int (*check_phys_apicid_present)(int phys_apicid);
317 void (*enable_apic_mode)(void);
318 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
321 * When one of the next two hooks returns 1 the apic
322 * is switched to this. Essentially they are additional
325 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
327 unsigned int (*get_apic_id)(unsigned long x);
328 unsigned long (*set_apic_id)(unsigned int id);
329 unsigned long apic_id_mask;
331 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
332 const struct cpumask *andmask,
333 unsigned int *apicid);
336 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
337 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
339 void (*send_IPI_allbutself)(int vector);
340 void (*send_IPI_all)(int vector);
341 void (*send_IPI_self)(int vector);
343 /* wakeup_secondary_cpu */
344 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
346 int trampoline_phys_low;
347 int trampoline_phys_high;
349 bool wait_for_init_deassert;
350 void (*smp_callin_clear_local_apic)(void);
351 void (*inquire_remote_apic)(int apicid);
354 u32 (*read)(u32 reg);
355 void (*write)(u32 reg, u32 v);
357 * ->eoi_write() has the same signature as ->write().
359 * Drivers can support both ->eoi_write() and ->write() by passing the same
360 * callback value. Kernel can override ->eoi_write() and fall back
363 void (*eoi_write)(u32 reg, u32 v);
364 u64 (*icr_read)(void);
365 void (*icr_write)(u32 low, u32 high);
366 void (*wait_icr_idle)(void);
367 u32 (*safe_wait_icr_idle)(void);
371 * Called very early during boot from get_smp_config(). It should
372 * return the logical apicid. x86_[bios]_cpu_to_apicid is
373 * initialized before this function is called.
375 * If logical apicid can't be determined that early, the function
376 * may return BAD_APICID. Logical apicid will be configured after
377 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
378 * won't be applied properly during early boot in this case.
380 int (*x86_32_early_logical_apicid)(int cpu);
383 * Optional method called from setup_local_APIC() after logical
384 * apicid is guaranteed to be known to initialize apicid -> node
385 * mapping if NUMA initialization hasn't done so already. Don't
388 int (*x86_32_numa_cpu_node)(int cpu);
393 * Pointer to the local APIC driver in use on this system (there's
394 * always just one such driver in use - the kernel decides via an
395 * early probing process which one it picks - and then sticks to it):
397 extern struct apic *apic;
400 * APIC drivers are probed based on how they are listed in the .apicdrivers
401 * section. So the order is important and enforced by the ordering
402 * of different apic driver files in the Makefile.
404 * For the files having two apic drivers, we use apic_drivers()
405 * to enforce the order with in them.
407 #define apic_driver(sym) \
408 static const struct apic *__apicdrivers_##sym __used \
409 __aligned(sizeof(struct apic *)) \
410 __section(.apicdrivers) = { &sym }
412 #define apic_drivers(sym1, sym2) \
413 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
414 __aligned(sizeof(struct apic *)) \
415 __section(.apicdrivers) = { &sym1, &sym2 }
417 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
420 * APIC functionality to boot other CPUs - only used on SMP:
423 extern atomic_t init_deasserted;
424 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
427 #ifdef CONFIG_X86_LOCAL_APIC
429 static inline u32 apic_read(u32 reg)
431 return apic->read(reg);
434 static inline void apic_write(u32 reg, u32 val)
436 apic->write(reg, val);
439 static inline void apic_eoi(void)
441 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
444 static inline u64 apic_icr_read(void)
446 return apic->icr_read();
449 static inline void apic_icr_write(u32 low, u32 high)
451 apic->icr_write(low, high);
454 static inline void apic_wait_icr_idle(void)
456 apic->wait_icr_idle();
459 static inline u32 safe_apic_wait_icr_idle(void)
461 return apic->safe_wait_icr_idle();
464 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
466 #else /* CONFIG_X86_LOCAL_APIC */
468 static inline u32 apic_read(u32 reg) { return 0; }
469 static inline void apic_write(u32 reg, u32 val) { }
470 static inline void apic_eoi(void) { }
471 static inline u64 apic_icr_read(void) { return 0; }
472 static inline void apic_icr_write(u32 low, u32 high) { }
473 static inline void apic_wait_icr_idle(void) { }
474 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
475 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
477 #endif /* CONFIG_X86_LOCAL_APIC */
479 static inline void ack_APIC_irq(void)
482 * ack_APIC_irq() actually gets compiled as a single instruction
488 static inline unsigned default_get_apic_id(unsigned long x)
490 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
492 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
493 return (x >> 24) & 0xFF;
495 return (x >> 24) & 0x0F;
499 * Warm reset vector default position:
501 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
502 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
505 extern int default_acpi_madt_oem_check(char *, char *);
507 extern void apic_send_IPI_self(int vector);
509 DECLARE_PER_CPU(int, x2apic_extra_bits);
511 extern int default_cpu_present_to_apicid(int mps_cpu);
512 extern int default_check_phys_apicid_present(int phys_apicid);
515 extern void generic_bigsmp_probe(void);
518 #ifdef CONFIG_X86_LOCAL_APIC
522 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
524 static inline const struct cpumask *default_target_cpus(void)
527 return cpu_online_mask;
529 return cpumask_of(0);
533 static inline const struct cpumask *online_target_cpus(void)
535 return cpu_online_mask;
538 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
541 static inline unsigned int read_apic_id(void)
545 reg = apic_read(APIC_ID);
547 return apic->get_apic_id(reg);
550 static inline int default_apic_id_valid(int apicid)
552 return (apicid < 255);
555 extern void default_setup_apic_routing(void);
557 extern struct apic apic_noop;
561 static inline int noop_x86_32_early_logical_apicid(int cpu)
567 * Set up the logical destination ID.
569 * Intel recommends to set DFR, LDR and TPR before enabling
570 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
571 * document number 292116). So here it goes...
573 extern void default_init_apic_ldr(void);
575 static inline int default_apic_id_registered(void)
577 return physid_isset(read_apic_id(), phys_cpu_present_map);
580 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
582 return cpuid_apic >> index_msb;
588 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
589 const struct cpumask *andmask,
590 unsigned int *apicid)
592 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
593 cpumask_bits(andmask)[0] &
594 cpumask_bits(cpu_online_mask)[0] &
597 if (likely(cpu_mask)) {
598 *apicid = (unsigned int)cpu_mask;
606 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
607 const struct cpumask *andmask,
608 unsigned int *apicid);
611 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
612 const struct cpumask *mask)
614 /* Careful. Some cpus do not strictly honor the set of cpus
615 * specified in the interrupt destination when using lowest
616 * priority interrupt delivery mode.
618 * In particular there was a hyperthreading cpu observed to
619 * deliver interrupts to the wrong hyperthread when only one
620 * hyperthread was specified in the interrupt desitination.
622 cpumask_clear(retmask);
623 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
627 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
628 const struct cpumask *mask)
630 cpumask_copy(retmask, cpumask_of(cpu));
633 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
635 return physid_isset(apicid, *map);
638 static inline unsigned long default_check_apicid_present(int bit)
640 return physid_isset(bit, phys_cpu_present_map);
643 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
648 static inline int __default_cpu_present_to_apicid(int mps_cpu)
650 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
651 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
657 __default_check_phys_apicid_present(int phys_apicid)
659 return physid_isset(phys_apicid, phys_cpu_present_map);
663 static inline int default_cpu_present_to_apicid(int mps_cpu)
665 return __default_cpu_present_to_apicid(mps_cpu);
669 default_check_phys_apicid_present(int phys_apicid)
671 return __default_check_phys_apicid_present(phys_apicid);
674 extern int default_cpu_present_to_apicid(int mps_cpu);
675 extern int default_check_phys_apicid_present(int phys_apicid);
678 #endif /* CONFIG_X86_LOCAL_APIC */
679 extern void irq_enter(void);
680 extern void irq_exit(void);
682 static inline void entering_irq(void)
688 static inline void entering_ack_irq(void)
694 static inline void exiting_irq(void)
699 static inline void exiting_ack_irq(void)
702 /* Ack only at the end to avoid potential reentry */
706 extern void ioapic_zap_locks(void);
708 #endif /* _ASM_X86_APIC_H */