1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
27 * Define the default level of output to be very little
28 * This can be turned up by using apic=verbose for more
29 * information and apic=debug for _lots_ of information.
30 * apic_verbosity is defined in apic.c
32 #define apic_printk(v, s, a...) do { \
33 if ((v) <= apic_verbosity) \
38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
39 extern void generic_apic_probe(void);
41 static inline void generic_apic_probe(void)
46 #ifdef CONFIG_X86_LOCAL_APIC
48 extern unsigned int apic_verbosity;
49 extern int local_apic_timer_c2_ok;
51 extern int disable_apic;
52 extern unsigned int lapic_timer_frequency;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
76 static inline bool apic_from_smp_config(void)
78 return smp_found_config && !disable_apic;
82 * Basic functions accessing APICs.
84 #ifdef CONFIG_PARAVIRT
85 #include <asm/paravirt.h>
88 extern int setup_profiling_timer(unsigned int);
90 static inline void native_apic_mem_write(u32 reg, u32 v)
92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
95 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
96 ASM_OUTPUT2("0" (v), "m" (*addr)));
99 static inline u32 native_apic_mem_read(u32 reg)
101 return *((volatile u32 *)(APIC_BASE + reg));
104 extern void native_apic_wait_icr_idle(void);
105 extern u32 native_safe_apic_wait_icr_idle(void);
106 extern void native_apic_icr_write(u32 low, u32 id);
107 extern u64 native_apic_icr_read(void);
109 static inline bool apic_is_x2apic_enabled(void)
113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
115 return msr & X2APIC_ENABLE;
118 #ifdef CONFIG_X86_X2APIC
120 * Make previous memory operations globally visible before
121 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
124 static inline void x2apic_wrmsr_fence(void)
126 asm volatile("mfence" : : : "memory");
129 static inline void native_apic_msr_write(u32 reg, u32 v)
131 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
135 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
138 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
140 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
143 static inline u32 native_apic_msr_read(u32 reg)
150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
154 static inline void native_x2apic_wait_icr_idle(void)
156 /* no need to wait for icr idle in x2apic */
160 static inline u32 native_safe_x2apic_wait_icr_idle(void)
162 /* no need to wait for icr idle in x2apic */
166 static inline void native_x2apic_icr_write(u32 low, u32 id)
168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
171 static inline u64 native_x2apic_icr_read(void)
175 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
179 extern int x2apic_mode;
180 extern int x2apic_phys;
181 extern void __init check_x2apic(void);
182 extern void x2apic_setup(void);
183 static inline int x2apic_enabled(void)
185 return cpu_has_x2apic && apic_is_x2apic_enabled();
188 #define x2apic_supported() (cpu_has_x2apic)
190 static inline void check_x2apic(void) { }
191 static inline void x2apic_setup(void) { }
192 static inline int x2apic_enabled(void) { return 0; }
194 #define x2apic_mode (0)
195 #define x2apic_supported() (0)
198 extern void enable_IR_x2apic(void);
200 extern int get_physical_broadcast(void);
202 extern int lapic_get_maxlvt(void);
203 extern void clear_local_APIC(void);
204 extern void disconnect_bsp_APIC(int virt_wire_setup);
205 extern void disable_local_APIC(void);
206 extern void lapic_shutdown(void);
207 extern int verify_local_APIC(void);
208 extern void sync_Arb_IDs(void);
209 extern void init_bsp_APIC(void);
210 extern void setup_local_APIC(void);
211 extern void init_apic_mappings(void);
212 void register_lapic_address(unsigned long address);
213 extern void setup_boot_APIC_clock(void);
214 extern void setup_secondary_APIC_clock(void);
215 extern int APIC_init_uniprocessor(void);
216 extern int apic_force_enable(unsigned long addr);
218 extern int apic_bsp_setup(void);
219 extern void apic_ap_setup(void);
222 * On 32bit this is mach-xxx local
225 extern int apic_is_clustered_box(void);
227 static inline int apic_is_clustered_box(void)
233 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
235 #else /* !CONFIG_X86_LOCAL_APIC */
236 static inline void lapic_shutdown(void) { }
237 #define local_apic_timer_c2_ok 1
238 static inline void init_apic_mappings(void) { }
239 static inline void disable_local_APIC(void) { }
240 # define setup_boot_APIC_clock x86_init_noop
241 # define setup_secondary_APIC_clock x86_init_noop
242 #endif /* !CONFIG_X86_LOCAL_APIC */
245 #define SET_APIC_ID(x) (apic->set_apic_id(x))
251 * Copyright 2004 James Cleverdon, IBM.
252 * Subject to the GNU Public License, v.2
254 * Generic APIC sub-arch data struct.
256 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
257 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
264 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
265 int (*apic_id_valid)(int apicid);
266 int (*apic_id_registered)(void);
268 u32 irq_delivery_mode;
271 const struct cpumask *(*target_cpus)(void);
276 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
278 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
279 const struct cpumask *mask);
280 void (*init_apic_ldr)(void);
282 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
284 void (*setup_apic_routing)(void);
285 int (*cpu_present_to_apicid)(int mps_cpu);
286 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
287 int (*check_phys_apicid_present)(int phys_apicid);
288 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
290 unsigned int (*get_apic_id)(unsigned long x);
291 unsigned long (*set_apic_id)(unsigned int id);
292 unsigned long apic_id_mask;
294 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
295 const struct cpumask *andmask,
296 unsigned int *apicid);
299 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
300 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
302 void (*send_IPI_allbutself)(int vector);
303 void (*send_IPI_all)(int vector);
304 void (*send_IPI_self)(int vector);
306 /* wakeup_secondary_cpu */
307 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
309 bool wait_for_init_deassert;
310 void (*inquire_remote_apic)(int apicid);
313 u32 (*read)(u32 reg);
314 void (*write)(u32 reg, u32 v);
316 * ->eoi_write() has the same signature as ->write().
318 * Drivers can support both ->eoi_write() and ->write() by passing the same
319 * callback value. Kernel can override ->eoi_write() and fall back
322 void (*eoi_write)(u32 reg, u32 v);
323 u64 (*icr_read)(void);
324 void (*icr_write)(u32 low, u32 high);
325 void (*wait_icr_idle)(void);
326 u32 (*safe_wait_icr_idle)(void);
330 * Called very early during boot from get_smp_config(). It should
331 * return the logical apicid. x86_[bios]_cpu_to_apicid is
332 * initialized before this function is called.
334 * If logical apicid can't be determined that early, the function
335 * may return BAD_APICID. Logical apicid will be configured after
336 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
337 * won't be applied properly during early boot in this case.
339 int (*x86_32_early_logical_apicid)(int cpu);
344 * Pointer to the local APIC driver in use on this system (there's
345 * always just one such driver in use - the kernel decides via an
346 * early probing process which one it picks - and then sticks to it):
348 extern struct apic *apic;
351 * APIC drivers are probed based on how they are listed in the .apicdrivers
352 * section. So the order is important and enforced by the ordering
353 * of different apic driver files in the Makefile.
355 * For the files having two apic drivers, we use apic_drivers()
356 * to enforce the order with in them.
358 #define apic_driver(sym) \
359 static const struct apic *__apicdrivers_##sym __used \
360 __aligned(sizeof(struct apic *)) \
361 __section(.apicdrivers) = { &sym }
363 #define apic_drivers(sym1, sym2) \
364 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
365 __aligned(sizeof(struct apic *)) \
366 __section(.apicdrivers) = { &sym1, &sym2 }
368 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
371 * APIC functionality to boot other CPUs - only used on SMP:
374 extern atomic_t init_deasserted;
375 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
378 #ifdef CONFIG_X86_LOCAL_APIC
380 static inline u32 apic_read(u32 reg)
382 return apic->read(reg);
385 static inline void apic_write(u32 reg, u32 val)
387 apic->write(reg, val);
390 static inline void apic_eoi(void)
392 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
395 static inline u64 apic_icr_read(void)
397 return apic->icr_read();
400 static inline void apic_icr_write(u32 low, u32 high)
402 apic->icr_write(low, high);
405 static inline void apic_wait_icr_idle(void)
407 apic->wait_icr_idle();
410 static inline u32 safe_apic_wait_icr_idle(void)
412 return apic->safe_wait_icr_idle();
415 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
417 #else /* CONFIG_X86_LOCAL_APIC */
419 static inline u32 apic_read(u32 reg) { return 0; }
420 static inline void apic_write(u32 reg, u32 val) { }
421 static inline void apic_eoi(void) { }
422 static inline u64 apic_icr_read(void) { return 0; }
423 static inline void apic_icr_write(u32 low, u32 high) { }
424 static inline void apic_wait_icr_idle(void) { }
425 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
426 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
428 #endif /* CONFIG_X86_LOCAL_APIC */
430 static inline void ack_APIC_irq(void)
433 * ack_APIC_irq() actually gets compiled as a single instruction
439 static inline unsigned default_get_apic_id(unsigned long x)
441 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
443 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
444 return (x >> 24) & 0xFF;
446 return (x >> 24) & 0x0F;
450 * Warm reset vector position:
452 #define TRAMPOLINE_PHYS_LOW 0x467
453 #define TRAMPOLINE_PHYS_HIGH 0x469
456 extern void apic_send_IPI_self(int vector);
458 DECLARE_PER_CPU(int, x2apic_extra_bits);
460 extern int default_cpu_present_to_apicid(int mps_cpu);
461 extern int default_check_phys_apicid_present(int phys_apicid);
464 extern void generic_bigsmp_probe(void);
467 #ifdef CONFIG_X86_LOCAL_APIC
471 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
473 static inline const struct cpumask *default_target_cpus(void)
476 return cpu_online_mask;
478 return cpumask_of(0);
482 static inline const struct cpumask *online_target_cpus(void)
484 return cpu_online_mask;
487 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
490 static inline unsigned int read_apic_id(void)
494 reg = apic_read(APIC_ID);
496 return apic->get_apic_id(reg);
499 static inline int default_apic_id_valid(int apicid)
501 return (apicid < 255);
504 extern int default_acpi_madt_oem_check(char *, char *);
506 extern void default_setup_apic_routing(void);
508 extern struct apic apic_noop;
512 static inline int noop_x86_32_early_logical_apicid(int cpu)
518 * Set up the logical destination ID.
520 * Intel recommends to set DFR, LDR and TPR before enabling
521 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
522 * document number 292116). So here it goes...
524 extern void default_init_apic_ldr(void);
526 static inline int default_apic_id_registered(void)
528 return physid_isset(read_apic_id(), phys_cpu_present_map);
531 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
533 return cpuid_apic >> index_msb;
539 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
540 const struct cpumask *andmask,
541 unsigned int *apicid)
543 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
544 cpumask_bits(andmask)[0] &
545 cpumask_bits(cpu_online_mask)[0] &
548 if (likely(cpu_mask)) {
549 *apicid = (unsigned int)cpu_mask;
557 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
558 const struct cpumask *andmask,
559 unsigned int *apicid);
562 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
563 const struct cpumask *mask)
565 /* Careful. Some cpus do not strictly honor the set of cpus
566 * specified in the interrupt destination when using lowest
567 * priority interrupt delivery mode.
569 * In particular there was a hyperthreading cpu observed to
570 * deliver interrupts to the wrong hyperthread when only one
571 * hyperthread was specified in the interrupt desitination.
573 cpumask_clear(retmask);
574 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
578 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
579 const struct cpumask *mask)
581 cpumask_copy(retmask, cpumask_of(cpu));
584 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
586 return physid_isset(apicid, *map);
589 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
594 static inline int __default_cpu_present_to_apicid(int mps_cpu)
596 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
597 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
603 __default_check_phys_apicid_present(int phys_apicid)
605 return physid_isset(phys_apicid, phys_cpu_present_map);
609 static inline int default_cpu_present_to_apicid(int mps_cpu)
611 return __default_cpu_present_to_apicid(mps_cpu);
615 default_check_phys_apicid_present(int phys_apicid)
617 return __default_check_phys_apicid_present(phys_apicid);
620 extern int default_cpu_present_to_apicid(int mps_cpu);
621 extern int default_check_phys_apicid_present(int phys_apicid);
624 #endif /* CONFIG_X86_LOCAL_APIC */
625 extern void irq_enter(void);
626 extern void irq_exit(void);
628 static inline void entering_irq(void)
634 static inline void entering_ack_irq(void)
640 static inline void exiting_irq(void)
645 static inline void exiting_ack_irq(void)
648 /* Ack only at the end to avoid potential reentry */
652 extern void ioapic_zap_locks(void);
654 #endif /* _ASM_X86_APIC_H */