1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
27 * Define the default level of output to be very little
28 * This can be turned up by using apic=verbose for more
29 * information and apic=debug for _lots_ of information.
30 * apic_verbosity is defined in apic.c
32 #define apic_printk(v, s, a...) do { \
33 if ((v) <= apic_verbosity) \
38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
39 extern void generic_apic_probe(void);
41 static inline void generic_apic_probe(void)
46 #ifdef CONFIG_X86_LOCAL_APIC
48 extern unsigned int apic_verbosity;
49 extern int local_apic_timer_c2_ok;
51 extern int disable_apic;
52 extern unsigned int lapic_timer_frequency;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
76 static inline bool apic_from_smp_config(void)
78 return smp_found_config && !disable_apic;
82 * Basic functions accessing APICs.
84 #ifdef CONFIG_PARAVIRT
85 #include <asm/paravirt.h>
88 extern int setup_profiling_timer(unsigned int);
90 static inline void native_apic_mem_write(u32 reg, u32 v)
92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
95 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
96 ASM_OUTPUT2("0" (v), "m" (*addr)));
99 static inline u32 native_apic_mem_read(u32 reg)
101 return *((volatile u32 *)(APIC_BASE + reg));
104 extern void native_apic_wait_icr_idle(void);
105 extern u32 native_safe_apic_wait_icr_idle(void);
106 extern void native_apic_icr_write(u32 low, u32 id);
107 extern u64 native_apic_icr_read(void);
109 static inline bool apic_is_x2apic_enabled(void)
113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
115 return msr & X2APIC_ENABLE;
118 #ifdef CONFIG_X86_X2APIC
120 * Make previous memory operations globally visible before
121 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
124 static inline void x2apic_wrmsr_fence(void)
126 asm volatile("mfence" : : : "memory");
129 static inline void native_apic_msr_write(u32 reg, u32 v)
131 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
135 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
138 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
140 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
143 static inline u32 native_apic_msr_read(u32 reg)
150 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
154 static inline void native_x2apic_wait_icr_idle(void)
156 /* no need to wait for icr idle in x2apic */
160 static inline u32 native_safe_x2apic_wait_icr_idle(void)
162 /* no need to wait for icr idle in x2apic */
166 static inline void native_x2apic_icr_write(u32 low, u32 id)
168 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
171 static inline u64 native_x2apic_icr_read(void)
175 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
179 extern int x2apic_mode;
180 extern int x2apic_phys;
181 extern int x2apic_preenabled;
182 extern void check_x2apic(void);
183 extern void enable_x2apic(void);
184 static inline int x2apic_enabled(void)
186 return cpu_has_x2apic && apic_is_x2apic_enabled();
189 #define x2apic_supported() (cpu_has_x2apic)
190 static inline void x2apic_force_phys(void)
195 static inline void disable_x2apic(void)
198 static inline void check_x2apic(void)
201 static inline void enable_x2apic(void)
204 static inline int x2apic_enabled(void)
208 static inline void x2apic_force_phys(void)
212 #define x2apic_mode (0)
213 #define x2apic_preenabled (0)
214 #define x2apic_supported() (0)
217 extern void enable_IR_x2apic(void);
219 extern int get_physical_broadcast(void);
221 extern int lapic_get_maxlvt(void);
222 extern void clear_local_APIC(void);
223 extern void connect_bsp_APIC(void);
224 extern void disconnect_bsp_APIC(int virt_wire_setup);
225 extern void disable_local_APIC(void);
226 extern void lapic_shutdown(void);
227 extern int verify_local_APIC(void);
228 extern void sync_Arb_IDs(void);
229 extern void init_bsp_APIC(void);
230 extern void setup_local_APIC(void);
231 extern void end_local_APIC_setup(void);
232 extern void bsp_end_local_APIC_setup(void);
233 extern void init_apic_mappings(void);
234 void register_lapic_address(unsigned long address);
235 extern void setup_boot_APIC_clock(void);
236 extern void setup_secondary_APIC_clock(void);
237 extern int APIC_init_uniprocessor(void);
238 extern int apic_force_enable(unsigned long addr);
241 * On 32bit this is mach-xxx local
244 extern int apic_is_clustered_box(void);
246 static inline int apic_is_clustered_box(void)
252 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
254 #else /* !CONFIG_X86_LOCAL_APIC */
255 static inline void lapic_shutdown(void) { }
256 #define local_apic_timer_c2_ok 1
257 static inline void init_apic_mappings(void) { }
258 static inline void disable_local_APIC(void) { }
259 # define setup_boot_APIC_clock x86_init_noop
260 # define setup_secondary_APIC_clock x86_init_noop
261 #endif /* !CONFIG_X86_LOCAL_APIC */
264 #define SET_APIC_ID(x) (apic->set_apic_id(x))
270 * Copyright 2004 James Cleverdon, IBM.
271 * Subject to the GNU Public License, v.2
273 * Generic APIC sub-arch data struct.
275 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
276 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
283 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
284 int (*apic_id_valid)(int apicid);
285 int (*apic_id_registered)(void);
287 u32 irq_delivery_mode;
290 const struct cpumask *(*target_cpus)(void);
295 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
297 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
298 const struct cpumask *mask);
299 void (*init_apic_ldr)(void);
301 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
303 void (*setup_apic_routing)(void);
304 int (*cpu_present_to_apicid)(int mps_cpu);
305 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
306 int (*check_phys_apicid_present)(int phys_apicid);
307 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
309 unsigned int (*get_apic_id)(unsigned long x);
310 unsigned long (*set_apic_id)(unsigned int id);
311 unsigned long apic_id_mask;
313 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
314 const struct cpumask *andmask,
315 unsigned int *apicid);
318 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
319 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
321 void (*send_IPI_allbutself)(int vector);
322 void (*send_IPI_all)(int vector);
323 void (*send_IPI_self)(int vector);
325 /* wakeup_secondary_cpu */
326 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
328 bool wait_for_init_deassert;
329 void (*inquire_remote_apic)(int apicid);
332 u32 (*read)(u32 reg);
333 void (*write)(u32 reg, u32 v);
335 * ->eoi_write() has the same signature as ->write().
337 * Drivers can support both ->eoi_write() and ->write() by passing the same
338 * callback value. Kernel can override ->eoi_write() and fall back
341 void (*eoi_write)(u32 reg, u32 v);
342 u64 (*icr_read)(void);
343 void (*icr_write)(u32 low, u32 high);
344 void (*wait_icr_idle)(void);
345 u32 (*safe_wait_icr_idle)(void);
349 * Called very early during boot from get_smp_config(). It should
350 * return the logical apicid. x86_[bios]_cpu_to_apicid is
351 * initialized before this function is called.
353 * If logical apicid can't be determined that early, the function
354 * may return BAD_APICID. Logical apicid will be configured after
355 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
356 * won't be applied properly during early boot in this case.
358 int (*x86_32_early_logical_apicid)(int cpu);
363 * Pointer to the local APIC driver in use on this system (there's
364 * always just one such driver in use - the kernel decides via an
365 * early probing process which one it picks - and then sticks to it):
367 extern struct apic *apic;
370 * APIC drivers are probed based on how they are listed in the .apicdrivers
371 * section. So the order is important and enforced by the ordering
372 * of different apic driver files in the Makefile.
374 * For the files having two apic drivers, we use apic_drivers()
375 * to enforce the order with in them.
377 #define apic_driver(sym) \
378 static const struct apic *__apicdrivers_##sym __used \
379 __aligned(sizeof(struct apic *)) \
380 __section(.apicdrivers) = { &sym }
382 #define apic_drivers(sym1, sym2) \
383 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
384 __aligned(sizeof(struct apic *)) \
385 __section(.apicdrivers) = { &sym1, &sym2 }
387 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
390 * APIC functionality to boot other CPUs - only used on SMP:
393 extern atomic_t init_deasserted;
394 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
397 #ifdef CONFIG_X86_LOCAL_APIC
399 static inline u32 apic_read(u32 reg)
401 return apic->read(reg);
404 static inline void apic_write(u32 reg, u32 val)
406 apic->write(reg, val);
409 static inline void apic_eoi(void)
411 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
414 static inline u64 apic_icr_read(void)
416 return apic->icr_read();
419 static inline void apic_icr_write(u32 low, u32 high)
421 apic->icr_write(low, high);
424 static inline void apic_wait_icr_idle(void)
426 apic->wait_icr_idle();
429 static inline u32 safe_apic_wait_icr_idle(void)
431 return apic->safe_wait_icr_idle();
434 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
436 #else /* CONFIG_X86_LOCAL_APIC */
438 static inline u32 apic_read(u32 reg) { return 0; }
439 static inline void apic_write(u32 reg, u32 val) { }
440 static inline void apic_eoi(void) { }
441 static inline u64 apic_icr_read(void) { return 0; }
442 static inline void apic_icr_write(u32 low, u32 high) { }
443 static inline void apic_wait_icr_idle(void) { }
444 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
445 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
447 #endif /* CONFIG_X86_LOCAL_APIC */
449 static inline void ack_APIC_irq(void)
452 * ack_APIC_irq() actually gets compiled as a single instruction
458 static inline unsigned default_get_apic_id(unsigned long x)
460 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
462 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
463 return (x >> 24) & 0xFF;
465 return (x >> 24) & 0x0F;
469 * Warm reset vector position:
471 #define TRAMPOLINE_PHYS_LOW 0x467
472 #define TRAMPOLINE_PHYS_HIGH 0x469
475 extern void apic_send_IPI_self(int vector);
477 DECLARE_PER_CPU(int, x2apic_extra_bits);
479 extern int default_cpu_present_to_apicid(int mps_cpu);
480 extern int default_check_phys_apicid_present(int phys_apicid);
483 extern void generic_bigsmp_probe(void);
486 #ifdef CONFIG_X86_LOCAL_APIC
490 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
492 static inline const struct cpumask *default_target_cpus(void)
495 return cpu_online_mask;
497 return cpumask_of(0);
501 static inline const struct cpumask *online_target_cpus(void)
503 return cpu_online_mask;
506 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
509 static inline unsigned int read_apic_id(void)
513 reg = apic_read(APIC_ID);
515 return apic->get_apic_id(reg);
518 static inline int default_apic_id_valid(int apicid)
520 return (apicid < 255);
523 extern int default_acpi_madt_oem_check(char *, char *);
525 extern void default_setup_apic_routing(void);
527 extern struct apic apic_noop;
531 static inline int noop_x86_32_early_logical_apicid(int cpu)
537 * Set up the logical destination ID.
539 * Intel recommends to set DFR, LDR and TPR before enabling
540 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
541 * document number 292116). So here it goes...
543 extern void default_init_apic_ldr(void);
545 static inline int default_apic_id_registered(void)
547 return physid_isset(read_apic_id(), phys_cpu_present_map);
550 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
552 return cpuid_apic >> index_msb;
558 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
559 const struct cpumask *andmask,
560 unsigned int *apicid)
562 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
563 cpumask_bits(andmask)[0] &
564 cpumask_bits(cpu_online_mask)[0] &
567 if (likely(cpu_mask)) {
568 *apicid = (unsigned int)cpu_mask;
576 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
577 const struct cpumask *andmask,
578 unsigned int *apicid);
581 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
582 const struct cpumask *mask)
584 /* Careful. Some cpus do not strictly honor the set of cpus
585 * specified in the interrupt destination when using lowest
586 * priority interrupt delivery mode.
588 * In particular there was a hyperthreading cpu observed to
589 * deliver interrupts to the wrong hyperthread when only one
590 * hyperthread was specified in the interrupt desitination.
592 cpumask_clear(retmask);
593 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
597 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
598 const struct cpumask *mask)
600 cpumask_copy(retmask, cpumask_of(cpu));
603 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
605 return physid_isset(apicid, *map);
608 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
613 static inline int __default_cpu_present_to_apicid(int mps_cpu)
615 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
616 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
622 __default_check_phys_apicid_present(int phys_apicid)
624 return physid_isset(phys_apicid, phys_cpu_present_map);
628 static inline int default_cpu_present_to_apicid(int mps_cpu)
630 return __default_cpu_present_to_apicid(mps_cpu);
634 default_check_phys_apicid_present(int phys_apicid)
636 return __default_check_phys_apicid_present(phys_apicid);
639 extern int default_cpu_present_to_apicid(int mps_cpu);
640 extern int default_check_phys_apicid_present(int phys_apicid);
643 #endif /* CONFIG_X86_LOCAL_APIC */
644 extern void irq_enter(void);
645 extern void irq_exit(void);
647 static inline void entering_irq(void)
653 static inline void entering_ack_irq(void)
659 static inline void exiting_irq(void)
664 static inline void exiting_ack_irq(void)
667 /* Ack only at the end to avoid potential reentry */
671 extern void ioapic_zap_locks(void);
673 #endif /* _ASM_X86_APIC_H */