1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
27 * Define the default level of output to be very little
28 * This can be turned up by using apic=verbose for more
29 * information and apic=debug for _lots_ of information.
30 * apic_verbosity is defined in apic.c
32 #define apic_printk(v, s, a...) do { \
33 if ((v) <= apic_verbosity) \
38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
39 extern void generic_apic_probe(void);
41 static inline void generic_apic_probe(void)
46 #ifdef CONFIG_X86_LOCAL_APIC
48 extern unsigned int apic_verbosity;
49 extern int local_apic_timer_c2_ok;
51 extern int disable_apic;
52 extern unsigned int lapic_timer_frequency;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
76 static inline bool apic_from_smp_config(void)
78 return smp_found_config && !disable_apic;
82 * Basic functions accessing APICs.
84 #ifdef CONFIG_PARAVIRT
85 #include <asm/paravirt.h>
88 extern int setup_profiling_timer(unsigned int);
90 static inline void native_apic_mem_write(u32 reg, u32 v)
92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
94 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
95 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
96 ASM_OUTPUT2("0" (v), "m" (*addr)));
99 static inline u32 native_apic_mem_read(u32 reg)
101 return *((volatile u32 *)(APIC_BASE + reg));
104 extern void native_apic_wait_icr_idle(void);
105 extern u32 native_safe_apic_wait_icr_idle(void);
106 extern void native_apic_icr_write(u32 low, u32 id);
107 extern u64 native_apic_icr_read(void);
109 extern int x2apic_mode;
111 #ifdef CONFIG_X86_X2APIC
113 * Make previous memory operations globally visible before
114 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
117 static inline void x2apic_wrmsr_fence(void)
119 asm volatile("mfence" : : : "memory");
122 static inline void native_apic_msr_write(u32 reg, u32 v)
124 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
128 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
131 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
133 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
136 static inline u32 native_apic_msr_read(u32 reg)
143 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
147 static inline void native_x2apic_wait_icr_idle(void)
149 /* no need to wait for icr idle in x2apic */
153 static inline u32 native_safe_x2apic_wait_icr_idle(void)
155 /* no need to wait for icr idle in x2apic */
159 static inline void native_x2apic_icr_write(u32 low, u32 id)
161 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
164 static inline u64 native_x2apic_icr_read(void)
168 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
172 extern int x2apic_phys;
173 extern int x2apic_preenabled;
174 extern void check_x2apic(void);
175 extern void enable_x2apic(void);
176 static inline int x2apic_enabled(void)
183 rdmsrl(MSR_IA32_APICBASE, msr);
184 if (msr & X2APIC_ENABLE)
189 #define x2apic_supported() (cpu_has_x2apic)
190 static inline void x2apic_force_phys(void)
195 static inline void disable_x2apic(void)
198 static inline void check_x2apic(void)
201 static inline void enable_x2apic(void)
204 static inline int x2apic_enabled(void)
208 static inline void x2apic_force_phys(void)
212 #define x2apic_preenabled 0
213 #define x2apic_supported() 0
216 extern void enable_IR_x2apic(void);
218 extern int get_physical_broadcast(void);
220 extern int lapic_get_maxlvt(void);
221 extern void clear_local_APIC(void);
222 extern void connect_bsp_APIC(void);
223 extern void disconnect_bsp_APIC(int virt_wire_setup);
224 extern void disable_local_APIC(void);
225 extern void lapic_shutdown(void);
226 extern int verify_local_APIC(void);
227 extern void sync_Arb_IDs(void);
228 extern void init_bsp_APIC(void);
229 extern void setup_local_APIC(void);
230 extern void end_local_APIC_setup(void);
231 extern void bsp_end_local_APIC_setup(void);
232 extern void init_apic_mappings(void);
233 void register_lapic_address(unsigned long address);
234 extern void setup_boot_APIC_clock(void);
235 extern void setup_secondary_APIC_clock(void);
236 extern int APIC_init_uniprocessor(void);
237 extern int apic_force_enable(unsigned long addr);
240 * On 32bit this is mach-xxx local
243 extern int apic_is_clustered_box(void);
245 static inline int apic_is_clustered_box(void)
251 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
253 #else /* !CONFIG_X86_LOCAL_APIC */
254 static inline void lapic_shutdown(void) { }
255 #define local_apic_timer_c2_ok 1
256 static inline void init_apic_mappings(void) { }
257 static inline void disable_local_APIC(void) { }
258 # define setup_boot_APIC_clock x86_init_noop
259 # define setup_secondary_APIC_clock x86_init_noop
260 #endif /* !CONFIG_X86_LOCAL_APIC */
263 #define SET_APIC_ID(x) (apic->set_apic_id(x))
269 * Copyright 2004 James Cleverdon, IBM.
270 * Subject to the GNU Public License, v.2
272 * Generic APIC sub-arch data struct.
274 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
275 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
282 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
283 int (*apic_id_valid)(int apicid);
284 int (*apic_id_registered)(void);
286 u32 irq_delivery_mode;
289 const struct cpumask *(*target_cpus)(void);
294 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
296 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
297 const struct cpumask *mask);
298 void (*init_apic_ldr)(void);
300 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
302 void (*setup_apic_routing)(void);
303 int (*cpu_present_to_apicid)(int mps_cpu);
304 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
305 int (*check_phys_apicid_present)(int phys_apicid);
306 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
308 unsigned int (*get_apic_id)(unsigned long x);
309 unsigned long (*set_apic_id)(unsigned int id);
310 unsigned long apic_id_mask;
312 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
313 const struct cpumask *andmask,
314 unsigned int *apicid);
317 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
318 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
320 void (*send_IPI_allbutself)(int vector);
321 void (*send_IPI_all)(int vector);
322 void (*send_IPI_self)(int vector);
324 /* wakeup_secondary_cpu */
325 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
327 bool wait_for_init_deassert;
328 void (*inquire_remote_apic)(int apicid);
331 u32 (*read)(u32 reg);
332 void (*write)(u32 reg, u32 v);
334 * ->eoi_write() has the same signature as ->write().
336 * Drivers can support both ->eoi_write() and ->write() by passing the same
337 * callback value. Kernel can override ->eoi_write() and fall back
340 void (*eoi_write)(u32 reg, u32 v);
341 u64 (*icr_read)(void);
342 void (*icr_write)(u32 low, u32 high);
343 void (*wait_icr_idle)(void);
344 u32 (*safe_wait_icr_idle)(void);
348 * Called very early during boot from get_smp_config(). It should
349 * return the logical apicid. x86_[bios]_cpu_to_apicid is
350 * initialized before this function is called.
352 * If logical apicid can't be determined that early, the function
353 * may return BAD_APICID. Logical apicid will be configured after
354 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
355 * won't be applied properly during early boot in this case.
357 int (*x86_32_early_logical_apicid)(int cpu);
362 * Pointer to the local APIC driver in use on this system (there's
363 * always just one such driver in use - the kernel decides via an
364 * early probing process which one it picks - and then sticks to it):
366 extern struct apic *apic;
369 * APIC drivers are probed based on how they are listed in the .apicdrivers
370 * section. So the order is important and enforced by the ordering
371 * of different apic driver files in the Makefile.
373 * For the files having two apic drivers, we use apic_drivers()
374 * to enforce the order with in them.
376 #define apic_driver(sym) \
377 static const struct apic *__apicdrivers_##sym __used \
378 __aligned(sizeof(struct apic *)) \
379 __section(.apicdrivers) = { &sym }
381 #define apic_drivers(sym1, sym2) \
382 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
383 __aligned(sizeof(struct apic *)) \
384 __section(.apicdrivers) = { &sym1, &sym2 }
386 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
389 * APIC functionality to boot other CPUs - only used on SMP:
392 extern atomic_t init_deasserted;
393 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
396 #ifdef CONFIG_X86_LOCAL_APIC
398 static inline u32 apic_read(u32 reg)
400 return apic->read(reg);
403 static inline void apic_write(u32 reg, u32 val)
405 apic->write(reg, val);
408 static inline void apic_eoi(void)
410 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
413 static inline u64 apic_icr_read(void)
415 return apic->icr_read();
418 static inline void apic_icr_write(u32 low, u32 high)
420 apic->icr_write(low, high);
423 static inline void apic_wait_icr_idle(void)
425 apic->wait_icr_idle();
428 static inline u32 safe_apic_wait_icr_idle(void)
430 return apic->safe_wait_icr_idle();
433 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
435 #else /* CONFIG_X86_LOCAL_APIC */
437 static inline u32 apic_read(u32 reg) { return 0; }
438 static inline void apic_write(u32 reg, u32 val) { }
439 static inline void apic_eoi(void) { }
440 static inline u64 apic_icr_read(void) { return 0; }
441 static inline void apic_icr_write(u32 low, u32 high) { }
442 static inline void apic_wait_icr_idle(void) { }
443 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
444 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
446 #endif /* CONFIG_X86_LOCAL_APIC */
448 static inline void ack_APIC_irq(void)
451 * ack_APIC_irq() actually gets compiled as a single instruction
457 static inline unsigned default_get_apic_id(unsigned long x)
459 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
461 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
462 return (x >> 24) & 0xFF;
464 return (x >> 24) & 0x0F;
468 * Warm reset vector position:
470 #define TRAMPOLINE_PHYS_LOW 0x467
471 #define TRAMPOLINE_PHYS_HIGH 0x469
474 extern void apic_send_IPI_self(int vector);
476 DECLARE_PER_CPU(int, x2apic_extra_bits);
478 extern int default_cpu_present_to_apicid(int mps_cpu);
479 extern int default_check_phys_apicid_present(int phys_apicid);
482 extern void generic_bigsmp_probe(void);
485 #ifdef CONFIG_X86_LOCAL_APIC
489 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
491 static inline const struct cpumask *default_target_cpus(void)
494 return cpu_online_mask;
496 return cpumask_of(0);
500 static inline const struct cpumask *online_target_cpus(void)
502 return cpu_online_mask;
505 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
508 static inline unsigned int read_apic_id(void)
512 reg = apic_read(APIC_ID);
514 return apic->get_apic_id(reg);
517 static inline int default_apic_id_valid(int apicid)
519 return (apicid < 255);
522 extern int default_acpi_madt_oem_check(char *, char *);
524 extern void default_setup_apic_routing(void);
526 extern struct apic apic_noop;
530 static inline int noop_x86_32_early_logical_apicid(int cpu)
536 * Set up the logical destination ID.
538 * Intel recommends to set DFR, LDR and TPR before enabling
539 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
540 * document number 292116). So here it goes...
542 extern void default_init_apic_ldr(void);
544 static inline int default_apic_id_registered(void)
546 return physid_isset(read_apic_id(), phys_cpu_present_map);
549 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
551 return cpuid_apic >> index_msb;
557 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
558 const struct cpumask *andmask,
559 unsigned int *apicid)
561 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
562 cpumask_bits(andmask)[0] &
563 cpumask_bits(cpu_online_mask)[0] &
566 if (likely(cpu_mask)) {
567 *apicid = (unsigned int)cpu_mask;
575 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
576 const struct cpumask *andmask,
577 unsigned int *apicid);
580 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
581 const struct cpumask *mask)
583 /* Careful. Some cpus do not strictly honor the set of cpus
584 * specified in the interrupt destination when using lowest
585 * priority interrupt delivery mode.
587 * In particular there was a hyperthreading cpu observed to
588 * deliver interrupts to the wrong hyperthread when only one
589 * hyperthread was specified in the interrupt desitination.
591 cpumask_clear(retmask);
592 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
596 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
597 const struct cpumask *mask)
599 cpumask_copy(retmask, cpumask_of(cpu));
602 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
604 return physid_isset(apicid, *map);
607 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
612 static inline int __default_cpu_present_to_apicid(int mps_cpu)
614 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
615 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
621 __default_check_phys_apicid_present(int phys_apicid)
623 return physid_isset(phys_apicid, phys_cpu_present_map);
627 static inline int default_cpu_present_to_apicid(int mps_cpu)
629 return __default_cpu_present_to_apicid(mps_cpu);
633 default_check_phys_apicid_present(int phys_apicid)
635 return __default_check_phys_apicid_present(phys_apicid);
638 extern int default_cpu_present_to_apicid(int mps_cpu);
639 extern int default_check_phys_apicid_present(int phys_apicid);
642 #endif /* CONFIG_X86_LOCAL_APIC */
643 extern void irq_enter(void);
644 extern void irq_exit(void);
646 static inline void entering_irq(void)
652 static inline void entering_ack_irq(void)
658 static inline void exiting_irq(void)
663 static inline void exiting_ack_irq(void)
666 /* Ack only at the end to avoid potential reentry */
670 extern void ioapic_zap_locks(void);
672 #endif /* _ASM_X86_APIC_H */