x86/fpu: Harmonize FPU register state types
[firefly-linux-kernel-4.4.55.git] / arch / x86 / include / asm / fpu / types.h
1 /*
2  * FPU data structures:
3  */
4 #ifndef _ASM_X86_FPU_H
5 #define _ASM_X86_FPU_H
6
7 struct fregs_state {
8         u32                     cwd;    /* FPU Control Word             */
9         u32                     swd;    /* FPU Status Word              */
10         u32                     twd;    /* FPU Tag Word                 */
11         u32                     fip;    /* FPU IP Offset                */
12         u32                     fcs;    /* FPU IP Selector              */
13         u32                     foo;    /* FPU Operand Pointer Offset   */
14         u32                     fos;    /* FPU Operand Pointer Selector */
15
16         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
17         u32                     st_space[20];
18
19         /* Software status information [not touched by FSAVE ]:         */
20         u32                     status;
21 };
22
23 struct fxregs_state {
24         u16                     cwd; /* Control Word                    */
25         u16                     swd; /* Status Word                     */
26         u16                     twd; /* Tag Word                        */
27         u16                     fop; /* Last Instruction Opcode         */
28         union {
29                 struct {
30                         u64     rip; /* Instruction Pointer             */
31                         u64     rdp; /* Data Pointer                    */
32                 };
33                 struct {
34                         u32     fip; /* FPU IP Offset                   */
35                         u32     fcs; /* FPU IP Selector                 */
36                         u32     foo; /* FPU Operand Offset              */
37                         u32     fos; /* FPU Operand Selector            */
38                 };
39         };
40         u32                     mxcsr;          /* MXCSR Register State */
41         u32                     mxcsr_mask;     /* MXCSR Mask           */
42
43         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
44         u32                     st_space[32];
45
46         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
47         u32                     xmm_space[64];
48
49         u32                     padding[12];
50
51         union {
52                 u32             padding1[12];
53                 u32             sw_reserved[12];
54         };
55
56 } __attribute__((aligned(16)));
57
58 /*
59  * Software based FPU emulation state:
60  */
61 struct swregs_state {
62         u32                     cwd;
63         u32                     swd;
64         u32                     twd;
65         u32                     fip;
66         u32                     fcs;
67         u32                     foo;
68         u32                     fos;
69         /* 8*10 bytes for each FP-reg = 80 bytes: */
70         u32                     st_space[20];
71         u8                      ftop;
72         u8                      changed;
73         u8                      lookahead;
74         u8                      no_update;
75         u8                      rm;
76         u8                      alimit;
77         struct math_emu_info    *info;
78         u32                     entry_eip;
79 };
80
81 /*
82  * List of XSAVE features Linux knows about:
83  */
84 enum xfeature_bit {
85         XSTATE_BIT_FP,
86         XSTATE_BIT_SSE,
87         XSTATE_BIT_YMM,
88         XSTATE_BIT_BNDREGS,
89         XSTATE_BIT_BNDCSR,
90         XSTATE_BIT_OPMASK,
91         XSTATE_BIT_ZMM_Hi256,
92         XSTATE_BIT_Hi16_ZMM,
93
94         XFEATURES_NR_MAX,
95 };
96
97 #define XSTATE_FP               (1 << XSTATE_BIT_FP)
98 #define XSTATE_SSE              (1 << XSTATE_BIT_SSE)
99 #define XSTATE_YMM              (1 << XSTATE_BIT_YMM)
100 #define XSTATE_BNDREGS          (1 << XSTATE_BIT_BNDREGS)
101 #define XSTATE_BNDCSR           (1 << XSTATE_BIT_BNDCSR)
102 #define XSTATE_OPMASK           (1 << XSTATE_BIT_OPMASK)
103 #define XSTATE_ZMM_Hi256        (1 << XSTATE_BIT_ZMM_Hi256)
104 #define XSTATE_Hi16_ZMM         (1 << XSTATE_BIT_Hi16_ZMM)
105
106 #define XSTATE_FPSSE            (XSTATE_FP | XSTATE_SSE)
107 #define XSTATE_AVX512           (XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)
108
109 /*
110  * There are 16x 256-bit AVX registers named YMM0-YMM15.
111  * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
112  * and are stored in 'struct fxregs_state::xmm_space[]'.
113  *
114  * The high 128 bits are stored here:
115  *    16x 128 bits == 256 bytes.
116  */
117 struct ymmh_struct {
118         u8                              ymmh_space[256];
119 };
120
121 /* We don't support LWP yet: */
122 struct lwp_struct {
123         u8                              reserved[128];
124 };
125
126 /* Intel MPX support: */
127 struct bndreg {
128         u64                             lower_bound;
129         u64                             upper_bound;
130 } __packed;
131
132 struct bndcsr {
133         u64                             bndcfgu;
134         u64                             bndstatus;
135 } __packed;
136
137 struct xstate_header {
138         u64                             xfeatures;
139         u64                             xcomp_bv;
140         u64                             reserved[6];
141 } __attribute__((packed));
142
143 struct xregs_state {
144         struct fxregs_state             i387;
145         struct xstate_header            header;
146         struct ymmh_struct              ymmh;
147         struct lwp_struct               lwp;
148         struct bndreg                   bndreg[4];
149         struct bndcsr                   bndcsr;
150         /* New processor state extensions will go here. */
151 } __attribute__ ((packed, aligned (64)));
152
153 union fpregs_state {
154         struct fregs_state              fsave;
155         struct fxregs_state             fxsave;
156         struct swregs_state             soft;
157         struct xregs_state              xsave;
158 };
159
160 struct fpu {
161         /*
162          * Records the last CPU on which this context was loaded into
163          * FPU registers. (In the lazy-switching case we might be
164          * able to reuse FPU registers across multiple context switches
165          * this way, if no intermediate task used the FPU.)
166          *
167          * A value of -1 is used to indicate that the FPU state in context
168          * memory is newer than the FPU state in registers, and that the
169          * FPU state should be reloaded next time the task is run.
170          */
171         unsigned int                    last_cpu;
172
173         unsigned int                    fpregs_active;
174         union fpregs_state              state;
175         /*
176          * This counter contains the number of consecutive context switches
177          * during which the FPU stays used. If this is over a threshold, the
178          * lazy fpu saving logic becomes unlazy, to save the trap overhead.
179          * This is an unsigned char so that after 256 iterations the counter
180          * wraps and the context switch behavior turns lazy again; this is to
181          * deal with bursty apps that only use the FPU for a short time:
182          */
183         unsigned char                   counter;
184         /*
185          * This flag indicates whether this context is fpstate_active: if the task is
186          * not running then we can restore from this context, if the task
187          * is running then we should save into this context.
188          */
189         unsigned char                   fpstate_active;
190 };
191
192 #endif /* _ASM_X86_FPU_H */