5 * KVM x86 specific structures and definitions
9 #include <linux/types.h>
10 #include <linux/ioctl.h>
12 /* Select x86 specific features in <linux/kvm.h> */
13 #define __KVM_HAVE_PIT
14 #define __KVM_HAVE_IOAPIC
15 #define __KVM_HAVE_DEVICE_ASSIGNMENT
16 #define __KVM_HAVE_MSI
17 #define __KVM_HAVE_USER_NMI
18 #define __KVM_HAVE_GUEST_DEBUG
19 #define __KVM_HAVE_MSIX
20 #define __KVM_HAVE_MCE
21 #define __KVM_HAVE_PIT_STATE2
22 #define __KVM_HAVE_XEN_HVM
23 #define __KVM_HAVE_VCPU_EVENTS
25 /* Architectural interrupt line count. */
26 #define KVM_NR_INTERRUPTS 256
28 struct kvm_memory_alias {
29 __u32 slot; /* this has a different namespace than memory slots */
31 __u64 guest_phys_addr;
33 __u64 target_phys_addr;
36 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
37 struct kvm_pic_state {
38 __u8 last_irr; /* edge detection */
39 __u8 irr; /* interrupt request register */
40 __u8 imr; /* interrupt mask register */
41 __u8 isr; /* interrupt service register */
42 __u8 priority_add; /* highest irq priority */
49 __u8 rotate_on_auto_eoi;
50 __u8 special_fully_nested_mode;
51 __u8 init4; /* true if 4 byte init */
52 __u8 elcr; /* PIIX edge/trigger selection */
56 #define KVM_IOAPIC_NUM_PINS 24
57 struct kvm_ioapic_state {
69 __u8 delivery_status:1;
78 } redirtbl[KVM_IOAPIC_NUM_PINS];
81 #define KVM_IRQCHIP_PIC_MASTER 0
82 #define KVM_IRQCHIP_PIC_SLAVE 1
83 #define KVM_IRQCHIP_IOAPIC 2
84 #define KVM_NR_IRQCHIPS 3
86 /* for KVM_GET_REGS and KVM_SET_REGS */
88 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
89 __u64 rax, rbx, rcx, rdx;
90 __u64 rsi, rdi, rsp, rbp;
91 __u64 r8, r9, r10, r11;
92 __u64 r12, r13, r14, r15;
96 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
97 #define KVM_APIC_REG_SIZE 0x400
98 struct kvm_lapic_state {
99 char regs[KVM_APIC_REG_SIZE];
107 __u8 present, dpl, db, s, l, g, avl;
119 /* for KVM_GET_SREGS and KVM_SET_SREGS */
121 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
122 struct kvm_segment cs, ds, es, fs, gs, ss;
123 struct kvm_segment tr, ldt;
124 struct kvm_dtable gdt, idt;
125 __u64 cr0, cr2, cr3, cr4, cr8;
128 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
131 /* for KVM_GET_FPU and KVM_SET_FPU */
136 __u8 ftwx; /* in fxsave format */
146 struct kvm_msr_entry {
152 /* for KVM_GET_MSRS and KVM_SET_MSRS */
154 __u32 nmsrs; /* number of msrs in entries */
157 struct kvm_msr_entry entries[0];
160 /* for KVM_GET_MSR_INDEX_LIST */
161 struct kvm_msr_list {
162 __u32 nmsrs; /* number of msrs in entries */
167 struct kvm_cpuid_entry {
176 /* for KVM_SET_CPUID */
180 struct kvm_cpuid_entry entries[0];
183 struct kvm_cpuid_entry2 {
194 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
195 #define KVM_CPUID_FLAG_STATEFUL_FUNC 2
196 #define KVM_CPUID_FLAG_STATE_READ_NEXT 4
198 /* for KVM_SET_CPUID2 */
202 struct kvm_cpuid_entry2 entries[0];
205 /* for KVM_GET_PIT and KVM_SET_PIT */
206 struct kvm_pit_channel_state {
207 __u32 count; /* can be 65536 */
219 __s64 count_load_time;
222 struct kvm_debug_exit_arch {
230 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
231 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
232 #define KVM_GUESTDBG_INJECT_DB 0x00040000
233 #define KVM_GUESTDBG_INJECT_BP 0x00080000
235 /* for KVM_SET_GUEST_DEBUG */
236 struct kvm_guest_debug_arch {
240 struct kvm_pit_state {
241 struct kvm_pit_channel_state channels[3];
244 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
246 struct kvm_pit_state2 {
247 struct kvm_pit_channel_state channels[3];
252 struct kvm_reinject_control {
257 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
258 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
259 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
261 /* for KVM_GET/SET_VCPU_EVENTS */
262 struct kvm_vcpu_events {
287 #endif /* _ASM_X86_KVM_H */