1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
4 #ifdef CONFIG_X86_LOCAL_APIC
6 #include <mach_apicdef.h>
9 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
11 static inline cpumask_t target_cpus(void)
14 return cpu_online_map;
16 return cpumask_of_cpu(0);
20 #define NO_BALANCE_IRQ (0)
21 #define esr_disable (0)
24 #include <asm/genapic.h>
25 #define INT_DELIVERY_MODE (genapic->int_delivery_mode)
26 #define INT_DEST_MODE (genapic->int_dest_mode)
27 #define TARGET_CPUS (genapic->target_cpus())
28 #define apic_id_registered (genapic->apic_id_registered)
29 #define init_apic_ldr (genapic->init_apic_ldr)
30 #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
31 #define phys_pkg_id (genapic->phys_pkg_id)
32 #define vector_allocation_domain (genapic->vector_allocation_domain)
33 #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
34 #define send_IPI_self (genapic->send_IPI_self)
35 #define wakeup_secondary_cpu (genapic->wakeup_cpu)
36 extern void setup_apic_routing(void);
38 #define INT_DELIVERY_MODE dest_LowestPrio
39 #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
40 #define TARGET_CPUS (target_cpus())
41 #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
43 * Set up the logical destination ID.
45 * Intel recommends to set DFR, LDR and TPR before enabling
46 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
47 * document number 292116). So here it goes...
49 static inline void init_apic_ldr(void)
53 apic_write(APIC_DFR, APIC_DFR_VALUE);
54 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
55 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
56 apic_write(APIC_LDR, val);
59 static inline int apic_id_registered(void)
61 return physid_isset(read_apic_id(), phys_cpu_present_map);
64 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
66 return cpus_addr(cpumask)[0];
69 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
71 return cpuid_apic >> index_msb;
74 static inline void setup_apic_routing(void)
76 #ifdef CONFIG_X86_IO_APIC
77 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
82 static inline int apicid_to_node(int logical_apicid)
85 return apicid_2_node[hard_smp_processor_id()];
91 static inline cpumask_t vector_allocation_domain(int cpu)
93 /* Careful. Some cpus do not strictly honor the set of cpus
94 * specified in the interrupt destination when using lowest
95 * priority interrupt delivery mode.
97 * In particular there was a hyperthreading cpu observed to
98 * deliver interrupts to the wrong hyperthread when only one
99 * hyperthread was specified in the interrupt desitination.
101 cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
106 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
108 return physid_isset(apicid, bitmap);
111 static inline unsigned long check_apicid_present(int bit)
113 return physid_isset(bit, phys_cpu_present_map);
116 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
121 static inline int multi_timer_check(int apic, int irq)
126 /* Mapping from cpu number to logical apicid */
127 static inline int cpu_to_logical_apicid(int cpu)
132 static inline int cpu_present_to_apicid(int mps_cpu)
134 if (mps_cpu < NR_CPUS && cpu_present(mps_cpu))
135 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
140 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
142 return physid_mask_of_physid(phys_apicid);
145 static inline void setup_portio_remap(void)
149 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
151 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
154 static inline void enable_apic_mode(void)
157 #endif /* CONFIG_X86_LOCAL_APIC */
158 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */