1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
89 char wp_works_ok; /* It doesn't on 386's */
91 /* Problems on some 486Dx4's and old 386's: */
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits;
103 /* Max extended CPUID function supported: */
104 __u32 extended_cpuid_level;
105 /* Maximum supported CPUID level, -1=no CPUID: */
107 __u32 x86_capability[NCAPINTS + NBUGINTS];
108 char x86_vendor_id[16];
109 char x86_model_id[64];
110 /* in KB - valid for CPUS which support this call: */
112 int x86_cache_alignment; /* In bytes */
114 unsigned long loops_per_jiffy;
115 /* cpuid returned max cores value: */
119 u16 x86_clflush_size;
120 /* number of cores as seen by the OS: */
122 /* Physical processor id: */
126 /* Compute unit id */
128 /* Index into per_cpu list: */
131 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
133 #define X86_VENDOR_INTEL 0
134 #define X86_VENDOR_CYRIX 1
135 #define X86_VENDOR_AMD 2
136 #define X86_VENDOR_UMC 3
137 #define X86_VENDOR_CENTAUR 5
138 #define X86_VENDOR_TRANSMETA 7
139 #define X86_VENDOR_NSC 8
140 #define X86_VENDOR_NUM 9
142 #define X86_VENDOR_UNKNOWN 0xff
145 * capabilities of CPUs
147 extern struct cpuinfo_x86 boot_cpu_data;
148 extern struct cpuinfo_x86 new_cpu_data;
150 extern struct tss_struct doublefault_tss;
151 extern __u32 cpu_caps_cleared[NCAPINTS];
152 extern __u32 cpu_caps_set[NCAPINTS];
155 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
156 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
158 #define cpu_info boot_cpu_data
159 #define cpu_data(cpu) boot_cpu_data
162 extern const struct seq_operations cpuinfo_op;
164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
166 extern void cpu_detect(struct cpuinfo_x86 *c);
168 extern void early_cpu_init(void);
169 extern void identify_boot_cpu(void);
170 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
171 extern void print_cpu_info(struct cpuinfo_x86 *);
172 void print_cpu_msr(struct cpuinfo_x86 *);
173 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
174 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
175 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
177 extern void detect_extended_topology(struct cpuinfo_x86 *c);
178 extern void detect_ht(struct cpuinfo_x86 *c);
181 extern int have_cpuid_p(void);
183 static inline int have_cpuid_p(void)
188 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
189 unsigned int *ecx, unsigned int *edx)
191 /* ecx is often an input as well as an output. */
197 : "0" (*eax), "2" (*ecx)
201 static inline void load_cr3(pgd_t *pgdir)
203 write_cr3(__pa(pgdir));
207 /* This is the TSS defined by the hardware. */
209 unsigned short back_link, __blh;
211 unsigned short ss0, __ss0h;
213 /* ss1 caches MSR_IA32_SYSENTER_CS: */
214 unsigned short ss1, __ss1h;
216 unsigned short ss2, __ss2h;
228 unsigned short es, __esh;
229 unsigned short cs, __csh;
230 unsigned short ss, __ssh;
231 unsigned short ds, __dsh;
232 unsigned short fs, __fsh;
233 unsigned short gs, __gsh;
234 unsigned short ldt, __ldth;
235 unsigned short trace;
236 unsigned short io_bitmap_base;
238 } __attribute__((packed));
252 } __attribute__((packed)) ____cacheline_aligned;
258 #define IO_BITMAP_BITS 65536
259 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
260 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
261 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
262 #define INVALID_IO_BITMAP_OFFSET 0x8000
266 * The hardware state:
268 struct x86_hw_tss x86_tss;
271 * The extra 1 is there because the CPU will access an
272 * additional byte beyond the end of the IO permission
273 * bitmap. The extra byte must be all 1 bits, and must
274 * be within the limit.
276 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
279 * .. and then another 0x100 bytes for the emergency kernel stack:
281 unsigned long stack[64];
283 } ____cacheline_aligned;
285 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
288 * Save the original ist values for checking stack pointers during debugging
291 unsigned long ist[7];
294 #define MXCSR_DEFAULT 0x1f80
296 struct i387_fsave_struct {
297 u32 cwd; /* FPU Control Word */
298 u32 swd; /* FPU Status Word */
299 u32 twd; /* FPU Tag Word */
300 u32 fip; /* FPU IP Offset */
301 u32 fcs; /* FPU IP Selector */
302 u32 foo; /* FPU Operand Pointer Offset */
303 u32 fos; /* FPU Operand Pointer Selector */
305 /* 8*10 bytes for each FP-reg = 80 bytes: */
308 /* Software status information [not touched by FSAVE ]: */
312 struct i387_fxsave_struct {
313 u16 cwd; /* Control Word */
314 u16 swd; /* Status Word */
315 u16 twd; /* Tag Word */
316 u16 fop; /* Last Instruction Opcode */
319 u64 rip; /* Instruction Pointer */
320 u64 rdp; /* Data Pointer */
323 u32 fip; /* FPU IP Offset */
324 u32 fcs; /* FPU IP Selector */
325 u32 foo; /* FPU Operand Offset */
326 u32 fos; /* FPU Operand Selector */
329 u32 mxcsr; /* MXCSR Register State */
330 u32 mxcsr_mask; /* MXCSR Mask */
332 /* 8*16 bytes for each FP-reg = 128 bytes: */
335 /* 16*16 bytes for each XMM-reg = 256 bytes: */
345 } __attribute__((aligned(16)));
347 struct i387_soft_struct {
355 /* 8*10 bytes for each FP-reg = 80 bytes: */
363 struct math_emu_info *info;
368 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
372 struct xsave_hdr_struct {
376 } __attribute__((packed));
378 struct xsave_struct {
379 struct i387_fxsave_struct i387;
380 struct xsave_hdr_struct xsave_hdr;
381 struct ymmh_struct ymmh;
382 /* new processor state extensions will go here */
383 } __attribute__ ((packed, aligned (64)));
385 union thread_xstate {
386 struct i387_fsave_struct fsave;
387 struct i387_fxsave_struct fxsave;
388 struct i387_soft_struct soft;
389 struct xsave_struct xsave;
393 unsigned int last_cpu;
394 unsigned int has_fpu;
395 union thread_xstate *state;
399 DECLARE_PER_CPU(struct orig_ist, orig_ist);
401 union irq_stack_union {
402 char irq_stack[IRQ_STACK_SIZE];
404 * GCC hardcodes the stack canary as %gs:40. Since the
405 * irq_stack is the object at %gs:0, we reserve the bottom
406 * 48 bytes of the irq stack for the canary.
410 unsigned long stack_canary;
414 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
415 DECLARE_INIT_PER_CPU(irq_stack_union);
417 DECLARE_PER_CPU(char *, irq_stack_ptr);
418 DECLARE_PER_CPU(unsigned int, irq_count);
419 extern asmlinkage void ignore_sysret(void);
421 #ifdef CONFIG_CC_STACKPROTECTOR
423 * Make sure stack canary segment base is cached-aligned:
424 * "For Intel Atom processors, avoid non zero segment base address
425 * that is not aligned to cache line boundary at all cost."
426 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
428 struct stack_canary {
429 char __pad[20]; /* canary at %gs:20 */
430 unsigned long canary;
432 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
436 extern unsigned int xstate_size;
437 extern void free_thread_xstate(struct task_struct *);
438 extern struct kmem_cache *task_xstate_cachep;
442 struct thread_struct {
443 /* Cached TLS descriptors: */
444 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
448 unsigned long sysenter_cs;
450 unsigned long usersp; /* Copy from PDA */
453 unsigned short fsindex;
454 unsigned short gsindex;
463 /* Save middle states of ptrace breakpoints */
464 struct perf_event *ptrace_bps[HBP_NUM];
465 /* Debug status used for traps, single steps, etc... */
466 unsigned long debugreg6;
467 /* Keep track of the exact dr7 value set by the user */
468 unsigned long ptrace_dr7;
471 unsigned long trap_nr;
472 unsigned long error_code;
473 /* floating point and extended processor state */
476 /* Virtual 86 mode info */
477 struct vm86_struct __user *vm86_info;
478 unsigned long screen_bitmap;
479 unsigned long v86flags;
480 unsigned long v86mask;
481 unsigned long saved_sp0;
482 unsigned int saved_fs;
483 unsigned int saved_gs;
485 /* IO permissions: */
486 unsigned long *io_bitmap_ptr;
488 /* Max allowed port in the bitmap, in bytes: */
489 unsigned io_bitmap_max;
493 * Set IOPL bits in EFLAGS from given mask
495 static inline void native_set_iopl_mask(unsigned mask)
500 asm volatile ("pushfl;"
507 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
512 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
514 tss->x86_tss.sp0 = thread->sp0;
516 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
517 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
518 tss->x86_tss.ss1 = thread->sysenter_cs;
519 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
524 static inline void native_swapgs(void)
527 asm volatile("swapgs" ::: "memory");
531 #ifdef CONFIG_PARAVIRT
532 #include <asm/paravirt.h>
534 #define __cpuid native_cpuid
535 #define paravirt_enabled() 0
537 static inline void load_sp0(struct tss_struct *tss,
538 struct thread_struct *thread)
540 native_load_sp0(tss, thread);
543 #define set_iopl_mask native_set_iopl_mask
544 #endif /* CONFIG_PARAVIRT */
547 * Save the cr4 feature set we're using (ie
548 * Pentium 4MB enable and PPro Global page
549 * enable), so that any CPU's that boot up
550 * after us can get the correct flags.
552 extern unsigned long mmu_cr4_features;
553 extern u32 *trampoline_cr4_features;
555 static inline void set_in_cr4(unsigned long mask)
559 mmu_cr4_features |= mask;
560 if (trampoline_cr4_features)
561 *trampoline_cr4_features = mmu_cr4_features;
567 static inline void clear_in_cr4(unsigned long mask)
571 mmu_cr4_features &= ~mask;
572 if (trampoline_cr4_features)
573 *trampoline_cr4_features = mmu_cr4_features;
584 /* Free all resources held by a thread. */
585 extern void release_thread(struct task_struct *);
587 unsigned long get_wchan(struct task_struct *p);
590 * Generic CPUID function
591 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
592 * resulting in stale register contents being returned.
594 static inline void cpuid(unsigned int op,
595 unsigned int *eax, unsigned int *ebx,
596 unsigned int *ecx, unsigned int *edx)
600 __cpuid(eax, ebx, ecx, edx);
603 /* Some CPUID calls want 'count' to be placed in ecx */
604 static inline void cpuid_count(unsigned int op, int count,
605 unsigned int *eax, unsigned int *ebx,
606 unsigned int *ecx, unsigned int *edx)
610 __cpuid(eax, ebx, ecx, edx);
614 * CPUID functions returning a single datum
616 static inline unsigned int cpuid_eax(unsigned int op)
618 unsigned int eax, ebx, ecx, edx;
620 cpuid(op, &eax, &ebx, &ecx, &edx);
625 static inline unsigned int cpuid_ebx(unsigned int op)
627 unsigned int eax, ebx, ecx, edx;
629 cpuid(op, &eax, &ebx, &ecx, &edx);
634 static inline unsigned int cpuid_ecx(unsigned int op)
636 unsigned int eax, ebx, ecx, edx;
638 cpuid(op, &eax, &ebx, &ecx, &edx);
643 static inline unsigned int cpuid_edx(unsigned int op)
645 unsigned int eax, ebx, ecx, edx;
647 cpuid(op, &eax, &ebx, &ecx, &edx);
652 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
653 static inline void rep_nop(void)
655 asm volatile("rep; nop" ::: "memory");
658 static inline void cpu_relax(void)
663 /* Stop speculative execution and prefetching of modified code. */
664 static inline void sync_core(void)
670 * Do a CPUID if available, otherwise do a jump. The jump
671 * can conveniently enough be the jump around CPUID.
673 asm volatile("cmpl %2,%1\n\t"
678 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
679 : "ebx", "ecx", "edx", "memory");
682 * CPUID is a barrier to speculative execution.
683 * Prefetched instructions are automatically
684 * invalidated when modified.
689 : "ebx", "ecx", "edx", "memory");
693 static inline void __monitor(const void *eax, unsigned long ecx,
696 /* "monitor %eax, %ecx, %edx;" */
697 asm volatile(".byte 0x0f, 0x01, 0xc8;"
698 :: "a" (eax), "c" (ecx), "d"(edx));
701 static inline void __mwait(unsigned long eax, unsigned long ecx)
703 /* "mwait %eax, %ecx;" */
704 asm volatile(".byte 0x0f, 0x01, 0xc9;"
705 :: "a" (eax), "c" (ecx));
708 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
711 /* "mwait %eax, %ecx;" */
712 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
713 :: "a" (eax), "c" (ecx));
716 extern void select_idle_routine(const struct cpuinfo_x86 *c);
717 extern void init_amd_e400_c1e_mask(void);
719 extern unsigned long boot_option_idle_override;
720 extern bool amd_e400_c1e_detected;
722 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
725 extern void enable_sep_cpu(void);
726 extern int sysenter_setup(void);
728 extern void early_trap_init(void);
729 void early_trap_pf_init(void);
731 /* Defined in head.S */
732 extern struct desc_ptr early_gdt_descr;
734 extern void cpu_set_gdt(int);
735 extern void switch_to_new_gdt(int);
736 extern void load_percpu_segment(int);
737 extern void cpu_init(void);
739 static inline unsigned long get_debugctlmsr(void)
741 unsigned long debugctlmsr = 0;
743 #ifndef CONFIG_X86_DEBUGCTLMSR
744 if (boot_cpu_data.x86 < 6)
747 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
752 static inline void update_debugctlmsr(unsigned long debugctlmsr)
754 #ifndef CONFIG_X86_DEBUGCTLMSR
755 if (boot_cpu_data.x86 < 6)
758 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
761 extern void set_task_blockstep(struct task_struct *task, bool on);
764 * from system description table in BIOS. Mostly for MCA use, but
765 * others may find it useful:
767 extern unsigned int machine_id;
768 extern unsigned int machine_submodel_id;
769 extern unsigned int BIOS_revision;
771 /* Boot loader type from the setup header: */
772 extern int bootloader_type;
773 extern int bootloader_version;
775 extern char ignore_fpu_irq;
777 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
778 #define ARCH_HAS_PREFETCHW
779 #define ARCH_HAS_SPINLOCK_PREFETCH
782 # define BASE_PREFETCH ASM_NOP4
783 # define ARCH_HAS_PREFETCH
785 # define BASE_PREFETCH "prefetcht0 (%1)"
789 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
791 * It's not worth to care about 3dnow prefetches for the K6
792 * because they are microcoded there and very slow.
794 static inline void prefetch(const void *x)
796 alternative_input(BASE_PREFETCH,
803 * 3dnow prefetch to get an exclusive cache line.
804 * Useful for spinlocks to avoid one state transition in the
805 * cache coherency protocol:
807 static inline void prefetchw(const void *x)
809 alternative_input(BASE_PREFETCH,
815 static inline void spin_lock_prefetch(const void *x)
822 * User space process size: 3GB (default).
824 #define TASK_SIZE PAGE_OFFSET
825 #define TASK_SIZE_MAX TASK_SIZE
826 #define STACK_TOP TASK_SIZE
827 #define STACK_TOP_MAX STACK_TOP
829 #define INIT_THREAD { \
830 .sp0 = sizeof(init_stack) + (long)&init_stack, \
832 .sysenter_cs = __KERNEL_CS, \
833 .io_bitmap_ptr = NULL, \
837 * Note that the .io_bitmap member must be extra-big. This is because
838 * the CPU will access an additional byte beyond the end of the IO
839 * permission bitmap. The extra byte must be all 1 bits, and must
840 * be within the limit.
844 .sp0 = sizeof(init_stack) + (long)&init_stack, \
845 .ss0 = __KERNEL_DS, \
846 .ss1 = __KERNEL_CS, \
847 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
849 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
852 extern unsigned long thread_saved_pc(struct task_struct *tsk);
854 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
855 #define KSTK_TOP(info) \
857 unsigned long *__ptr = (unsigned long *)(info); \
858 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
862 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
863 * This is necessary to guarantee that the entire "struct pt_regs"
864 * is accessible even if the CPU haven't stored the SS/ESP registers
865 * on the stack (interrupt gate does not save these registers
866 * when switching to the same priv ring).
867 * Therefore beware: accessing the ss/esp fields of the
868 * "struct pt_regs" is possible, but they may contain the
869 * completely wrong values.
871 #define task_pt_regs(task) \
873 struct pt_regs *__regs__; \
874 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
878 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
882 * User space process size. 47bits minus one guard page.
884 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
886 /* This decides where the kernel will search for a free chunk of vm
887 * space during mmap's.
889 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
890 0xc0000000 : 0xFFFFe000)
892 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
893 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
894 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
895 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
897 #define STACK_TOP TASK_SIZE
898 #define STACK_TOP_MAX TASK_SIZE_MAX
900 #define INIT_THREAD { \
901 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
905 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
909 * Return saved PC of a blocked thread.
910 * What is this good for? it will be always the scheduler or ret_from_fork.
912 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
914 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
915 extern unsigned long KSTK_ESP(struct task_struct *task);
918 * User space RSP while inside the SYSCALL fast path
920 DECLARE_PER_CPU(unsigned long, old_rsp);
922 #endif /* CONFIG_X86_64 */
924 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
925 unsigned long new_sp);
928 * This decides where the kernel will search for a free chunk of vm
929 * space during mmap's.
931 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
933 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
935 /* Get/set a process' ability to use the timestamp counter instruction */
936 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
937 #define SET_TSC_CTL(val) set_tsc_mode((val))
939 extern int get_tsc_mode(unsigned long adr);
940 extern int set_tsc_mode(unsigned int val);
942 extern u16 amd_get_nb_id(int cpu);
948 static inline void get_aperfmperf(struct aperfmperf *am)
950 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
952 rdmsrl(MSR_IA32_APERF, am->aperf);
953 rdmsrl(MSR_IA32_MPERF, am->mperf);
956 #define APERFMPERF_SHIFT 10
959 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
960 struct aperfmperf *new)
962 u64 aperf = new->aperf - old->aperf;
963 u64 mperf = new->mperf - old->mperf;
964 unsigned long ratio = aperf;
966 mperf >>= APERFMPERF_SHIFT;
968 ratio = div64_u64(aperf, mperf);
973 extern unsigned long arch_align_stack(unsigned long sp);
974 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
976 void default_idle(void);
978 bool xen_set_default_idle(void);
980 #define xen_set_default_idle 0
983 void stop_this_cpu(void *dummy);
985 #endif /* _ASM_X86_PROCESSOR_H */