1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
89 char wp_works_ok; /* It doesn't on 386's */
91 /* Problems on some 486Dx4's and old 386's: */
99 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
104 /* CPUID returned core id bits: */
105 __u8 x86_coreid_bits;
106 /* Max extended CPUID function supported: */
107 __u32 extended_cpuid_level;
108 /* Maximum supported CPUID level, -1=no CPUID: */
110 __u32 x86_capability[NCAPINTS];
111 char x86_vendor_id[16];
112 char x86_model_id[64];
113 /* in KB - valid for CPUS which support this call: */
115 int x86_cache_alignment; /* In bytes */
117 unsigned long loops_per_jiffy;
118 /* cpuid returned max cores value: */
122 u16 x86_clflush_size;
123 /* number of cores as seen by the OS: */
125 /* Physical processor id: */
129 /* Compute unit id */
131 /* Index into per_cpu list: */
134 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
136 #define X86_VENDOR_INTEL 0
137 #define X86_VENDOR_CYRIX 1
138 #define X86_VENDOR_AMD 2
139 #define X86_VENDOR_UMC 3
140 #define X86_VENDOR_CENTAUR 5
141 #define X86_VENDOR_TRANSMETA 7
142 #define X86_VENDOR_NSC 8
143 #define X86_VENDOR_NUM 9
145 #define X86_VENDOR_UNKNOWN 0xff
148 * capabilities of CPUs
150 extern struct cpuinfo_x86 boot_cpu_data;
151 extern struct cpuinfo_x86 new_cpu_data;
153 extern struct tss_struct doublefault_tss;
154 extern __u32 cpu_caps_cleared[NCAPINTS];
155 extern __u32 cpu_caps_set[NCAPINTS];
158 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
159 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
161 #define cpu_info boot_cpu_data
162 #define cpu_data(cpu) boot_cpu_data
165 extern const struct seq_operations cpuinfo_op;
167 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
169 extern void cpu_detect(struct cpuinfo_x86 *c);
171 extern void early_cpu_init(void);
172 extern void identify_boot_cpu(void);
173 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
174 extern void print_cpu_info(struct cpuinfo_x86 *);
175 void print_cpu_msr(struct cpuinfo_x86 *);
176 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
177 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
178 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
180 extern void detect_extended_topology(struct cpuinfo_x86 *c);
181 extern void detect_ht(struct cpuinfo_x86 *c);
183 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
184 unsigned int *ecx, unsigned int *edx)
186 /* ecx is often an input as well as an output. */
192 : "0" (*eax), "2" (*ecx)
196 static inline void load_cr3(pgd_t *pgdir)
198 write_cr3(__pa(pgdir));
202 /* This is the TSS defined by the hardware. */
204 unsigned short back_link, __blh;
206 unsigned short ss0, __ss0h;
208 /* ss1 caches MSR_IA32_SYSENTER_CS: */
209 unsigned short ss1, __ss1h;
211 unsigned short ss2, __ss2h;
223 unsigned short es, __esh;
224 unsigned short cs, __csh;
225 unsigned short ss, __ssh;
226 unsigned short ds, __dsh;
227 unsigned short fs, __fsh;
228 unsigned short gs, __gsh;
229 unsigned short ldt, __ldth;
230 unsigned short trace;
231 unsigned short io_bitmap_base;
233 } __attribute__((packed));
247 } __attribute__((packed)) ____cacheline_aligned;
253 #define IO_BITMAP_BITS 65536
254 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
255 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
256 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
257 #define INVALID_IO_BITMAP_OFFSET 0x8000
261 * The hardware state:
263 struct x86_hw_tss x86_tss;
266 * The extra 1 is there because the CPU will access an
267 * additional byte beyond the end of the IO permission
268 * bitmap. The extra byte must be all 1 bits, and must
269 * be within the limit.
271 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
274 * .. and then another 0x100 bytes for the emergency kernel stack:
276 unsigned long stack[64];
278 } ____cacheline_aligned;
280 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
283 * Save the original ist values for checking stack pointers during debugging
286 unsigned long ist[7];
289 #define MXCSR_DEFAULT 0x1f80
291 struct i387_fsave_struct {
292 u32 cwd; /* FPU Control Word */
293 u32 swd; /* FPU Status Word */
294 u32 twd; /* FPU Tag Word */
295 u32 fip; /* FPU IP Offset */
296 u32 fcs; /* FPU IP Selector */
297 u32 foo; /* FPU Operand Pointer Offset */
298 u32 fos; /* FPU Operand Pointer Selector */
300 /* 8*10 bytes for each FP-reg = 80 bytes: */
303 /* Software status information [not touched by FSAVE ]: */
307 struct i387_fxsave_struct {
308 u16 cwd; /* Control Word */
309 u16 swd; /* Status Word */
310 u16 twd; /* Tag Word */
311 u16 fop; /* Last Instruction Opcode */
314 u64 rip; /* Instruction Pointer */
315 u64 rdp; /* Data Pointer */
318 u32 fip; /* FPU IP Offset */
319 u32 fcs; /* FPU IP Selector */
320 u32 foo; /* FPU Operand Offset */
321 u32 fos; /* FPU Operand Selector */
324 u32 mxcsr; /* MXCSR Register State */
325 u32 mxcsr_mask; /* MXCSR Mask */
327 /* 8*16 bytes for each FP-reg = 128 bytes: */
330 /* 16*16 bytes for each XMM-reg = 256 bytes: */
340 } __attribute__((aligned(16)));
342 struct i387_soft_struct {
350 /* 8*10 bytes for each FP-reg = 80 bytes: */
358 struct math_emu_info *info;
363 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
367 struct xsave_hdr_struct {
371 } __attribute__((packed));
373 struct xsave_struct {
374 struct i387_fxsave_struct i387;
375 struct xsave_hdr_struct xsave_hdr;
376 struct ymmh_struct ymmh;
377 /* new processor state extensions will go here */
378 } __attribute__ ((packed, aligned (64)));
380 union thread_xstate {
381 struct i387_fsave_struct fsave;
382 struct i387_fxsave_struct fxsave;
383 struct i387_soft_struct soft;
384 struct xsave_struct xsave;
388 unsigned int last_cpu;
389 unsigned int has_fpu;
390 union thread_xstate *state;
394 DECLARE_PER_CPU(struct orig_ist, orig_ist);
396 union irq_stack_union {
397 char irq_stack[IRQ_STACK_SIZE];
399 * GCC hardcodes the stack canary as %gs:40. Since the
400 * irq_stack is the object at %gs:0, we reserve the bottom
401 * 48 bytes of the irq stack for the canary.
405 unsigned long stack_canary;
409 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
410 DECLARE_INIT_PER_CPU(irq_stack_union);
412 DECLARE_PER_CPU(char *, irq_stack_ptr);
413 DECLARE_PER_CPU(unsigned int, irq_count);
414 extern asmlinkage void ignore_sysret(void);
416 #ifdef CONFIG_CC_STACKPROTECTOR
418 * Make sure stack canary segment base is cached-aligned:
419 * "For Intel Atom processors, avoid non zero segment base address
420 * that is not aligned to cache line boundary at all cost."
421 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
423 struct stack_canary {
424 char __pad[20]; /* canary at %gs:20 */
425 unsigned long canary;
427 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
431 extern unsigned int xstate_size;
432 extern void free_thread_xstate(struct task_struct *);
433 extern struct kmem_cache *task_xstate_cachep;
437 struct thread_struct {
438 /* Cached TLS descriptors: */
439 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
443 unsigned long sysenter_cs;
445 unsigned long usersp; /* Copy from PDA */
448 unsigned short fsindex;
449 unsigned short gsindex;
458 /* Save middle states of ptrace breakpoints */
459 struct perf_event *ptrace_bps[HBP_NUM];
460 /* Debug status used for traps, single steps, etc... */
461 unsigned long debugreg6;
462 /* Keep track of the exact dr7 value set by the user */
463 unsigned long ptrace_dr7;
466 unsigned long trap_nr;
467 unsigned long error_code;
468 /* floating point and extended processor state */
471 /* Virtual 86 mode info */
472 struct vm86_struct __user *vm86_info;
473 unsigned long screen_bitmap;
474 unsigned long v86flags;
475 unsigned long v86mask;
476 unsigned long saved_sp0;
477 unsigned int saved_fs;
478 unsigned int saved_gs;
480 /* IO permissions: */
481 unsigned long *io_bitmap_ptr;
483 /* Max allowed port in the bitmap, in bytes: */
484 unsigned io_bitmap_max;
488 * Set IOPL bits in EFLAGS from given mask
490 static inline void native_set_iopl_mask(unsigned mask)
495 asm volatile ("pushfl;"
502 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
507 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
509 tss->x86_tss.sp0 = thread->sp0;
511 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
512 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
513 tss->x86_tss.ss1 = thread->sysenter_cs;
514 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
519 static inline void native_swapgs(void)
522 asm volatile("swapgs" ::: "memory");
526 #ifdef CONFIG_PARAVIRT
527 #include <asm/paravirt.h>
529 #define __cpuid native_cpuid
530 #define paravirt_enabled() 0
532 static inline void load_sp0(struct tss_struct *tss,
533 struct thread_struct *thread)
535 native_load_sp0(tss, thread);
538 #define set_iopl_mask native_set_iopl_mask
539 #endif /* CONFIG_PARAVIRT */
542 * Save the cr4 feature set we're using (ie
543 * Pentium 4MB enable and PPro Global page
544 * enable), so that any CPU's that boot up
545 * after us can get the correct flags.
547 extern unsigned long mmu_cr4_features;
548 extern u32 *trampoline_cr4_features;
550 static inline void set_in_cr4(unsigned long mask)
554 mmu_cr4_features |= mask;
555 if (trampoline_cr4_features)
556 *trampoline_cr4_features = mmu_cr4_features;
562 static inline void clear_in_cr4(unsigned long mask)
566 mmu_cr4_features &= ~mask;
567 if (trampoline_cr4_features)
568 *trampoline_cr4_features = mmu_cr4_features;
579 /* Free all resources held by a thread. */
580 extern void release_thread(struct task_struct *);
582 unsigned long get_wchan(struct task_struct *p);
585 * Generic CPUID function
586 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
587 * resulting in stale register contents being returned.
589 static inline void cpuid(unsigned int op,
590 unsigned int *eax, unsigned int *ebx,
591 unsigned int *ecx, unsigned int *edx)
595 __cpuid(eax, ebx, ecx, edx);
598 /* Some CPUID calls want 'count' to be placed in ecx */
599 static inline void cpuid_count(unsigned int op, int count,
600 unsigned int *eax, unsigned int *ebx,
601 unsigned int *ecx, unsigned int *edx)
605 __cpuid(eax, ebx, ecx, edx);
609 * CPUID functions returning a single datum
611 static inline unsigned int cpuid_eax(unsigned int op)
613 unsigned int eax, ebx, ecx, edx;
615 cpuid(op, &eax, &ebx, &ecx, &edx);
620 static inline unsigned int cpuid_ebx(unsigned int op)
622 unsigned int eax, ebx, ecx, edx;
624 cpuid(op, &eax, &ebx, &ecx, &edx);
629 static inline unsigned int cpuid_ecx(unsigned int op)
631 unsigned int eax, ebx, ecx, edx;
633 cpuid(op, &eax, &ebx, &ecx, &edx);
638 static inline unsigned int cpuid_edx(unsigned int op)
640 unsigned int eax, ebx, ecx, edx;
642 cpuid(op, &eax, &ebx, &ecx, &edx);
647 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
648 static inline void rep_nop(void)
650 asm volatile("rep; nop" ::: "memory");
653 static inline void cpu_relax(void)
658 /* Stop speculative execution and prefetching of modified code. */
659 static inline void sync_core(void)
665 * Do a CPUID if available, otherwise do a jump. The jump
666 * can conveniently enough be the jump around CPUID.
668 asm volatile("cmpl %2,%1\n\t"
673 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
674 : "ebx", "ecx", "edx", "memory");
677 * CPUID is a barrier to speculative execution.
678 * Prefetched instructions are automatically
679 * invalidated when modified.
684 : "ebx", "ecx", "edx", "memory");
688 static inline void __monitor(const void *eax, unsigned long ecx,
691 /* "monitor %eax, %ecx, %edx;" */
692 asm volatile(".byte 0x0f, 0x01, 0xc8;"
693 :: "a" (eax), "c" (ecx), "d"(edx));
696 static inline void __mwait(unsigned long eax, unsigned long ecx)
698 /* "mwait %eax, %ecx;" */
699 asm volatile(".byte 0x0f, 0x01, 0xc9;"
700 :: "a" (eax), "c" (ecx));
703 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
706 /* "mwait %eax, %ecx;" */
707 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
708 :: "a" (eax), "c" (ecx));
711 extern void select_idle_routine(const struct cpuinfo_x86 *c);
712 extern void init_amd_e400_c1e_mask(void);
714 extern unsigned long boot_option_idle_override;
715 extern bool amd_e400_c1e_detected;
717 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
720 extern void enable_sep_cpu(void);
721 extern int sysenter_setup(void);
723 extern void early_trap_init(void);
725 /* Defined in head.S */
726 extern struct desc_ptr early_gdt_descr;
728 extern void cpu_set_gdt(int);
729 extern void switch_to_new_gdt(int);
730 extern void load_percpu_segment(int);
731 extern void cpu_init(void);
733 static inline unsigned long get_debugctlmsr(void)
735 unsigned long debugctlmsr = 0;
737 #ifndef CONFIG_X86_DEBUGCTLMSR
738 if (boot_cpu_data.x86 < 6)
741 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
746 static inline void update_debugctlmsr(unsigned long debugctlmsr)
748 #ifndef CONFIG_X86_DEBUGCTLMSR
749 if (boot_cpu_data.x86 < 6)
752 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
755 extern void set_task_blockstep(struct task_struct *task, bool on);
758 * from system description table in BIOS. Mostly for MCA use, but
759 * others may find it useful:
761 extern unsigned int machine_id;
762 extern unsigned int machine_submodel_id;
763 extern unsigned int BIOS_revision;
765 /* Boot loader type from the setup header: */
766 extern int bootloader_type;
767 extern int bootloader_version;
769 extern char ignore_fpu_irq;
771 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
772 #define ARCH_HAS_PREFETCHW
773 #define ARCH_HAS_SPINLOCK_PREFETCH
776 # define BASE_PREFETCH ASM_NOP4
777 # define ARCH_HAS_PREFETCH
779 # define BASE_PREFETCH "prefetcht0 (%1)"
783 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
785 * It's not worth to care about 3dnow prefetches for the K6
786 * because they are microcoded there and very slow.
788 static inline void prefetch(const void *x)
790 alternative_input(BASE_PREFETCH,
797 * 3dnow prefetch to get an exclusive cache line.
798 * Useful for spinlocks to avoid one state transition in the
799 * cache coherency protocol:
801 static inline void prefetchw(const void *x)
803 alternative_input(BASE_PREFETCH,
809 static inline void spin_lock_prefetch(const void *x)
816 * User space process size: 3GB (default).
818 #define TASK_SIZE PAGE_OFFSET
819 #define TASK_SIZE_MAX TASK_SIZE
820 #define STACK_TOP TASK_SIZE
821 #define STACK_TOP_MAX STACK_TOP
823 #define INIT_THREAD { \
824 .sp0 = sizeof(init_stack) + (long)&init_stack, \
826 .sysenter_cs = __KERNEL_CS, \
827 .io_bitmap_ptr = NULL, \
831 * Note that the .io_bitmap member must be extra-big. This is because
832 * the CPU will access an additional byte beyond the end of the IO
833 * permission bitmap. The extra byte must be all 1 bits, and must
834 * be within the limit.
838 .sp0 = sizeof(init_stack) + (long)&init_stack, \
839 .ss0 = __KERNEL_DS, \
840 .ss1 = __KERNEL_CS, \
841 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
843 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
846 extern unsigned long thread_saved_pc(struct task_struct *tsk);
848 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
849 #define KSTK_TOP(info) \
851 unsigned long *__ptr = (unsigned long *)(info); \
852 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
856 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
857 * This is necessary to guarantee that the entire "struct pt_regs"
858 * is accessible even if the CPU haven't stored the SS/ESP registers
859 * on the stack (interrupt gate does not save these registers
860 * when switching to the same priv ring).
861 * Therefore beware: accessing the ss/esp fields of the
862 * "struct pt_regs" is possible, but they may contain the
863 * completely wrong values.
865 #define task_pt_regs(task) \
867 struct pt_regs *__regs__; \
868 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
872 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
876 * User space process size. 47bits minus one guard page.
878 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
880 /* This decides where the kernel will search for a free chunk of vm
881 * space during mmap's.
883 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
884 0xc0000000 : 0xFFFFe000)
886 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
887 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
888 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
889 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
891 #define STACK_TOP TASK_SIZE
892 #define STACK_TOP_MAX TASK_SIZE_MAX
894 #define INIT_THREAD { \
895 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
899 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
903 * Return saved PC of a blocked thread.
904 * What is this good for? it will be always the scheduler or ret_from_fork.
906 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
908 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
909 extern unsigned long KSTK_ESP(struct task_struct *task);
912 * User space RSP while inside the SYSCALL fast path
914 DECLARE_PER_CPU(unsigned long, old_rsp);
916 #endif /* CONFIG_X86_64 */
918 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
919 unsigned long new_sp);
922 * This decides where the kernel will search for a free chunk of vm
923 * space during mmap's.
925 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
927 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
929 /* Get/set a process' ability to use the timestamp counter instruction */
930 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
931 #define SET_TSC_CTL(val) set_tsc_mode((val))
933 extern int get_tsc_mode(unsigned long adr);
934 extern int set_tsc_mode(unsigned int val);
936 extern u16 amd_get_nb_id(int cpu);
942 static inline void get_aperfmperf(struct aperfmperf *am)
944 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
946 rdmsrl(MSR_IA32_APERF, am->aperf);
947 rdmsrl(MSR_IA32_MPERF, am->mperf);
950 #define APERFMPERF_SHIFT 10
953 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
954 struct aperfmperf *new)
956 u64 aperf = new->aperf - old->aperf;
957 u64 mperf = new->mperf - old->mperf;
958 unsigned long ratio = aperf;
960 mperf >>= APERFMPERF_SHIFT;
962 ratio = div64_u64(aperf, mperf);
968 * AMD errata checking
970 #ifdef CONFIG_CPU_SUP_AMD
971 extern const int amd_erratum_383[];
972 extern const int amd_erratum_400[];
973 extern bool cpu_has_amd_erratum(const int *);
975 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
976 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
977 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
978 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
979 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
980 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
981 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
984 #define cpu_has_amd_erratum(x) (false)
985 #endif /* CONFIG_CPU_SUP_AMD */
987 extern unsigned long arch_align_stack(unsigned long sp);
988 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
990 void default_idle(void);
992 bool xen_set_default_idle(void);
994 #define xen_set_default_idle 0
997 void stop_this_cpu(void *dummy);
999 #endif /* _ASM_X86_PROCESSOR_H */