5 * vmx.h: VMX Architecture related definitions
6 * Copyright (c) 2004, Intel Corporation.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
21 * A few random additions are:
22 * Copyright (C) 2006 Qumranet
23 * Avi Kivity <avi@qumranet.com>
24 * Yaniv Kamay <yaniv@qumranet.com>
28 #include <linux/types.h>
31 * Definitions of Primary Processor-Based VM-Execution Controls.
33 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
34 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
35 #define CPU_BASED_HLT_EXITING 0x00000080
36 #define CPU_BASED_INVLPG_EXITING 0x00000200
37 #define CPU_BASED_MWAIT_EXITING 0x00000400
38 #define CPU_BASED_RDPMC_EXITING 0x00000800
39 #define CPU_BASED_RDTSC_EXITING 0x00001000
40 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000
41 #define CPU_BASED_CR3_STORE_EXITING 0x00010000
42 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
43 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
44 #define CPU_BASED_TPR_SHADOW 0x00200000
45 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
46 #define CPU_BASED_MOV_DR_EXITING 0x00800000
47 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
48 #define CPU_BASED_USE_IO_BITMAPS 0x02000000
49 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000
50 #define CPU_BASED_MONITOR_EXITING 0x20000000
51 #define CPU_BASED_PAUSE_EXITING 0x40000000
52 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
54 * Definitions of Secondary Processor-Based VM-Execution Controls.
56 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
57 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002
58 #define SECONDARY_EXEC_RDTSCP 0x00000008
59 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020
60 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
61 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
62 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
65 #define PIN_BASED_EXT_INTR_MASK 0x00000001
66 #define PIN_BASED_NMI_EXITING 0x00000008
67 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
69 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002
70 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
71 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
72 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
73 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
74 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
75 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
76 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
77 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
79 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000002
80 #define VM_ENTRY_IA32E_MODE 0x00000200
81 #define VM_ENTRY_SMM 0x00000400
82 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
83 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
84 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
85 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
89 VIRTUAL_PROCESSOR_ID = 0x00000000,
90 GUEST_ES_SELECTOR = 0x00000800,
91 GUEST_CS_SELECTOR = 0x00000802,
92 GUEST_SS_SELECTOR = 0x00000804,
93 GUEST_DS_SELECTOR = 0x00000806,
94 GUEST_FS_SELECTOR = 0x00000808,
95 GUEST_GS_SELECTOR = 0x0000080a,
96 GUEST_LDTR_SELECTOR = 0x0000080c,
97 GUEST_TR_SELECTOR = 0x0000080e,
98 HOST_ES_SELECTOR = 0x00000c00,
99 HOST_CS_SELECTOR = 0x00000c02,
100 HOST_SS_SELECTOR = 0x00000c04,
101 HOST_DS_SELECTOR = 0x00000c06,
102 HOST_FS_SELECTOR = 0x00000c08,
103 HOST_GS_SELECTOR = 0x00000c0a,
104 HOST_TR_SELECTOR = 0x00000c0c,
105 IO_BITMAP_A = 0x00002000,
106 IO_BITMAP_A_HIGH = 0x00002001,
107 IO_BITMAP_B = 0x00002002,
108 IO_BITMAP_B_HIGH = 0x00002003,
109 MSR_BITMAP = 0x00002004,
110 MSR_BITMAP_HIGH = 0x00002005,
111 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
112 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
113 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
114 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
115 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
116 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
117 TSC_OFFSET = 0x00002010,
118 TSC_OFFSET_HIGH = 0x00002011,
119 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
120 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
121 APIC_ACCESS_ADDR = 0x00002014,
122 APIC_ACCESS_ADDR_HIGH = 0x00002015,
123 EPT_POINTER = 0x0000201a,
124 EPT_POINTER_HIGH = 0x0000201b,
125 GUEST_PHYSICAL_ADDRESS = 0x00002400,
126 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
127 VMCS_LINK_POINTER = 0x00002800,
128 VMCS_LINK_POINTER_HIGH = 0x00002801,
129 GUEST_IA32_DEBUGCTL = 0x00002802,
130 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
131 GUEST_IA32_PAT = 0x00002804,
132 GUEST_IA32_PAT_HIGH = 0x00002805,
133 GUEST_IA32_EFER = 0x00002806,
134 GUEST_IA32_EFER_HIGH = 0x00002807,
135 GUEST_PDPTR0 = 0x0000280a,
136 GUEST_PDPTR0_HIGH = 0x0000280b,
137 GUEST_PDPTR1 = 0x0000280c,
138 GUEST_PDPTR1_HIGH = 0x0000280d,
139 GUEST_PDPTR2 = 0x0000280e,
140 GUEST_PDPTR2_HIGH = 0x0000280f,
141 GUEST_PDPTR3 = 0x00002810,
142 GUEST_PDPTR3_HIGH = 0x00002811,
143 HOST_IA32_PAT = 0x00002c00,
144 HOST_IA32_PAT_HIGH = 0x00002c01,
145 HOST_IA32_EFER = 0x00002c02,
146 HOST_IA32_EFER_HIGH = 0x00002c03,
147 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
148 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
149 EXCEPTION_BITMAP = 0x00004004,
150 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
151 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
152 CR3_TARGET_COUNT = 0x0000400a,
153 VM_EXIT_CONTROLS = 0x0000400c,
154 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
155 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
156 VM_ENTRY_CONTROLS = 0x00004012,
157 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
158 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
159 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
160 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
161 TPR_THRESHOLD = 0x0000401c,
162 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
163 PLE_GAP = 0x00004020,
164 PLE_WINDOW = 0x00004022,
165 VM_INSTRUCTION_ERROR = 0x00004400,
166 VM_EXIT_REASON = 0x00004402,
167 VM_EXIT_INTR_INFO = 0x00004404,
168 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
169 IDT_VECTORING_INFO_FIELD = 0x00004408,
170 IDT_VECTORING_ERROR_CODE = 0x0000440a,
171 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
172 VMX_INSTRUCTION_INFO = 0x0000440e,
173 GUEST_ES_LIMIT = 0x00004800,
174 GUEST_CS_LIMIT = 0x00004802,
175 GUEST_SS_LIMIT = 0x00004804,
176 GUEST_DS_LIMIT = 0x00004806,
177 GUEST_FS_LIMIT = 0x00004808,
178 GUEST_GS_LIMIT = 0x0000480a,
179 GUEST_LDTR_LIMIT = 0x0000480c,
180 GUEST_TR_LIMIT = 0x0000480e,
181 GUEST_GDTR_LIMIT = 0x00004810,
182 GUEST_IDTR_LIMIT = 0x00004812,
183 GUEST_ES_AR_BYTES = 0x00004814,
184 GUEST_CS_AR_BYTES = 0x00004816,
185 GUEST_SS_AR_BYTES = 0x00004818,
186 GUEST_DS_AR_BYTES = 0x0000481a,
187 GUEST_FS_AR_BYTES = 0x0000481c,
188 GUEST_GS_AR_BYTES = 0x0000481e,
189 GUEST_LDTR_AR_BYTES = 0x00004820,
190 GUEST_TR_AR_BYTES = 0x00004822,
191 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
192 GUEST_ACTIVITY_STATE = 0X00004826,
193 GUEST_SYSENTER_CS = 0x0000482A,
194 HOST_IA32_SYSENTER_CS = 0x00004c00,
195 CR0_GUEST_HOST_MASK = 0x00006000,
196 CR4_GUEST_HOST_MASK = 0x00006002,
197 CR0_READ_SHADOW = 0x00006004,
198 CR4_READ_SHADOW = 0x00006006,
199 CR3_TARGET_VALUE0 = 0x00006008,
200 CR3_TARGET_VALUE1 = 0x0000600a,
201 CR3_TARGET_VALUE2 = 0x0000600c,
202 CR3_TARGET_VALUE3 = 0x0000600e,
203 EXIT_QUALIFICATION = 0x00006400,
204 GUEST_LINEAR_ADDRESS = 0x0000640a,
205 GUEST_CR0 = 0x00006800,
206 GUEST_CR3 = 0x00006802,
207 GUEST_CR4 = 0x00006804,
208 GUEST_ES_BASE = 0x00006806,
209 GUEST_CS_BASE = 0x00006808,
210 GUEST_SS_BASE = 0x0000680a,
211 GUEST_DS_BASE = 0x0000680c,
212 GUEST_FS_BASE = 0x0000680e,
213 GUEST_GS_BASE = 0x00006810,
214 GUEST_LDTR_BASE = 0x00006812,
215 GUEST_TR_BASE = 0x00006814,
216 GUEST_GDTR_BASE = 0x00006816,
217 GUEST_IDTR_BASE = 0x00006818,
218 GUEST_DR7 = 0x0000681a,
219 GUEST_RSP = 0x0000681c,
220 GUEST_RIP = 0x0000681e,
221 GUEST_RFLAGS = 0x00006820,
222 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
223 GUEST_SYSENTER_ESP = 0x00006824,
224 GUEST_SYSENTER_EIP = 0x00006826,
225 HOST_CR0 = 0x00006c00,
226 HOST_CR3 = 0x00006c02,
227 HOST_CR4 = 0x00006c04,
228 HOST_FS_BASE = 0x00006c06,
229 HOST_GS_BASE = 0x00006c08,
230 HOST_TR_BASE = 0x00006c0a,
231 HOST_GDTR_BASE = 0x00006c0c,
232 HOST_IDTR_BASE = 0x00006c0e,
233 HOST_IA32_SYSENTER_ESP = 0x00006c10,
234 HOST_IA32_SYSENTER_EIP = 0x00006c12,
235 HOST_RSP = 0x00006c14,
236 HOST_RIP = 0x00006c16,
239 #define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
241 #define EXIT_REASON_EXCEPTION_NMI 0
242 #define EXIT_REASON_EXTERNAL_INTERRUPT 1
243 #define EXIT_REASON_TRIPLE_FAULT 2
245 #define EXIT_REASON_PENDING_INTERRUPT 7
246 #define EXIT_REASON_NMI_WINDOW 8
247 #define EXIT_REASON_TASK_SWITCH 9
248 #define EXIT_REASON_CPUID 10
249 #define EXIT_REASON_HLT 12
250 #define EXIT_REASON_INVD 13
251 #define EXIT_REASON_INVLPG 14
252 #define EXIT_REASON_RDPMC 15
253 #define EXIT_REASON_RDTSC 16
254 #define EXIT_REASON_VMCALL 18
255 #define EXIT_REASON_VMCLEAR 19
256 #define EXIT_REASON_VMLAUNCH 20
257 #define EXIT_REASON_VMPTRLD 21
258 #define EXIT_REASON_VMPTRST 22
259 #define EXIT_REASON_VMREAD 23
260 #define EXIT_REASON_VMRESUME 24
261 #define EXIT_REASON_VMWRITE 25
262 #define EXIT_REASON_VMOFF 26
263 #define EXIT_REASON_VMON 27
264 #define EXIT_REASON_CR_ACCESS 28
265 #define EXIT_REASON_DR_ACCESS 29
266 #define EXIT_REASON_IO_INSTRUCTION 30
267 #define EXIT_REASON_MSR_READ 31
268 #define EXIT_REASON_MSR_WRITE 32
269 #define EXIT_REASON_INVALID_STATE 33
270 #define EXIT_REASON_MWAIT_INSTRUCTION 36
271 #define EXIT_REASON_MONITOR_INSTRUCTION 39
272 #define EXIT_REASON_PAUSE_INSTRUCTION 40
273 #define EXIT_REASON_MCE_DURING_VMENTRY 41
274 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
275 #define EXIT_REASON_APIC_ACCESS 44
276 #define EXIT_REASON_EPT_VIOLATION 48
277 #define EXIT_REASON_EPT_MISCONFIG 49
278 #define EXIT_REASON_WBINVD 54
279 #define EXIT_REASON_XSETBV 55
282 * Interruption-information format
284 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
285 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
286 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
287 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
288 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
289 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
291 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
292 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
293 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
294 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
296 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
297 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
298 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
299 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
300 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
302 /* GUEST_INTERRUPTIBILITY_INFO flags. */
303 #define GUEST_INTR_STATE_STI 0x00000001
304 #define GUEST_INTR_STATE_MOV_SS 0x00000002
305 #define GUEST_INTR_STATE_SMI 0x00000004
306 #define GUEST_INTR_STATE_NMI 0x00000008
308 /* GUEST_ACTIVITY_STATE flags */
309 #define GUEST_ACTIVITY_ACTIVE 0
310 #define GUEST_ACTIVITY_HLT 1
311 #define GUEST_ACTIVITY_SHUTDOWN 2
312 #define GUEST_ACTIVITY_WAIT_SIPI 3
315 * Exit Qualifications for MOV for Control Register Access
317 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
318 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
319 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
320 #define LMSW_SOURCE_DATA_SHIFT 16
321 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
322 #define REG_EAX (0 << 8)
323 #define REG_ECX (1 << 8)
324 #define REG_EDX (2 << 8)
325 #define REG_EBX (3 << 8)
326 #define REG_ESP (4 << 8)
327 #define REG_EBP (5 << 8)
328 #define REG_ESI (6 << 8)
329 #define REG_EDI (7 << 8)
330 #define REG_R8 (8 << 8)
331 #define REG_R9 (9 << 8)
332 #define REG_R10 (10 << 8)
333 #define REG_R11 (11 << 8)
334 #define REG_R12 (12 << 8)
335 #define REG_R13 (13 << 8)
336 #define REG_R14 (14 << 8)
337 #define REG_R15 (15 << 8)
340 * Exit Qualifications for MOV for Debug Register Access
342 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
343 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
344 #define TYPE_MOV_TO_DR (0 << 4)
345 #define TYPE_MOV_FROM_DR (1 << 4)
346 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
350 #define SEGMENT_AR_L_MASK (1 << 13)
352 #define AR_TYPE_ACCESSES_MASK 1
353 #define AR_TYPE_READABLE_MASK (1 << 1)
354 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
355 #define AR_TYPE_CODE_MASK (1 << 3)
356 #define AR_TYPE_MASK 0x0f
357 #define AR_TYPE_BUSY_64_TSS 11
358 #define AR_TYPE_BUSY_32_TSS 11
359 #define AR_TYPE_BUSY_16_TSS 3
360 #define AR_TYPE_LDT 2
362 #define AR_UNUSABLE_MASK (1 << 16)
363 #define AR_S_MASK (1 << 4)
364 #define AR_P_MASK (1 << 7)
365 #define AR_L_MASK (1 << 13)
366 #define AR_DB_MASK (1 << 14)
367 #define AR_G_MASK (1 << 15)
368 #define AR_DPL_SHIFT 5
369 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
371 #define AR_RESERVD_MASK 0xfffe0f00
373 #define TSS_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 0)
374 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 1)
375 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 2)
377 #define VMX_NR_VPIDS (1 << 16)
378 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
379 #define VMX_VPID_EXTENT_ALL_CONTEXT 2
381 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
382 #define VMX_EPT_EXTENT_CONTEXT 1
383 #define VMX_EPT_EXTENT_GLOBAL 2
385 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
386 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
387 #define VMX_EPTP_UC_BIT (1ull << 8)
388 #define VMX_EPTP_WB_BIT (1ull << 14)
389 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
390 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
391 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT (1ull << 24)
392 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
393 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
395 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
396 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
398 #define VMX_EPT_DEFAULT_GAW 3
399 #define VMX_EPT_MAX_GAW 0x4
400 #define VMX_EPT_MT_EPTE_SHIFT 3
401 #define VMX_EPT_GAW_EPTP_SHIFT 3
402 #define VMX_EPT_DEFAULT_MT 0x6ull
403 #define VMX_EPT_READABLE_MASK 0x1ull
404 #define VMX_EPT_WRITABLE_MASK 0x2ull
405 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
406 #define VMX_EPT_IPAT_BIT (1ull << 6)
408 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
411 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
412 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
413 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
414 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
415 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
416 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
417 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
418 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
419 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
420 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
421 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
423 struct vmx_msr_entry {
430 * VM-instruction error numbers
432 enum vm_instruction_error_number {
433 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
434 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
435 VMXERR_VMCLEAR_VMXON_POINTER = 3,
436 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
437 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
438 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
439 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
440 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
441 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
442 VMXERR_VMPTRLD_VMXON_POINTER = 10,
443 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
444 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
445 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
446 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
447 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
448 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
449 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
450 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
451 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
452 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
453 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
454 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
455 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
456 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
457 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,