2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
31 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
33 #define EXIT_LOOP_COUNT 10000000
35 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 /* A list of preallocated protection domains */
38 static LIST_HEAD(iommu_pd_list);
39 static DEFINE_SPINLOCK(iommu_pd_list_lock);
42 * general struct to manage commands send to an IOMMU
48 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
49 struct unity_map_entry *e);
51 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
52 static int iommu_has_npcache(struct amd_iommu *iommu)
54 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
57 /****************************************************************************
59 * Interrupt handling functions
61 ****************************************************************************/
63 static void iommu_print_event(void *__evt)
66 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
67 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
68 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
69 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
70 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
72 printk(KERN_ERR "AMD IOMMU: Event logged [");
75 case EVENT_TYPE_ILL_DEV:
76 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
77 "address=0x%016llx flags=0x%04x]\n",
78 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
81 case EVENT_TYPE_IO_FAULT:
82 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
83 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
84 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
85 domid, address, flags);
87 case EVENT_TYPE_DEV_TAB_ERR:
88 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
89 "address=0x%016llx flags=0x%04x]\n",
90 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
93 case EVENT_TYPE_PAGE_TAB_ERR:
94 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
95 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
96 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
97 domid, address, flags);
99 case EVENT_TYPE_ILL_CMD:
100 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
102 case EVENT_TYPE_CMD_HARD_ERR:
103 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
104 "flags=0x%04x]\n", address, flags);
106 case EVENT_TYPE_IOTLB_INV_TO:
107 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
108 "address=0x%016llx]\n",
109 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
112 case EVENT_TYPE_INV_DEV_REQ:
113 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
114 "address=0x%016llx flags=0x%04x]\n",
115 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
119 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
123 static void iommu_poll_events(struct amd_iommu *iommu)
128 spin_lock_irqsave(&iommu->lock, flags);
130 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
131 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
133 while (head != tail) {
134 iommu_print_event(iommu->evt_buf + head);
135 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
138 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
140 spin_unlock_irqrestore(&iommu->lock, flags);
143 irqreturn_t amd_iommu_int_handler(int irq, void *data)
145 struct amd_iommu *iommu;
147 list_for_each_entry(iommu, &amd_iommu_list, list)
148 iommu_poll_events(iommu);
153 /****************************************************************************
155 * IOMMU command queuing functions
157 ****************************************************************************/
160 * Writes the command to the IOMMUs command buffer and informs the
161 * hardware about the new command. Must be called with iommu->lock held.
163 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
168 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
169 target = iommu->cmd_buf + tail;
170 memcpy_toio(target, cmd, sizeof(*cmd));
171 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
172 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
175 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
181 * General queuing function for commands. Takes iommu->lock and calls
182 * __iommu_queue_command().
184 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
189 spin_lock_irqsave(&iommu->lock, flags);
190 ret = __iommu_queue_command(iommu, cmd);
192 iommu->need_sync = 1;
193 spin_unlock_irqrestore(&iommu->lock, flags);
199 * This function waits until an IOMMU has completed a completion
202 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
208 while (!ready && (i < EXIT_LOOP_COUNT)) {
210 /* wait for the bit to become one */
211 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
212 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
215 /* set bit back to zero */
216 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
217 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
219 if (unlikely(i == EXIT_LOOP_COUNT))
220 panic("AMD IOMMU: Completion wait loop failed\n");
224 * This function queues a completion wait command into the command
227 static int __iommu_completion_wait(struct amd_iommu *iommu)
229 struct iommu_cmd cmd;
231 memset(&cmd, 0, sizeof(cmd));
232 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
233 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
235 return __iommu_queue_command(iommu, &cmd);
239 * This function is called whenever we need to ensure that the IOMMU has
240 * completed execution of all commands we sent. It sends a
241 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
242 * us about that by writing a value to a physical address we pass with
245 static int iommu_completion_wait(struct amd_iommu *iommu)
250 spin_lock_irqsave(&iommu->lock, flags);
252 if (!iommu->need_sync)
255 ret = __iommu_completion_wait(iommu);
257 iommu->need_sync = 0;
262 __iommu_wait_for_completion(iommu);
265 spin_unlock_irqrestore(&iommu->lock, flags);
271 * Command send function for invalidating a device table entry
273 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
275 struct iommu_cmd cmd;
278 BUG_ON(iommu == NULL);
280 memset(&cmd, 0, sizeof(cmd));
281 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
284 ret = iommu_queue_command(iommu, &cmd);
289 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
290 u16 domid, int pde, int s)
292 memset(cmd, 0, sizeof(*cmd));
293 address &= PAGE_MASK;
294 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
295 cmd->data[1] |= domid;
296 cmd->data[2] = lower_32_bits(address);
297 cmd->data[3] = upper_32_bits(address);
298 if (s) /* size bit - we flush more than one 4kb page */
299 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
300 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
301 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
305 * Generic command send function for invalidaing TLB entries
307 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
308 u64 address, u16 domid, int pde, int s)
310 struct iommu_cmd cmd;
313 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
315 ret = iommu_queue_command(iommu, &cmd);
321 * TLB invalidation function which is called from the mapping functions.
322 * It invalidates a single PTE if the range to flush is within a single
323 * page. Otherwise it flushes the whole TLB of the IOMMU.
325 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
326 u64 address, size_t size)
329 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
331 address &= PAGE_MASK;
335 * If we have to flush more than one page, flush all
336 * TLB entries for this domain
338 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
342 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
347 /* Flush the whole IO/TLB for a given protection domain */
348 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
350 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
352 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
355 #ifdef CONFIG_IOMMU_API
357 * This function is used to flush the IO/TLB for a given protection domain
358 * on every IOMMU in the system
360 static void iommu_flush_domain(u16 domid)
363 struct amd_iommu *iommu;
364 struct iommu_cmd cmd;
366 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
369 list_for_each_entry(iommu, &amd_iommu_list, list) {
370 spin_lock_irqsave(&iommu->lock, flags);
371 __iommu_queue_command(iommu, &cmd);
372 __iommu_completion_wait(iommu);
373 __iommu_wait_for_completion(iommu);
374 spin_unlock_irqrestore(&iommu->lock, flags);
379 /****************************************************************************
381 * The functions below are used the create the page table mappings for
382 * unity mapped regions.
384 ****************************************************************************/
387 * Generic mapping functions. It maps a physical address into a DMA
388 * address space. It allocates the page table pages if necessary.
389 * In the future it can be extended to a generic mapping function
390 * supporting all features of AMD IOMMU page tables like level skipping
391 * and full 64 bit address spaces.
393 static int iommu_map_page(struct protection_domain *dom,
394 unsigned long bus_addr,
395 unsigned long phys_addr,
398 u64 __pte, *pte, *page;
400 bus_addr = PAGE_ALIGN(bus_addr);
401 phys_addr = PAGE_ALIGN(phys_addr);
403 /* only support 512GB address spaces for now */
404 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
407 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
409 if (!IOMMU_PTE_PRESENT(*pte)) {
410 page = (u64 *)get_zeroed_page(GFP_KERNEL);
413 *pte = IOMMU_L2_PDE(virt_to_phys(page));
416 pte = IOMMU_PTE_PAGE(*pte);
417 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
419 if (!IOMMU_PTE_PRESENT(*pte)) {
420 page = (u64 *)get_zeroed_page(GFP_KERNEL);
423 *pte = IOMMU_L1_PDE(virt_to_phys(page));
426 pte = IOMMU_PTE_PAGE(*pte);
427 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
429 if (IOMMU_PTE_PRESENT(*pte))
432 __pte = phys_addr | IOMMU_PTE_P;
433 if (prot & IOMMU_PROT_IR)
434 __pte |= IOMMU_PTE_IR;
435 if (prot & IOMMU_PROT_IW)
436 __pte |= IOMMU_PTE_IW;
444 * This function checks if a specific unity mapping entry is needed for
445 * this specific IOMMU.
447 static int iommu_for_unity_map(struct amd_iommu *iommu,
448 struct unity_map_entry *entry)
452 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
453 bdf = amd_iommu_alias_table[i];
454 if (amd_iommu_rlookup_table[bdf] == iommu)
462 * Init the unity mappings for a specific IOMMU in the system
464 * Basically iterates over all unity mapping entries and applies them to
465 * the default domain DMA of that IOMMU if necessary.
467 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
469 struct unity_map_entry *entry;
472 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
473 if (!iommu_for_unity_map(iommu, entry))
475 ret = dma_ops_unity_map(iommu->default_dom, entry);
484 * This function actually applies the mapping to the page table of the
487 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
488 struct unity_map_entry *e)
493 for (addr = e->address_start; addr < e->address_end;
495 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
499 * if unity mapping is in aperture range mark the page
500 * as allocated in the aperture
502 if (addr < dma_dom->aperture_size)
503 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
510 * Inits the unity mappings required for a specific device
512 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
515 struct unity_map_entry *e;
518 list_for_each_entry(e, &amd_iommu_unity_map, list) {
519 if (!(devid >= e->devid_start && devid <= e->devid_end))
521 ret = dma_ops_unity_map(dma_dom, e);
529 /****************************************************************************
531 * The next functions belong to the address allocator for the dma_ops
532 * interface functions. They work like the allocators in the other IOMMU
533 * drivers. Its basically a bitmap which marks the allocated pages in
534 * the aperture. Maybe it could be enhanced in the future to a more
535 * efficient allocator.
537 ****************************************************************************/
540 * The address allocator core function.
542 * called with domain->lock held
544 static unsigned long dma_ops_alloc_addresses(struct device *dev,
545 struct dma_ops_domain *dom,
547 unsigned long align_mask,
551 unsigned long address;
552 unsigned long boundary_size;
554 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
555 PAGE_SIZE) >> PAGE_SHIFT;
556 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
557 dma_mask >> PAGE_SHIFT);
559 if (dom->next_bit >= limit) {
561 dom->need_flush = true;
564 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
565 0 , boundary_size, align_mask);
567 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
568 0, boundary_size, align_mask);
569 dom->need_flush = true;
572 if (likely(address != -1)) {
573 dom->next_bit = address + pages;
574 address <<= PAGE_SHIFT;
576 address = bad_dma_address;
578 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
584 * The address free function.
586 * called with domain->lock held
588 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
589 unsigned long address,
592 address >>= PAGE_SHIFT;
593 iommu_area_free(dom->bitmap, address, pages);
595 if (address >= dom->next_bit)
596 dom->need_flush = true;
599 /****************************************************************************
601 * The next functions belong to the domain allocation. A domain is
602 * allocated for every IOMMU as the default domain. If device isolation
603 * is enabled, every device get its own domain. The most important thing
604 * about domains is the page table mapping the DMA address space they
607 ****************************************************************************/
609 static u16 domain_id_alloc(void)
614 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
615 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
617 if (id > 0 && id < MAX_DOMAIN_ID)
618 __set_bit(id, amd_iommu_pd_alloc_bitmap);
621 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
626 #ifdef CONFIG_IOMMU_API
627 static void domain_id_free(int id)
631 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
632 if (id > 0 && id < MAX_DOMAIN_ID)
633 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
634 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
639 * Used to reserve address ranges in the aperture (e.g. for exclusion
642 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
643 unsigned long start_page,
646 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
648 if (start_page + pages > last_page)
649 pages = last_page - start_page;
651 iommu_area_reserve(dom->bitmap, start_page, pages);
654 static void free_pagetable(struct protection_domain *domain)
659 p1 = domain->pt_root;
664 for (i = 0; i < 512; ++i) {
665 if (!IOMMU_PTE_PRESENT(p1[i]))
668 p2 = IOMMU_PTE_PAGE(p1[i]);
669 for (j = 0; j < 512; ++j) {
670 if (!IOMMU_PTE_PRESENT(p2[j]))
672 p3 = IOMMU_PTE_PAGE(p2[j]);
673 free_page((unsigned long)p3);
676 free_page((unsigned long)p2);
679 free_page((unsigned long)p1);
681 domain->pt_root = NULL;
685 * Free a domain, only used if something went wrong in the
686 * allocation path and we need to free an already allocated page table
688 static void dma_ops_domain_free(struct dma_ops_domain *dom)
693 free_pagetable(&dom->domain);
695 kfree(dom->pte_pages);
703 * Allocates a new protection domain usable for the dma_ops functions.
704 * It also intializes the page table and the address allocator data
705 * structures required for the dma_ops interface
707 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
710 struct dma_ops_domain *dma_dom;
711 unsigned i, num_pte_pages;
716 * Currently the DMA aperture must be between 32 MB and 1GB in size
718 if ((order < 25) || (order > 30))
721 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
725 spin_lock_init(&dma_dom->domain.lock);
727 dma_dom->domain.id = domain_id_alloc();
728 if (dma_dom->domain.id == 0)
730 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
731 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
732 dma_dom->domain.priv = dma_dom;
733 if (!dma_dom->domain.pt_root)
735 dma_dom->aperture_size = (1ULL << order);
736 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
738 if (!dma_dom->bitmap)
741 * mark the first page as allocated so we never return 0 as
742 * a valid dma-address. So we can use 0 as error value
744 dma_dom->bitmap[0] = 1;
745 dma_dom->next_bit = 0;
747 dma_dom->need_flush = false;
748 dma_dom->target_dev = 0xffff;
750 /* Intialize the exclusion range if necessary */
751 if (iommu->exclusion_start &&
752 iommu->exclusion_start < dma_dom->aperture_size) {
753 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
754 int pages = iommu_num_pages(iommu->exclusion_start,
755 iommu->exclusion_length,
757 dma_ops_reserve_addresses(dma_dom, startpage, pages);
761 * At the last step, build the page tables so we don't need to
762 * allocate page table pages in the dma_ops mapping/unmapping
765 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
766 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
768 if (!dma_dom->pte_pages)
771 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
775 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
777 for (i = 0; i < num_pte_pages; ++i) {
778 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
779 if (!dma_dom->pte_pages[i])
781 address = virt_to_phys(dma_dom->pte_pages[i]);
782 l2_pde[i] = IOMMU_L1_PDE(address);
788 dma_ops_domain_free(dma_dom);
794 * Find out the protection domain structure for a given PCI device. This
795 * will give us the pointer to the page table root for example.
797 static struct protection_domain *domain_for_device(u16 devid)
799 struct protection_domain *dom;
802 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
803 dom = amd_iommu_pd_table[devid];
804 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
810 * If a device is not yet associated with a domain, this function does
811 * assigns it visible for the hardware
813 static void set_device_domain(struct amd_iommu *iommu,
814 struct protection_domain *domain,
819 u64 pte_root = virt_to_phys(domain->pt_root);
821 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
822 << DEV_ENTRY_MODE_SHIFT;
823 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
825 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
826 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
827 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
828 amd_iommu_dev_table[devid].data[2] = domain->id;
830 amd_iommu_pd_table[devid] = domain;
831 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
833 iommu_queue_inv_dev_entry(iommu, devid);
836 /*****************************************************************************
838 * The next functions belong to the dma_ops mapping/unmapping code.
840 *****************************************************************************/
843 * This function checks if the driver got a valid device from the caller to
844 * avoid dereferencing invalid pointers.
846 static bool check_device(struct device *dev)
848 if (!dev || !dev->dma_mask)
855 * In this function the list of preallocated protection domains is traversed to
856 * find the domain for a specific device
858 static struct dma_ops_domain *find_protection_domain(u16 devid)
860 struct dma_ops_domain *entry, *ret = NULL;
863 if (list_empty(&iommu_pd_list))
866 spin_lock_irqsave(&iommu_pd_list_lock, flags);
868 list_for_each_entry(entry, &iommu_pd_list, list) {
869 if (entry->target_dev == devid) {
875 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
881 * In the dma_ops path we only have the struct device. This function
882 * finds the corresponding IOMMU, the protection domain and the
883 * requestor id for a given device.
884 * If the device is not yet associated with a domain this is also done
887 static int get_device_resources(struct device *dev,
888 struct amd_iommu **iommu,
889 struct protection_domain **domain,
892 struct dma_ops_domain *dma_dom;
893 struct pci_dev *pcidev;
900 if (dev->bus != &pci_bus_type)
903 pcidev = to_pci_dev(dev);
904 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
906 /* device not translated by any IOMMU in the system? */
907 if (_bdf > amd_iommu_last_bdf)
910 *bdf = amd_iommu_alias_table[_bdf];
912 *iommu = amd_iommu_rlookup_table[*bdf];
915 *domain = domain_for_device(*bdf);
916 if (*domain == NULL) {
917 dma_dom = find_protection_domain(*bdf);
919 dma_dom = (*iommu)->default_dom;
920 *domain = &dma_dom->domain;
921 set_device_domain(*iommu, *domain, *bdf);
922 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
923 "device ", (*domain)->id);
924 print_devid(_bdf, 1);
927 if (domain_for_device(_bdf) == NULL)
928 set_device_domain(*iommu, *domain, _bdf);
934 * This is the generic map function. It maps one 4kb page at paddr to
935 * the given address in the DMA address space for the domain.
937 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
938 struct dma_ops_domain *dom,
939 unsigned long address,
945 WARN_ON(address > dom->aperture_size);
949 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
950 pte += IOMMU_PTE_L0_INDEX(address);
952 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
954 if (direction == DMA_TO_DEVICE)
955 __pte |= IOMMU_PTE_IR;
956 else if (direction == DMA_FROM_DEVICE)
957 __pte |= IOMMU_PTE_IW;
958 else if (direction == DMA_BIDIRECTIONAL)
959 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
965 return (dma_addr_t)address;
969 * The generic unmapping function for on page in the DMA address space.
971 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
972 struct dma_ops_domain *dom,
973 unsigned long address)
977 if (address >= dom->aperture_size)
980 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
982 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
983 pte += IOMMU_PTE_L0_INDEX(address);
991 * This function contains common code for mapping of a physically
992 * contiguous memory region into DMA address space. It is used by all
993 * mapping functions provided with this IOMMU driver.
994 * Must be called with the domain lock held.
996 static dma_addr_t __map_single(struct device *dev,
997 struct amd_iommu *iommu,
998 struct dma_ops_domain *dma_dom,
1005 dma_addr_t offset = paddr & ~PAGE_MASK;
1006 dma_addr_t address, start;
1008 unsigned long align_mask = 0;
1011 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1015 align_mask = (1UL << get_order(size)) - 1;
1017 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1019 if (unlikely(address == bad_dma_address))
1023 for (i = 0; i < pages; ++i) {
1024 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1030 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1031 iommu_flush_tlb(iommu, dma_dom->domain.id);
1032 dma_dom->need_flush = false;
1033 } else if (unlikely(iommu_has_npcache(iommu)))
1034 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1041 * Does the reverse of the __map_single function. Must be called with
1042 * the domain lock held too
1044 static void __unmap_single(struct amd_iommu *iommu,
1045 struct dma_ops_domain *dma_dom,
1046 dma_addr_t dma_addr,
1050 dma_addr_t i, start;
1053 if ((dma_addr == bad_dma_address) ||
1054 (dma_addr + size > dma_dom->aperture_size))
1057 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1058 dma_addr &= PAGE_MASK;
1061 for (i = 0; i < pages; ++i) {
1062 dma_ops_domain_unmap(iommu, dma_dom, start);
1066 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1068 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1069 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1070 dma_dom->need_flush = false;
1075 * The exported map_single function for dma_ops.
1077 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1078 size_t size, int dir)
1080 unsigned long flags;
1081 struct amd_iommu *iommu;
1082 struct protection_domain *domain;
1087 if (!check_device(dev))
1088 return bad_dma_address;
1090 dma_mask = *dev->dma_mask;
1092 get_device_resources(dev, &iommu, &domain, &devid);
1094 if (iommu == NULL || domain == NULL)
1095 /* device not handled by any AMD IOMMU */
1096 return (dma_addr_t)paddr;
1098 spin_lock_irqsave(&domain->lock, flags);
1099 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1101 if (addr == bad_dma_address)
1104 iommu_completion_wait(iommu);
1107 spin_unlock_irqrestore(&domain->lock, flags);
1113 * The exported unmap_single function for dma_ops.
1115 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1116 size_t size, int dir)
1118 unsigned long flags;
1119 struct amd_iommu *iommu;
1120 struct protection_domain *domain;
1123 if (!check_device(dev) ||
1124 !get_device_resources(dev, &iommu, &domain, &devid))
1125 /* device not handled by any AMD IOMMU */
1128 spin_lock_irqsave(&domain->lock, flags);
1130 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1132 iommu_completion_wait(iommu);
1134 spin_unlock_irqrestore(&domain->lock, flags);
1138 * This is a special map_sg function which is used if we should map a
1139 * device which is not handled by an AMD IOMMU in the system.
1141 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1142 int nelems, int dir)
1144 struct scatterlist *s;
1147 for_each_sg(sglist, s, nelems, i) {
1148 s->dma_address = (dma_addr_t)sg_phys(s);
1149 s->dma_length = s->length;
1156 * The exported map_sg function for dma_ops (handles scatter-gather
1159 static int map_sg(struct device *dev, struct scatterlist *sglist,
1160 int nelems, int dir)
1162 unsigned long flags;
1163 struct amd_iommu *iommu;
1164 struct protection_domain *domain;
1167 struct scatterlist *s;
1169 int mapped_elems = 0;
1172 if (!check_device(dev))
1175 dma_mask = *dev->dma_mask;
1177 get_device_resources(dev, &iommu, &domain, &devid);
1179 if (!iommu || !domain)
1180 return map_sg_no_iommu(dev, sglist, nelems, dir);
1182 spin_lock_irqsave(&domain->lock, flags);
1184 for_each_sg(sglist, s, nelems, i) {
1187 s->dma_address = __map_single(dev, iommu, domain->priv,
1188 paddr, s->length, dir, false,
1191 if (s->dma_address) {
1192 s->dma_length = s->length;
1198 iommu_completion_wait(iommu);
1201 spin_unlock_irqrestore(&domain->lock, flags);
1203 return mapped_elems;
1205 for_each_sg(sglist, s, mapped_elems, i) {
1207 __unmap_single(iommu, domain->priv, s->dma_address,
1208 s->dma_length, dir);
1209 s->dma_address = s->dma_length = 0;
1218 * The exported map_sg function for dma_ops (handles scatter-gather
1221 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1222 int nelems, int dir)
1224 unsigned long flags;
1225 struct amd_iommu *iommu;
1226 struct protection_domain *domain;
1227 struct scatterlist *s;
1231 if (!check_device(dev) ||
1232 !get_device_resources(dev, &iommu, &domain, &devid))
1235 spin_lock_irqsave(&domain->lock, flags);
1237 for_each_sg(sglist, s, nelems, i) {
1238 __unmap_single(iommu, domain->priv, s->dma_address,
1239 s->dma_length, dir);
1240 s->dma_address = s->dma_length = 0;
1243 iommu_completion_wait(iommu);
1245 spin_unlock_irqrestore(&domain->lock, flags);
1249 * The exported alloc_coherent function for dma_ops.
1251 static void *alloc_coherent(struct device *dev, size_t size,
1252 dma_addr_t *dma_addr, gfp_t flag)
1254 unsigned long flags;
1256 struct amd_iommu *iommu;
1257 struct protection_domain *domain;
1260 u64 dma_mask = dev->coherent_dma_mask;
1262 if (!check_device(dev))
1265 if (!get_device_resources(dev, &iommu, &domain, &devid))
1266 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1269 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1273 paddr = virt_to_phys(virt_addr);
1275 if (!iommu || !domain) {
1276 *dma_addr = (dma_addr_t)paddr;
1281 dma_mask = *dev->dma_mask;
1283 spin_lock_irqsave(&domain->lock, flags);
1285 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1286 size, DMA_BIDIRECTIONAL, true, dma_mask);
1288 if (*dma_addr == bad_dma_address) {
1289 free_pages((unsigned long)virt_addr, get_order(size));
1294 iommu_completion_wait(iommu);
1297 spin_unlock_irqrestore(&domain->lock, flags);
1303 * The exported free_coherent function for dma_ops.
1305 static void free_coherent(struct device *dev, size_t size,
1306 void *virt_addr, dma_addr_t dma_addr)
1308 unsigned long flags;
1309 struct amd_iommu *iommu;
1310 struct protection_domain *domain;
1313 if (!check_device(dev))
1316 get_device_resources(dev, &iommu, &domain, &devid);
1318 if (!iommu || !domain)
1321 spin_lock_irqsave(&domain->lock, flags);
1323 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1325 iommu_completion_wait(iommu);
1327 spin_unlock_irqrestore(&domain->lock, flags);
1330 free_pages((unsigned long)virt_addr, get_order(size));
1334 * This function is called by the DMA layer to find out if we can handle a
1335 * particular device. It is part of the dma_ops.
1337 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1340 struct pci_dev *pcidev;
1342 /* No device or no PCI device */
1343 if (!dev || dev->bus != &pci_bus_type)
1346 pcidev = to_pci_dev(dev);
1348 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1350 /* Out of our scope? */
1351 if (bdf > amd_iommu_last_bdf)
1358 * The function for pre-allocating protection domains.
1360 * If the driver core informs the DMA layer if a driver grabs a device
1361 * we don't need to preallocate the protection domains anymore.
1362 * For now we have to.
1364 void prealloc_protection_domains(void)
1366 struct pci_dev *dev = NULL;
1367 struct dma_ops_domain *dma_dom;
1368 struct amd_iommu *iommu;
1369 int order = amd_iommu_aperture_order;
1372 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1373 devid = (dev->bus->number << 8) | dev->devfn;
1374 if (devid > amd_iommu_last_bdf)
1376 devid = amd_iommu_alias_table[devid];
1377 if (domain_for_device(devid))
1379 iommu = amd_iommu_rlookup_table[devid];
1382 dma_dom = dma_ops_domain_alloc(iommu, order);
1385 init_unity_mappings_for_device(dma_dom, devid);
1386 dma_dom->target_dev = devid;
1388 list_add_tail(&dma_dom->list, &iommu_pd_list);
1392 static struct dma_mapping_ops amd_iommu_dma_ops = {
1393 .alloc_coherent = alloc_coherent,
1394 .free_coherent = free_coherent,
1395 .map_single = map_single,
1396 .unmap_single = unmap_single,
1398 .unmap_sg = unmap_sg,
1399 .dma_supported = amd_iommu_dma_supported,
1403 * The function which clues the AMD IOMMU driver into dma_ops.
1405 int __init amd_iommu_init_dma_ops(void)
1407 struct amd_iommu *iommu;
1408 int order = amd_iommu_aperture_order;
1412 * first allocate a default protection domain for every IOMMU we
1413 * found in the system. Devices not assigned to any other
1414 * protection domain will be assigned to the default one.
1416 list_for_each_entry(iommu, &amd_iommu_list, list) {
1417 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1418 if (iommu->default_dom == NULL)
1420 ret = iommu_init_unity_mappings(iommu);
1426 * If device isolation is enabled, pre-allocate the protection
1427 * domains for each device.
1429 if (amd_iommu_isolate)
1430 prealloc_protection_domains();
1434 bad_dma_address = 0;
1435 #ifdef CONFIG_GART_IOMMU
1436 gart_iommu_aperture_disabled = 1;
1437 gart_iommu_aperture = 0;
1440 /* Make the driver finally visible to the drivers */
1441 dma_ops = &amd_iommu_dma_ops;
1447 list_for_each_entry(iommu, &amd_iommu_list, list) {
1448 if (iommu->default_dom)
1449 dma_ops_domain_free(iommu->default_dom);