2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
70 DECLARE_STATS_COUNTER(cnt_map_sg);
71 DECLARE_STATS_COUNTER(cnt_unmap_sg);
72 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
73 DECLARE_STATS_COUNTER(cnt_free_coherent);
74 DECLARE_STATS_COUNTER(cross_page);
75 DECLARE_STATS_COUNTER(domain_flush_single);
76 DECLARE_STATS_COUNTER(domain_flush_all);
77 DECLARE_STATS_COUNTER(alloced_io_mem);
79 static struct dentry *stats_dir;
80 static struct dentry *de_isolate;
81 static struct dentry *de_fflush;
83 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
85 if (stats_dir == NULL)
88 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
92 static void amd_iommu_stats_init(void)
94 stats_dir = debugfs_create_dir("amd-iommu", NULL);
95 if (stats_dir == NULL)
98 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
99 (u32 *)&amd_iommu_isolate);
101 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
102 (u32 *)&amd_iommu_unmap_flush);
104 amd_iommu_stats_add(&compl_wait);
105 amd_iommu_stats_add(&cnt_map_single);
106 amd_iommu_stats_add(&cnt_unmap_single);
107 amd_iommu_stats_add(&cnt_map_sg);
108 amd_iommu_stats_add(&cnt_unmap_sg);
109 amd_iommu_stats_add(&cnt_alloc_coherent);
110 amd_iommu_stats_add(&cnt_free_coherent);
111 amd_iommu_stats_add(&cross_page);
112 amd_iommu_stats_add(&domain_flush_single);
113 amd_iommu_stats_add(&domain_flush_all);
114 amd_iommu_stats_add(&alloced_io_mem);
119 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
120 static int iommu_has_npcache(struct amd_iommu *iommu)
122 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
125 /****************************************************************************
127 * Interrupt handling functions
129 ****************************************************************************/
131 static void iommu_print_event(void *__evt)
134 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
135 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
136 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
137 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
138 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
140 printk(KERN_ERR "AMD IOMMU: Event logged [");
143 case EVENT_TYPE_ILL_DEV:
144 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
145 "address=0x%016llx flags=0x%04x]\n",
146 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
149 case EVENT_TYPE_IO_FAULT:
150 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
151 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
152 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
153 domid, address, flags);
155 case EVENT_TYPE_DEV_TAB_ERR:
156 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
157 "address=0x%016llx flags=0x%04x]\n",
158 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
161 case EVENT_TYPE_PAGE_TAB_ERR:
162 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
163 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
164 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
165 domid, address, flags);
167 case EVENT_TYPE_ILL_CMD:
168 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
170 case EVENT_TYPE_CMD_HARD_ERR:
171 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
172 "flags=0x%04x]\n", address, flags);
174 case EVENT_TYPE_IOTLB_INV_TO:
175 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
176 "address=0x%016llx]\n",
177 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
180 case EVENT_TYPE_INV_DEV_REQ:
181 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
182 "address=0x%016llx flags=0x%04x]\n",
183 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
191 static void iommu_poll_events(struct amd_iommu *iommu)
196 spin_lock_irqsave(&iommu->lock, flags);
198 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
199 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
201 while (head != tail) {
202 iommu_print_event(iommu->evt_buf + head);
203 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
206 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
208 spin_unlock_irqrestore(&iommu->lock, flags);
211 irqreturn_t amd_iommu_int_handler(int irq, void *data)
213 struct amd_iommu *iommu;
215 list_for_each_entry(iommu, &amd_iommu_list, list)
216 iommu_poll_events(iommu);
221 /****************************************************************************
223 * IOMMU command queuing functions
225 ****************************************************************************/
228 * Writes the command to the IOMMUs command buffer and informs the
229 * hardware about the new command. Must be called with iommu->lock held.
231 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
236 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
237 target = iommu->cmd_buf + tail;
238 memcpy_toio(target, cmd, sizeof(*cmd));
239 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
240 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
243 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
249 * General queuing function for commands. Takes iommu->lock and calls
250 * __iommu_queue_command().
252 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
257 spin_lock_irqsave(&iommu->lock, flags);
258 ret = __iommu_queue_command(iommu, cmd);
260 iommu->need_sync = true;
261 spin_unlock_irqrestore(&iommu->lock, flags);
267 * This function waits until an IOMMU has completed a completion
270 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
276 INC_STATS_COUNTER(compl_wait);
278 while (!ready && (i < EXIT_LOOP_COUNT)) {
280 /* wait for the bit to become one */
281 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
282 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
285 /* set bit back to zero */
286 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
287 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
289 if (unlikely(i == EXIT_LOOP_COUNT))
290 panic("AMD IOMMU: Completion wait loop failed\n");
294 * This function queues a completion wait command into the command
297 static int __iommu_completion_wait(struct amd_iommu *iommu)
299 struct iommu_cmd cmd;
301 memset(&cmd, 0, sizeof(cmd));
302 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
303 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
305 return __iommu_queue_command(iommu, &cmd);
309 * This function is called whenever we need to ensure that the IOMMU has
310 * completed execution of all commands we sent. It sends a
311 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
312 * us about that by writing a value to a physical address we pass with
315 static int iommu_completion_wait(struct amd_iommu *iommu)
320 spin_lock_irqsave(&iommu->lock, flags);
322 if (!iommu->need_sync)
325 ret = __iommu_completion_wait(iommu);
327 iommu->need_sync = false;
332 __iommu_wait_for_completion(iommu);
335 spin_unlock_irqrestore(&iommu->lock, flags);
341 * Command send function for invalidating a device table entry
343 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
345 struct iommu_cmd cmd;
348 BUG_ON(iommu == NULL);
350 memset(&cmd, 0, sizeof(cmd));
351 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
354 ret = iommu_queue_command(iommu, &cmd);
359 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
360 u16 domid, int pde, int s)
362 memset(cmd, 0, sizeof(*cmd));
363 address &= PAGE_MASK;
364 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
365 cmd->data[1] |= domid;
366 cmd->data[2] = lower_32_bits(address);
367 cmd->data[3] = upper_32_bits(address);
368 if (s) /* size bit - we flush more than one 4kb page */
369 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
370 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
371 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
375 * Generic command send function for invalidaing TLB entries
377 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
378 u64 address, u16 domid, int pde, int s)
380 struct iommu_cmd cmd;
383 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
385 ret = iommu_queue_command(iommu, &cmd);
391 * TLB invalidation function which is called from the mapping functions.
392 * It invalidates a single PTE if the range to flush is within a single
393 * page. Otherwise it flushes the whole TLB of the IOMMU.
395 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
396 u64 address, size_t size)
399 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
401 address &= PAGE_MASK;
405 * If we have to flush more than one page, flush all
406 * TLB entries for this domain
408 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
412 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
417 /* Flush the whole IO/TLB for a given protection domain */
418 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
420 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
422 INC_STATS_COUNTER(domain_flush_single);
424 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
427 #ifdef CONFIG_IOMMU_API
429 * This function is used to flush the IO/TLB for a given protection domain
430 * on every IOMMU in the system
432 static void iommu_flush_domain(u16 domid)
435 struct amd_iommu *iommu;
436 struct iommu_cmd cmd;
438 INC_STATS_COUNTER(domain_flush_all);
440 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
443 list_for_each_entry(iommu, &amd_iommu_list, list) {
444 spin_lock_irqsave(&iommu->lock, flags);
445 __iommu_queue_command(iommu, &cmd);
446 __iommu_completion_wait(iommu);
447 __iommu_wait_for_completion(iommu);
448 spin_unlock_irqrestore(&iommu->lock, flags);
453 /****************************************************************************
455 * The functions below are used the create the page table mappings for
456 * unity mapped regions.
458 ****************************************************************************/
461 * Generic mapping functions. It maps a physical address into a DMA
462 * address space. It allocates the page table pages if necessary.
463 * In the future it can be extended to a generic mapping function
464 * supporting all features of AMD IOMMU page tables like level skipping
465 * and full 64 bit address spaces.
467 static int iommu_map_page(struct protection_domain *dom,
468 unsigned long bus_addr,
469 unsigned long phys_addr,
472 u64 __pte, *pte, *page;
474 bus_addr = PAGE_ALIGN(bus_addr);
475 phys_addr = PAGE_ALIGN(phys_addr);
477 /* only support 512GB address spaces for now */
478 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
481 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
483 if (!IOMMU_PTE_PRESENT(*pte)) {
484 page = (u64 *)get_zeroed_page(GFP_KERNEL);
487 *pte = IOMMU_L2_PDE(virt_to_phys(page));
490 pte = IOMMU_PTE_PAGE(*pte);
491 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
493 if (!IOMMU_PTE_PRESENT(*pte)) {
494 page = (u64 *)get_zeroed_page(GFP_KERNEL);
497 *pte = IOMMU_L1_PDE(virt_to_phys(page));
500 pte = IOMMU_PTE_PAGE(*pte);
501 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
503 if (IOMMU_PTE_PRESENT(*pte))
506 __pte = phys_addr | IOMMU_PTE_P;
507 if (prot & IOMMU_PROT_IR)
508 __pte |= IOMMU_PTE_IR;
509 if (prot & IOMMU_PROT_IW)
510 __pte |= IOMMU_PTE_IW;
517 #ifdef CONFIG_IOMMU_API
518 static void iommu_unmap_page(struct protection_domain *dom,
519 unsigned long bus_addr)
523 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
525 if (!IOMMU_PTE_PRESENT(*pte))
528 pte = IOMMU_PTE_PAGE(*pte);
529 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
531 if (!IOMMU_PTE_PRESENT(*pte))
534 pte = IOMMU_PTE_PAGE(*pte);
535 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
542 * This function checks if a specific unity mapping entry is needed for
543 * this specific IOMMU.
545 static int iommu_for_unity_map(struct amd_iommu *iommu,
546 struct unity_map_entry *entry)
550 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
551 bdf = amd_iommu_alias_table[i];
552 if (amd_iommu_rlookup_table[bdf] == iommu)
560 * Init the unity mappings for a specific IOMMU in the system
562 * Basically iterates over all unity mapping entries and applies them to
563 * the default domain DMA of that IOMMU if necessary.
565 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
567 struct unity_map_entry *entry;
570 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
571 if (!iommu_for_unity_map(iommu, entry))
573 ret = dma_ops_unity_map(iommu->default_dom, entry);
582 * This function actually applies the mapping to the page table of the
585 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
586 struct unity_map_entry *e)
591 for (addr = e->address_start; addr < e->address_end;
593 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
597 * if unity mapping is in aperture range mark the page
598 * as allocated in the aperture
600 if (addr < dma_dom->aperture_size)
601 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
608 * Inits the unity mappings required for a specific device
610 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
613 struct unity_map_entry *e;
616 list_for_each_entry(e, &amd_iommu_unity_map, list) {
617 if (!(devid >= e->devid_start && devid <= e->devid_end))
619 ret = dma_ops_unity_map(dma_dom, e);
627 /****************************************************************************
629 * The next functions belong to the address allocator for the dma_ops
630 * interface functions. They work like the allocators in the other IOMMU
631 * drivers. Its basically a bitmap which marks the allocated pages in
632 * the aperture. Maybe it could be enhanced in the future to a more
633 * efficient allocator.
635 ****************************************************************************/
638 * The address allocator core function.
640 * called with domain->lock held
642 static unsigned long dma_ops_alloc_addresses(struct device *dev,
643 struct dma_ops_domain *dom,
645 unsigned long align_mask,
649 unsigned long address;
650 unsigned long boundary_size;
652 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
653 PAGE_SIZE) >> PAGE_SHIFT;
654 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
655 dma_mask >> PAGE_SHIFT);
657 if (dom->next_bit >= limit) {
659 dom->need_flush = true;
662 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
663 0 , boundary_size, align_mask);
665 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
666 0, boundary_size, align_mask);
667 dom->need_flush = true;
670 if (likely(address != -1)) {
671 dom->next_bit = address + pages;
672 address <<= PAGE_SHIFT;
674 address = bad_dma_address;
676 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
682 * The address free function.
684 * called with domain->lock held
686 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
687 unsigned long address,
690 address >>= PAGE_SHIFT;
691 iommu_area_free(dom->bitmap, address, pages);
693 if (address >= dom->next_bit)
694 dom->need_flush = true;
697 /****************************************************************************
699 * The next functions belong to the domain allocation. A domain is
700 * allocated for every IOMMU as the default domain. If device isolation
701 * is enabled, every device get its own domain. The most important thing
702 * about domains is the page table mapping the DMA address space they
705 ****************************************************************************/
707 static u16 domain_id_alloc(void)
712 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
713 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
715 if (id > 0 && id < MAX_DOMAIN_ID)
716 __set_bit(id, amd_iommu_pd_alloc_bitmap);
719 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
724 #ifdef CONFIG_IOMMU_API
725 static void domain_id_free(int id)
729 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
730 if (id > 0 && id < MAX_DOMAIN_ID)
731 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
732 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
737 * Used to reserve address ranges in the aperture (e.g. for exclusion
740 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
741 unsigned long start_page,
744 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
746 if (start_page + pages > last_page)
747 pages = last_page - start_page;
749 iommu_area_reserve(dom->bitmap, start_page, pages);
752 static void free_pagetable(struct protection_domain *domain)
757 p1 = domain->pt_root;
762 for (i = 0; i < 512; ++i) {
763 if (!IOMMU_PTE_PRESENT(p1[i]))
766 p2 = IOMMU_PTE_PAGE(p1[i]);
767 for (j = 0; j < 512; ++j) {
768 if (!IOMMU_PTE_PRESENT(p2[j]))
770 p3 = IOMMU_PTE_PAGE(p2[j]);
771 free_page((unsigned long)p3);
774 free_page((unsigned long)p2);
777 free_page((unsigned long)p1);
779 domain->pt_root = NULL;
783 * Free a domain, only used if something went wrong in the
784 * allocation path and we need to free an already allocated page table
786 static void dma_ops_domain_free(struct dma_ops_domain *dom)
791 free_pagetable(&dom->domain);
793 kfree(dom->pte_pages);
801 * Allocates a new protection domain usable for the dma_ops functions.
802 * It also intializes the page table and the address allocator data
803 * structures required for the dma_ops interface
805 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
808 struct dma_ops_domain *dma_dom;
809 unsigned i, num_pte_pages;
814 * Currently the DMA aperture must be between 32 MB and 1GB in size
816 if ((order < 25) || (order > 30))
819 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
823 spin_lock_init(&dma_dom->domain.lock);
825 dma_dom->domain.id = domain_id_alloc();
826 if (dma_dom->domain.id == 0)
828 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
829 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
830 dma_dom->domain.flags = PD_DMA_OPS_MASK;
831 dma_dom->domain.priv = dma_dom;
832 if (!dma_dom->domain.pt_root)
834 dma_dom->aperture_size = (1ULL << order);
835 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
837 if (!dma_dom->bitmap)
840 * mark the first page as allocated so we never return 0 as
841 * a valid dma-address. So we can use 0 as error value
843 dma_dom->bitmap[0] = 1;
844 dma_dom->next_bit = 0;
846 dma_dom->need_flush = false;
847 dma_dom->target_dev = 0xffff;
849 /* Intialize the exclusion range if necessary */
850 if (iommu->exclusion_start &&
851 iommu->exclusion_start < dma_dom->aperture_size) {
852 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
853 int pages = iommu_num_pages(iommu->exclusion_start,
854 iommu->exclusion_length,
856 dma_ops_reserve_addresses(dma_dom, startpage, pages);
860 * At the last step, build the page tables so we don't need to
861 * allocate page table pages in the dma_ops mapping/unmapping
864 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
865 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
867 if (!dma_dom->pte_pages)
870 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
874 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
876 for (i = 0; i < num_pte_pages; ++i) {
877 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
878 if (!dma_dom->pte_pages[i])
880 address = virt_to_phys(dma_dom->pte_pages[i]);
881 l2_pde[i] = IOMMU_L1_PDE(address);
887 dma_ops_domain_free(dma_dom);
893 * little helper function to check whether a given protection domain is a
896 static bool dma_ops_domain(struct protection_domain *domain)
898 return domain->flags & PD_DMA_OPS_MASK;
902 * Find out the protection domain structure for a given PCI device. This
903 * will give us the pointer to the page table root for example.
905 static struct protection_domain *domain_for_device(u16 devid)
907 struct protection_domain *dom;
910 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
911 dom = amd_iommu_pd_table[devid];
912 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
918 * If a device is not yet associated with a domain, this function does
919 * assigns it visible for the hardware
921 static void attach_device(struct amd_iommu *iommu,
922 struct protection_domain *domain,
926 u64 pte_root = virt_to_phys(domain->pt_root);
928 domain->dev_cnt += 1;
930 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
931 << DEV_ENTRY_MODE_SHIFT;
932 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
934 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
935 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
936 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
937 amd_iommu_dev_table[devid].data[2] = domain->id;
939 amd_iommu_pd_table[devid] = domain;
940 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
942 iommu_queue_inv_dev_entry(iommu, devid);
946 * Removes a device from a protection domain (unlocked)
948 static void __detach_device(struct protection_domain *domain, u16 devid)
952 spin_lock(&domain->lock);
954 /* remove domain from the lookup table */
955 amd_iommu_pd_table[devid] = NULL;
957 /* remove entry from the device table seen by the hardware */
958 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
959 amd_iommu_dev_table[devid].data[1] = 0;
960 amd_iommu_dev_table[devid].data[2] = 0;
962 /* decrease reference counter */
963 domain->dev_cnt -= 1;
966 spin_unlock(&domain->lock);
970 * Removes a device from a protection domain (with devtable_lock held)
972 static void detach_device(struct protection_domain *domain, u16 devid)
976 /* lock device table */
977 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
978 __detach_device(domain, devid);
979 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
982 static int device_change_notifier(struct notifier_block *nb,
983 unsigned long action, void *data)
985 struct device *dev = data;
986 struct pci_dev *pdev = to_pci_dev(dev);
987 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
988 struct protection_domain *domain;
989 struct dma_ops_domain *dma_domain;
990 struct amd_iommu *iommu;
991 int order = amd_iommu_aperture_order;
994 if (devid > amd_iommu_last_bdf)
997 devid = amd_iommu_alias_table[devid];
999 iommu = amd_iommu_rlookup_table[devid];
1003 domain = domain_for_device(devid);
1005 if (domain && !dma_ops_domain(domain))
1006 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1007 "to a non-dma-ops domain\n", dev_name(dev));
1010 case BUS_NOTIFY_BOUND_DRIVER:
1013 dma_domain = find_protection_domain(devid);
1015 dma_domain = iommu->default_dom;
1016 attach_device(iommu, &dma_domain->domain, devid);
1017 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1018 "device %s\n", dma_domain->domain.id, dev_name(dev));
1020 case BUS_NOTIFY_UNBIND_DRIVER:
1023 detach_device(domain, devid);
1025 case BUS_NOTIFY_ADD_DEVICE:
1026 /* allocate a protection domain if a device is added */
1027 dma_domain = find_protection_domain(devid);
1030 dma_domain = dma_ops_domain_alloc(iommu, order);
1033 dma_domain->target_dev = devid;
1035 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1036 list_add_tail(&dma_domain->list, &iommu_pd_list);
1037 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1044 iommu_queue_inv_dev_entry(iommu, devid);
1045 iommu_completion_wait(iommu);
1051 struct notifier_block device_nb = {
1052 .notifier_call = device_change_notifier,
1055 /*****************************************************************************
1057 * The next functions belong to the dma_ops mapping/unmapping code.
1059 *****************************************************************************/
1062 * This function checks if the driver got a valid device from the caller to
1063 * avoid dereferencing invalid pointers.
1065 static bool check_device(struct device *dev)
1067 if (!dev || !dev->dma_mask)
1074 * In this function the list of preallocated protection domains is traversed to
1075 * find the domain for a specific device
1077 static struct dma_ops_domain *find_protection_domain(u16 devid)
1079 struct dma_ops_domain *entry, *ret = NULL;
1080 unsigned long flags;
1082 if (list_empty(&iommu_pd_list))
1085 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1087 list_for_each_entry(entry, &iommu_pd_list, list) {
1088 if (entry->target_dev == devid) {
1094 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1100 * In the dma_ops path we only have the struct device. This function
1101 * finds the corresponding IOMMU, the protection domain and the
1102 * requestor id for a given device.
1103 * If the device is not yet associated with a domain this is also done
1106 static int get_device_resources(struct device *dev,
1107 struct amd_iommu **iommu,
1108 struct protection_domain **domain,
1111 struct dma_ops_domain *dma_dom;
1112 struct pci_dev *pcidev;
1119 if (dev->bus != &pci_bus_type)
1122 pcidev = to_pci_dev(dev);
1123 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1125 /* device not translated by any IOMMU in the system? */
1126 if (_bdf > amd_iommu_last_bdf)
1129 *bdf = amd_iommu_alias_table[_bdf];
1131 *iommu = amd_iommu_rlookup_table[*bdf];
1134 *domain = domain_for_device(*bdf);
1135 if (*domain == NULL) {
1136 dma_dom = find_protection_domain(*bdf);
1138 dma_dom = (*iommu)->default_dom;
1139 *domain = &dma_dom->domain;
1140 attach_device(*iommu, *domain, *bdf);
1141 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1142 "device %s\n", (*domain)->id, dev_name(dev));
1145 if (domain_for_device(_bdf) == NULL)
1146 attach_device(*iommu, *domain, _bdf);
1152 * This is the generic map function. It maps one 4kb page at paddr to
1153 * the given address in the DMA address space for the domain.
1155 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1156 struct dma_ops_domain *dom,
1157 unsigned long address,
1163 WARN_ON(address > dom->aperture_size);
1167 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1168 pte += IOMMU_PTE_L0_INDEX(address);
1170 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1172 if (direction == DMA_TO_DEVICE)
1173 __pte |= IOMMU_PTE_IR;
1174 else if (direction == DMA_FROM_DEVICE)
1175 __pte |= IOMMU_PTE_IW;
1176 else if (direction == DMA_BIDIRECTIONAL)
1177 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1183 return (dma_addr_t)address;
1187 * The generic unmapping function for on page in the DMA address space.
1189 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1190 struct dma_ops_domain *dom,
1191 unsigned long address)
1195 if (address >= dom->aperture_size)
1198 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1200 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1201 pte += IOMMU_PTE_L0_INDEX(address);
1209 * This function contains common code for mapping of a physically
1210 * contiguous memory region into DMA address space. It is used by all
1211 * mapping functions provided with this IOMMU driver.
1212 * Must be called with the domain lock held.
1214 static dma_addr_t __map_single(struct device *dev,
1215 struct amd_iommu *iommu,
1216 struct dma_ops_domain *dma_dom,
1223 dma_addr_t offset = paddr & ~PAGE_MASK;
1224 dma_addr_t address, start;
1226 unsigned long align_mask = 0;
1229 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1233 INC_STATS_COUNTER(cross_page);
1236 align_mask = (1UL << get_order(size)) - 1;
1238 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1240 if (unlikely(address == bad_dma_address))
1244 for (i = 0; i < pages; ++i) {
1245 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1251 ADD_STATS_COUNTER(alloced_io_mem, size);
1253 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1254 iommu_flush_tlb(iommu, dma_dom->domain.id);
1255 dma_dom->need_flush = false;
1256 } else if (unlikely(iommu_has_npcache(iommu)))
1257 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1264 * Does the reverse of the __map_single function. Must be called with
1265 * the domain lock held too
1267 static void __unmap_single(struct amd_iommu *iommu,
1268 struct dma_ops_domain *dma_dom,
1269 dma_addr_t dma_addr,
1273 dma_addr_t i, start;
1276 if ((dma_addr == bad_dma_address) ||
1277 (dma_addr + size > dma_dom->aperture_size))
1280 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1281 dma_addr &= PAGE_MASK;
1284 for (i = 0; i < pages; ++i) {
1285 dma_ops_domain_unmap(iommu, dma_dom, start);
1289 SUB_STATS_COUNTER(alloced_io_mem, size);
1291 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1293 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1294 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1295 dma_dom->need_flush = false;
1300 * The exported map_single function for dma_ops.
1302 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1303 size_t size, int dir)
1305 unsigned long flags;
1306 struct amd_iommu *iommu;
1307 struct protection_domain *domain;
1312 INC_STATS_COUNTER(cnt_map_single);
1314 if (!check_device(dev))
1315 return bad_dma_address;
1317 dma_mask = *dev->dma_mask;
1319 get_device_resources(dev, &iommu, &domain, &devid);
1321 if (iommu == NULL || domain == NULL)
1322 /* device not handled by any AMD IOMMU */
1323 return (dma_addr_t)paddr;
1325 if (!dma_ops_domain(domain))
1326 return bad_dma_address;
1328 spin_lock_irqsave(&domain->lock, flags);
1329 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1331 if (addr == bad_dma_address)
1334 iommu_completion_wait(iommu);
1337 spin_unlock_irqrestore(&domain->lock, flags);
1343 * The exported unmap_single function for dma_ops.
1345 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1346 size_t size, int dir)
1348 unsigned long flags;
1349 struct amd_iommu *iommu;
1350 struct protection_domain *domain;
1353 INC_STATS_COUNTER(cnt_unmap_single);
1355 if (!check_device(dev) ||
1356 !get_device_resources(dev, &iommu, &domain, &devid))
1357 /* device not handled by any AMD IOMMU */
1360 if (!dma_ops_domain(domain))
1363 spin_lock_irqsave(&domain->lock, flags);
1365 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1367 iommu_completion_wait(iommu);
1369 spin_unlock_irqrestore(&domain->lock, flags);
1373 * This is a special map_sg function which is used if we should map a
1374 * device which is not handled by an AMD IOMMU in the system.
1376 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1377 int nelems, int dir)
1379 struct scatterlist *s;
1382 for_each_sg(sglist, s, nelems, i) {
1383 s->dma_address = (dma_addr_t)sg_phys(s);
1384 s->dma_length = s->length;
1391 * The exported map_sg function for dma_ops (handles scatter-gather
1394 static int map_sg(struct device *dev, struct scatterlist *sglist,
1395 int nelems, int dir)
1397 unsigned long flags;
1398 struct amd_iommu *iommu;
1399 struct protection_domain *domain;
1402 struct scatterlist *s;
1404 int mapped_elems = 0;
1407 INC_STATS_COUNTER(cnt_map_sg);
1409 if (!check_device(dev))
1412 dma_mask = *dev->dma_mask;
1414 get_device_resources(dev, &iommu, &domain, &devid);
1416 if (!iommu || !domain)
1417 return map_sg_no_iommu(dev, sglist, nelems, dir);
1419 if (!dma_ops_domain(domain))
1422 spin_lock_irqsave(&domain->lock, flags);
1424 for_each_sg(sglist, s, nelems, i) {
1427 s->dma_address = __map_single(dev, iommu, domain->priv,
1428 paddr, s->length, dir, false,
1431 if (s->dma_address) {
1432 s->dma_length = s->length;
1438 iommu_completion_wait(iommu);
1441 spin_unlock_irqrestore(&domain->lock, flags);
1443 return mapped_elems;
1445 for_each_sg(sglist, s, mapped_elems, i) {
1447 __unmap_single(iommu, domain->priv, s->dma_address,
1448 s->dma_length, dir);
1449 s->dma_address = s->dma_length = 0;
1458 * The exported map_sg function for dma_ops (handles scatter-gather
1461 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1462 int nelems, int dir)
1464 unsigned long flags;
1465 struct amd_iommu *iommu;
1466 struct protection_domain *domain;
1467 struct scatterlist *s;
1471 INC_STATS_COUNTER(cnt_unmap_sg);
1473 if (!check_device(dev) ||
1474 !get_device_resources(dev, &iommu, &domain, &devid))
1477 if (!dma_ops_domain(domain))
1480 spin_lock_irqsave(&domain->lock, flags);
1482 for_each_sg(sglist, s, nelems, i) {
1483 __unmap_single(iommu, domain->priv, s->dma_address,
1484 s->dma_length, dir);
1485 s->dma_address = s->dma_length = 0;
1488 iommu_completion_wait(iommu);
1490 spin_unlock_irqrestore(&domain->lock, flags);
1494 * The exported alloc_coherent function for dma_ops.
1496 static void *alloc_coherent(struct device *dev, size_t size,
1497 dma_addr_t *dma_addr, gfp_t flag)
1499 unsigned long flags;
1501 struct amd_iommu *iommu;
1502 struct protection_domain *domain;
1505 u64 dma_mask = dev->coherent_dma_mask;
1507 INC_STATS_COUNTER(cnt_alloc_coherent);
1509 if (!check_device(dev))
1512 if (!get_device_resources(dev, &iommu, &domain, &devid))
1513 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1516 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1520 paddr = virt_to_phys(virt_addr);
1522 if (!iommu || !domain) {
1523 *dma_addr = (dma_addr_t)paddr;
1527 if (!dma_ops_domain(domain))
1531 dma_mask = *dev->dma_mask;
1533 spin_lock_irqsave(&domain->lock, flags);
1535 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1536 size, DMA_BIDIRECTIONAL, true, dma_mask);
1538 if (*dma_addr == bad_dma_address)
1541 iommu_completion_wait(iommu);
1543 spin_unlock_irqrestore(&domain->lock, flags);
1549 free_pages((unsigned long)virt_addr, get_order(size));
1555 * The exported free_coherent function for dma_ops.
1557 static void free_coherent(struct device *dev, size_t size,
1558 void *virt_addr, dma_addr_t dma_addr)
1560 unsigned long flags;
1561 struct amd_iommu *iommu;
1562 struct protection_domain *domain;
1565 INC_STATS_COUNTER(cnt_free_coherent);
1567 if (!check_device(dev))
1570 get_device_resources(dev, &iommu, &domain, &devid);
1572 if (!iommu || !domain)
1575 if (!dma_ops_domain(domain))
1578 spin_lock_irqsave(&domain->lock, flags);
1580 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1582 iommu_completion_wait(iommu);
1584 spin_unlock_irqrestore(&domain->lock, flags);
1587 free_pages((unsigned long)virt_addr, get_order(size));
1591 * This function is called by the DMA layer to find out if we can handle a
1592 * particular device. It is part of the dma_ops.
1594 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1597 struct pci_dev *pcidev;
1599 /* No device or no PCI device */
1600 if (!dev || dev->bus != &pci_bus_type)
1603 pcidev = to_pci_dev(dev);
1605 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1607 /* Out of our scope? */
1608 if (bdf > amd_iommu_last_bdf)
1615 * The function for pre-allocating protection domains.
1617 * If the driver core informs the DMA layer if a driver grabs a device
1618 * we don't need to preallocate the protection domains anymore.
1619 * For now we have to.
1621 void prealloc_protection_domains(void)
1623 struct pci_dev *dev = NULL;
1624 struct dma_ops_domain *dma_dom;
1625 struct amd_iommu *iommu;
1626 int order = amd_iommu_aperture_order;
1629 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1630 devid = calc_devid(dev->bus->number, dev->devfn);
1631 if (devid > amd_iommu_last_bdf)
1633 devid = amd_iommu_alias_table[devid];
1634 if (domain_for_device(devid))
1636 iommu = amd_iommu_rlookup_table[devid];
1639 dma_dom = dma_ops_domain_alloc(iommu, order);
1642 init_unity_mappings_for_device(dma_dom, devid);
1643 dma_dom->target_dev = devid;
1645 list_add_tail(&dma_dom->list, &iommu_pd_list);
1649 static struct dma_mapping_ops amd_iommu_dma_ops = {
1650 .alloc_coherent = alloc_coherent,
1651 .free_coherent = free_coherent,
1652 .map_single = map_single,
1653 .unmap_single = unmap_single,
1655 .unmap_sg = unmap_sg,
1656 .dma_supported = amd_iommu_dma_supported,
1660 * The function which clues the AMD IOMMU driver into dma_ops.
1662 int __init amd_iommu_init_dma_ops(void)
1664 struct amd_iommu *iommu;
1665 int order = amd_iommu_aperture_order;
1669 * first allocate a default protection domain for every IOMMU we
1670 * found in the system. Devices not assigned to any other
1671 * protection domain will be assigned to the default one.
1673 list_for_each_entry(iommu, &amd_iommu_list, list) {
1674 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1675 if (iommu->default_dom == NULL)
1677 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1678 ret = iommu_init_unity_mappings(iommu);
1684 * If device isolation is enabled, pre-allocate the protection
1685 * domains for each device.
1687 if (amd_iommu_isolate)
1688 prealloc_protection_domains();
1692 bad_dma_address = 0;
1693 #ifdef CONFIG_GART_IOMMU
1694 gart_iommu_aperture_disabled = 1;
1695 gart_iommu_aperture = 0;
1698 /* Make the driver finally visible to the drivers */
1699 dma_ops = &amd_iommu_dma_ops;
1701 #ifdef CONFIG_IOMMU_API
1702 register_iommu(&amd_iommu_ops);
1705 bus_register_notifier(&pci_bus_type, &device_nb);
1707 amd_iommu_stats_init();
1713 list_for_each_entry(iommu, &amd_iommu_list, list) {
1714 if (iommu->default_dom)
1715 dma_ops_domain_free(iommu->default_dom);
1721 /*****************************************************************************
1723 * The following functions belong to the exported interface of AMD IOMMU
1725 * This interface allows access to lower level functions of the IOMMU
1726 * like protection domain handling and assignement of devices to domains
1727 * which is not possible with the dma_ops interface.
1729 *****************************************************************************/
1731 #ifdef CONFIG_IOMMU_API
1733 static void cleanup_domain(struct protection_domain *domain)
1735 unsigned long flags;
1738 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1740 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1741 if (amd_iommu_pd_table[devid] == domain)
1742 __detach_device(domain, devid);
1744 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1747 static int amd_iommu_domain_init(struct iommu_domain *dom)
1749 struct protection_domain *domain;
1751 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1755 spin_lock_init(&domain->lock);
1756 domain->mode = PAGE_MODE_3_LEVEL;
1757 domain->id = domain_id_alloc();
1760 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1761 if (!domain->pt_root)
1774 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1776 struct protection_domain *domain = dom->priv;
1781 if (domain->dev_cnt > 0)
1782 cleanup_domain(domain);
1784 BUG_ON(domain->dev_cnt != 0);
1786 free_pagetable(domain);
1788 domain_id_free(domain->id);
1795 static void amd_iommu_detach_device(struct iommu_domain *dom,
1798 struct protection_domain *domain = dom->priv;
1799 struct amd_iommu *iommu;
1800 struct pci_dev *pdev;
1803 if (dev->bus != &pci_bus_type)
1806 pdev = to_pci_dev(dev);
1808 devid = calc_devid(pdev->bus->number, pdev->devfn);
1811 detach_device(domain, devid);
1813 iommu = amd_iommu_rlookup_table[devid];
1817 iommu_queue_inv_dev_entry(iommu, devid);
1818 iommu_completion_wait(iommu);
1821 static int amd_iommu_attach_device(struct iommu_domain *dom,
1824 struct protection_domain *domain = dom->priv;
1825 struct protection_domain *old_domain;
1826 struct amd_iommu *iommu;
1827 struct pci_dev *pdev;
1830 if (dev->bus != &pci_bus_type)
1833 pdev = to_pci_dev(dev);
1835 devid = calc_devid(pdev->bus->number, pdev->devfn);
1837 if (devid >= amd_iommu_last_bdf ||
1838 devid != amd_iommu_alias_table[devid])
1841 iommu = amd_iommu_rlookup_table[devid];
1845 old_domain = domain_for_device(devid);
1849 attach_device(iommu, domain, devid);
1851 iommu_completion_wait(iommu);
1856 static int amd_iommu_map_range(struct iommu_domain *dom,
1857 unsigned long iova, phys_addr_t paddr,
1858 size_t size, int iommu_prot)
1860 struct protection_domain *domain = dom->priv;
1861 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1865 if (iommu_prot & IOMMU_READ)
1866 prot |= IOMMU_PROT_IR;
1867 if (iommu_prot & IOMMU_WRITE)
1868 prot |= IOMMU_PROT_IW;
1873 for (i = 0; i < npages; ++i) {
1874 ret = iommu_map_page(domain, iova, paddr, prot);
1885 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1886 unsigned long iova, size_t size)
1889 struct protection_domain *domain = dom->priv;
1890 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1894 for (i = 0; i < npages; ++i) {
1895 iommu_unmap_page(domain, iova);
1899 iommu_flush_domain(domain->id);
1902 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1905 struct protection_domain *domain = dom->priv;
1906 unsigned long offset = iova & ~PAGE_MASK;
1910 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1912 if (!IOMMU_PTE_PRESENT(*pte))
1915 pte = IOMMU_PTE_PAGE(*pte);
1916 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1918 if (!IOMMU_PTE_PRESENT(*pte))
1921 pte = IOMMU_PTE_PAGE(*pte);
1922 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1924 if (!IOMMU_PTE_PRESENT(*pte))
1927 paddr = *pte & IOMMU_PAGE_MASK;
1933 static struct iommu_ops amd_iommu_ops = {
1934 .domain_init = amd_iommu_domain_init,
1935 .domain_destroy = amd_iommu_domain_destroy,
1936 .attach_dev = amd_iommu_attach_device,
1937 .detach_dev = amd_iommu_detach_device,
1938 .map = amd_iommu_map_range,
1939 .unmap = amd_iommu_unmap_range,
1940 .iova_to_phys = amd_iommu_iova_to_phys,