2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #ifdef CONFIG_IOMMU_API
26 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 * general struct to manage commands send to an IOMMU
51 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
52 struct unity_map_entry *e);
53 static struct dma_ops_domain *find_protection_domain(u16 devid);
56 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
57 static int iommu_has_npcache(struct amd_iommu *iommu)
59 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
62 /****************************************************************************
64 * Interrupt handling functions
66 ****************************************************************************/
68 static void iommu_print_event(void *__evt)
71 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
72 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
73 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
74 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
75 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
77 printk(KERN_ERR "AMD IOMMU: Event logged [");
80 case EVENT_TYPE_ILL_DEV:
81 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
82 "address=0x%016llx flags=0x%04x]\n",
83 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
86 case EVENT_TYPE_IO_FAULT:
87 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
88 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
89 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90 domid, address, flags);
92 case EVENT_TYPE_DEV_TAB_ERR:
93 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
94 "address=0x%016llx flags=0x%04x]\n",
95 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
98 case EVENT_TYPE_PAGE_TAB_ERR:
99 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
100 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
101 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
102 domid, address, flags);
104 case EVENT_TYPE_ILL_CMD:
105 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
107 case EVENT_TYPE_CMD_HARD_ERR:
108 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
109 "flags=0x%04x]\n", address, flags);
111 case EVENT_TYPE_IOTLB_INV_TO:
112 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
113 "address=0x%016llx]\n",
114 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
117 case EVENT_TYPE_INV_DEV_REQ:
118 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
119 "address=0x%016llx flags=0x%04x]\n",
120 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
124 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
128 static void iommu_poll_events(struct amd_iommu *iommu)
133 spin_lock_irqsave(&iommu->lock, flags);
135 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
136 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
138 while (head != tail) {
139 iommu_print_event(iommu->evt_buf + head);
140 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
143 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
145 spin_unlock_irqrestore(&iommu->lock, flags);
148 irqreturn_t amd_iommu_int_handler(int irq, void *data)
150 struct amd_iommu *iommu;
152 list_for_each_entry(iommu, &amd_iommu_list, list)
153 iommu_poll_events(iommu);
158 /****************************************************************************
160 * IOMMU command queuing functions
162 ****************************************************************************/
165 * Writes the command to the IOMMUs command buffer and informs the
166 * hardware about the new command. Must be called with iommu->lock held.
168 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
173 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
174 target = iommu->cmd_buf + tail;
175 memcpy_toio(target, cmd, sizeof(*cmd));
176 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
177 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
180 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
186 * General queuing function for commands. Takes iommu->lock and calls
187 * __iommu_queue_command().
189 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
194 spin_lock_irqsave(&iommu->lock, flags);
195 ret = __iommu_queue_command(iommu, cmd);
197 iommu->need_sync = 1;
198 spin_unlock_irqrestore(&iommu->lock, flags);
204 * This function waits until an IOMMU has completed a completion
207 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
213 while (!ready && (i < EXIT_LOOP_COUNT)) {
215 /* wait for the bit to become one */
216 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
217 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
220 /* set bit back to zero */
221 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
222 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
224 if (unlikely(i == EXIT_LOOP_COUNT))
225 panic("AMD IOMMU: Completion wait loop failed\n");
229 * This function queues a completion wait command into the command
232 static int __iommu_completion_wait(struct amd_iommu *iommu)
234 struct iommu_cmd cmd;
236 memset(&cmd, 0, sizeof(cmd));
237 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
238 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
240 return __iommu_queue_command(iommu, &cmd);
244 * This function is called whenever we need to ensure that the IOMMU has
245 * completed execution of all commands we sent. It sends a
246 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
247 * us about that by writing a value to a physical address we pass with
250 static int iommu_completion_wait(struct amd_iommu *iommu)
255 spin_lock_irqsave(&iommu->lock, flags);
257 if (!iommu->need_sync)
260 ret = __iommu_completion_wait(iommu);
262 iommu->need_sync = 0;
267 __iommu_wait_for_completion(iommu);
270 spin_unlock_irqrestore(&iommu->lock, flags);
276 * Command send function for invalidating a device table entry
278 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
280 struct iommu_cmd cmd;
283 BUG_ON(iommu == NULL);
285 memset(&cmd, 0, sizeof(cmd));
286 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
289 ret = iommu_queue_command(iommu, &cmd);
294 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
295 u16 domid, int pde, int s)
297 memset(cmd, 0, sizeof(*cmd));
298 address &= PAGE_MASK;
299 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
300 cmd->data[1] |= domid;
301 cmd->data[2] = lower_32_bits(address);
302 cmd->data[3] = upper_32_bits(address);
303 if (s) /* size bit - we flush more than one 4kb page */
304 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
305 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
306 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
310 * Generic command send function for invalidaing TLB entries
312 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
313 u64 address, u16 domid, int pde, int s)
315 struct iommu_cmd cmd;
318 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
320 ret = iommu_queue_command(iommu, &cmd);
326 * TLB invalidation function which is called from the mapping functions.
327 * It invalidates a single PTE if the range to flush is within a single
328 * page. Otherwise it flushes the whole TLB of the IOMMU.
330 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
331 u64 address, size_t size)
334 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
336 address &= PAGE_MASK;
340 * If we have to flush more than one page, flush all
341 * TLB entries for this domain
343 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
347 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
352 /* Flush the whole IO/TLB for a given protection domain */
353 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
355 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
357 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
360 #ifdef CONFIG_IOMMU_API
362 * This function is used to flush the IO/TLB for a given protection domain
363 * on every IOMMU in the system
365 static void iommu_flush_domain(u16 domid)
368 struct amd_iommu *iommu;
369 struct iommu_cmd cmd;
371 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
374 list_for_each_entry(iommu, &amd_iommu_list, list) {
375 spin_lock_irqsave(&iommu->lock, flags);
376 __iommu_queue_command(iommu, &cmd);
377 __iommu_completion_wait(iommu);
378 __iommu_wait_for_completion(iommu);
379 spin_unlock_irqrestore(&iommu->lock, flags);
384 /****************************************************************************
386 * The functions below are used the create the page table mappings for
387 * unity mapped regions.
389 ****************************************************************************/
392 * Generic mapping functions. It maps a physical address into a DMA
393 * address space. It allocates the page table pages if necessary.
394 * In the future it can be extended to a generic mapping function
395 * supporting all features of AMD IOMMU page tables like level skipping
396 * and full 64 bit address spaces.
398 static int iommu_map_page(struct protection_domain *dom,
399 unsigned long bus_addr,
400 unsigned long phys_addr,
403 u64 __pte, *pte, *page;
405 bus_addr = PAGE_ALIGN(bus_addr);
406 phys_addr = PAGE_ALIGN(phys_addr);
408 /* only support 512GB address spaces for now */
409 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
412 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
414 if (!IOMMU_PTE_PRESENT(*pte)) {
415 page = (u64 *)get_zeroed_page(GFP_KERNEL);
418 *pte = IOMMU_L2_PDE(virt_to_phys(page));
421 pte = IOMMU_PTE_PAGE(*pte);
422 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
424 if (!IOMMU_PTE_PRESENT(*pte)) {
425 page = (u64 *)get_zeroed_page(GFP_KERNEL);
428 *pte = IOMMU_L1_PDE(virt_to_phys(page));
431 pte = IOMMU_PTE_PAGE(*pte);
432 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
434 if (IOMMU_PTE_PRESENT(*pte))
437 __pte = phys_addr | IOMMU_PTE_P;
438 if (prot & IOMMU_PROT_IR)
439 __pte |= IOMMU_PTE_IR;
440 if (prot & IOMMU_PROT_IW)
441 __pte |= IOMMU_PTE_IW;
448 #ifdef CONFIG_IOMMU_API
449 static void iommu_unmap_page(struct protection_domain *dom,
450 unsigned long bus_addr)
454 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
456 if (!IOMMU_PTE_PRESENT(*pte))
459 pte = IOMMU_PTE_PAGE(*pte);
460 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
462 if (!IOMMU_PTE_PRESENT(*pte))
465 pte = IOMMU_PTE_PAGE(*pte);
466 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
473 * This function checks if a specific unity mapping entry is needed for
474 * this specific IOMMU.
476 static int iommu_for_unity_map(struct amd_iommu *iommu,
477 struct unity_map_entry *entry)
481 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
482 bdf = amd_iommu_alias_table[i];
483 if (amd_iommu_rlookup_table[bdf] == iommu)
491 * Init the unity mappings for a specific IOMMU in the system
493 * Basically iterates over all unity mapping entries and applies them to
494 * the default domain DMA of that IOMMU if necessary.
496 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
498 struct unity_map_entry *entry;
501 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
502 if (!iommu_for_unity_map(iommu, entry))
504 ret = dma_ops_unity_map(iommu->default_dom, entry);
513 * This function actually applies the mapping to the page table of the
516 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
517 struct unity_map_entry *e)
522 for (addr = e->address_start; addr < e->address_end;
524 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
528 * if unity mapping is in aperture range mark the page
529 * as allocated in the aperture
531 if (addr < dma_dom->aperture_size)
532 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
539 * Inits the unity mappings required for a specific device
541 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
544 struct unity_map_entry *e;
547 list_for_each_entry(e, &amd_iommu_unity_map, list) {
548 if (!(devid >= e->devid_start && devid <= e->devid_end))
550 ret = dma_ops_unity_map(dma_dom, e);
558 /****************************************************************************
560 * The next functions belong to the address allocator for the dma_ops
561 * interface functions. They work like the allocators in the other IOMMU
562 * drivers. Its basically a bitmap which marks the allocated pages in
563 * the aperture. Maybe it could be enhanced in the future to a more
564 * efficient allocator.
566 ****************************************************************************/
569 * The address allocator core function.
571 * called with domain->lock held
573 static unsigned long dma_ops_alloc_addresses(struct device *dev,
574 struct dma_ops_domain *dom,
576 unsigned long align_mask,
580 unsigned long address;
581 unsigned long boundary_size;
583 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
584 PAGE_SIZE) >> PAGE_SHIFT;
585 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
586 dma_mask >> PAGE_SHIFT);
588 if (dom->next_bit >= limit) {
590 dom->need_flush = true;
593 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
594 0 , boundary_size, align_mask);
596 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
597 0, boundary_size, align_mask);
598 dom->need_flush = true;
601 if (likely(address != -1)) {
602 dom->next_bit = address + pages;
603 address <<= PAGE_SHIFT;
605 address = bad_dma_address;
607 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
613 * The address free function.
615 * called with domain->lock held
617 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
618 unsigned long address,
621 address >>= PAGE_SHIFT;
622 iommu_area_free(dom->bitmap, address, pages);
624 if (address >= dom->next_bit)
625 dom->need_flush = true;
628 /****************************************************************************
630 * The next functions belong to the domain allocation. A domain is
631 * allocated for every IOMMU as the default domain. If device isolation
632 * is enabled, every device get its own domain. The most important thing
633 * about domains is the page table mapping the DMA address space they
636 ****************************************************************************/
638 static u16 domain_id_alloc(void)
643 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
644 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
646 if (id > 0 && id < MAX_DOMAIN_ID)
647 __set_bit(id, amd_iommu_pd_alloc_bitmap);
650 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
655 #ifdef CONFIG_IOMMU_API
656 static void domain_id_free(int id)
660 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
661 if (id > 0 && id < MAX_DOMAIN_ID)
662 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
663 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
668 * Used to reserve address ranges in the aperture (e.g. for exclusion
671 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
672 unsigned long start_page,
675 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
677 if (start_page + pages > last_page)
678 pages = last_page - start_page;
680 iommu_area_reserve(dom->bitmap, start_page, pages);
683 static void free_pagetable(struct protection_domain *domain)
688 p1 = domain->pt_root;
693 for (i = 0; i < 512; ++i) {
694 if (!IOMMU_PTE_PRESENT(p1[i]))
697 p2 = IOMMU_PTE_PAGE(p1[i]);
698 for (j = 0; j < 512; ++j) {
699 if (!IOMMU_PTE_PRESENT(p2[j]))
701 p3 = IOMMU_PTE_PAGE(p2[j]);
702 free_page((unsigned long)p3);
705 free_page((unsigned long)p2);
708 free_page((unsigned long)p1);
710 domain->pt_root = NULL;
714 * Free a domain, only used if something went wrong in the
715 * allocation path and we need to free an already allocated page table
717 static void dma_ops_domain_free(struct dma_ops_domain *dom)
722 free_pagetable(&dom->domain);
724 kfree(dom->pte_pages);
732 * Allocates a new protection domain usable for the dma_ops functions.
733 * It also intializes the page table and the address allocator data
734 * structures required for the dma_ops interface
736 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
739 struct dma_ops_domain *dma_dom;
740 unsigned i, num_pte_pages;
745 * Currently the DMA aperture must be between 32 MB and 1GB in size
747 if ((order < 25) || (order > 30))
750 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
754 spin_lock_init(&dma_dom->domain.lock);
756 dma_dom->domain.id = domain_id_alloc();
757 if (dma_dom->domain.id == 0)
759 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
760 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
761 dma_dom->domain.flags = PD_DMA_OPS_MASK;
762 dma_dom->domain.priv = dma_dom;
763 if (!dma_dom->domain.pt_root)
765 dma_dom->aperture_size = (1ULL << order);
766 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
768 if (!dma_dom->bitmap)
771 * mark the first page as allocated so we never return 0 as
772 * a valid dma-address. So we can use 0 as error value
774 dma_dom->bitmap[0] = 1;
775 dma_dom->next_bit = 0;
777 dma_dom->need_flush = false;
778 dma_dom->target_dev = 0xffff;
780 /* Intialize the exclusion range if necessary */
781 if (iommu->exclusion_start &&
782 iommu->exclusion_start < dma_dom->aperture_size) {
783 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
784 int pages = iommu_num_pages(iommu->exclusion_start,
785 iommu->exclusion_length,
787 dma_ops_reserve_addresses(dma_dom, startpage, pages);
791 * At the last step, build the page tables so we don't need to
792 * allocate page table pages in the dma_ops mapping/unmapping
795 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
796 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
798 if (!dma_dom->pte_pages)
801 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
805 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
807 for (i = 0; i < num_pte_pages; ++i) {
808 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
809 if (!dma_dom->pte_pages[i])
811 address = virt_to_phys(dma_dom->pte_pages[i]);
812 l2_pde[i] = IOMMU_L1_PDE(address);
818 dma_ops_domain_free(dma_dom);
824 * little helper function to check whether a given protection domain is a
827 static bool dma_ops_domain(struct protection_domain *domain)
829 return domain->flags & PD_DMA_OPS_MASK;
833 * Find out the protection domain structure for a given PCI device. This
834 * will give us the pointer to the page table root for example.
836 static struct protection_domain *domain_for_device(u16 devid)
838 struct protection_domain *dom;
841 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
842 dom = amd_iommu_pd_table[devid];
843 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
849 * If a device is not yet associated with a domain, this function does
850 * assigns it visible for the hardware
852 static void attach_device(struct amd_iommu *iommu,
853 struct protection_domain *domain,
857 u64 pte_root = virt_to_phys(domain->pt_root);
859 domain->dev_cnt += 1;
861 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
862 << DEV_ENTRY_MODE_SHIFT;
863 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
865 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
866 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
867 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
868 amd_iommu_dev_table[devid].data[2] = domain->id;
870 amd_iommu_pd_table[devid] = domain;
871 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
873 iommu_queue_inv_dev_entry(iommu, devid);
877 * Removes a device from a protection domain (unlocked)
879 static void __detach_device(struct protection_domain *domain, u16 devid)
883 spin_lock(&domain->lock);
885 /* remove domain from the lookup table */
886 amd_iommu_pd_table[devid] = NULL;
888 /* remove entry from the device table seen by the hardware */
889 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
890 amd_iommu_dev_table[devid].data[1] = 0;
891 amd_iommu_dev_table[devid].data[2] = 0;
893 /* decrease reference counter */
894 domain->dev_cnt -= 1;
897 spin_unlock(&domain->lock);
901 * Removes a device from a protection domain (with devtable_lock held)
903 static void detach_device(struct protection_domain *domain, u16 devid)
907 /* lock device table */
908 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
909 __detach_device(domain, devid);
910 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
913 static int device_change_notifier(struct notifier_block *nb,
914 unsigned long action, void *data)
916 struct device *dev = data;
917 struct pci_dev *pdev = to_pci_dev(dev);
918 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
919 struct protection_domain *domain;
920 struct dma_ops_domain *dma_domain;
921 struct amd_iommu *iommu;
923 if (devid > amd_iommu_last_bdf)
926 devid = amd_iommu_alias_table[devid];
928 iommu = amd_iommu_rlookup_table[devid];
932 domain = domain_for_device(devid);
934 if (domain && !dma_ops_domain(domain))
935 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
936 "to a non-dma-ops domain\n", dev_name(dev));
939 case BUS_NOTIFY_BOUND_DRIVER:
942 dma_domain = find_protection_domain(devid);
944 dma_domain = iommu->default_dom;
945 attach_device(iommu, &dma_domain->domain, devid);
946 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
947 "device %s\n", dma_domain->domain.id, dev_name(dev));
949 case BUS_NOTIFY_UNBIND_DRIVER:
952 detach_device(domain, devid);
958 iommu_queue_inv_dev_entry(iommu, devid);
959 iommu_completion_wait(iommu);
965 struct notifier_block device_nb = {
966 .notifier_call = device_change_notifier,
969 /*****************************************************************************
971 * The next functions belong to the dma_ops mapping/unmapping code.
973 *****************************************************************************/
976 * This function checks if the driver got a valid device from the caller to
977 * avoid dereferencing invalid pointers.
979 static bool check_device(struct device *dev)
981 if (!dev || !dev->dma_mask)
988 * In this function the list of preallocated protection domains is traversed to
989 * find the domain for a specific device
991 static struct dma_ops_domain *find_protection_domain(u16 devid)
993 struct dma_ops_domain *entry, *ret = NULL;
996 if (list_empty(&iommu_pd_list))
999 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1001 list_for_each_entry(entry, &iommu_pd_list, list) {
1002 if (entry->target_dev == devid) {
1008 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1014 * In the dma_ops path we only have the struct device. This function
1015 * finds the corresponding IOMMU, the protection domain and the
1016 * requestor id for a given device.
1017 * If the device is not yet associated with a domain this is also done
1020 static int get_device_resources(struct device *dev,
1021 struct amd_iommu **iommu,
1022 struct protection_domain **domain,
1025 struct dma_ops_domain *dma_dom;
1026 struct pci_dev *pcidev;
1033 if (dev->bus != &pci_bus_type)
1036 pcidev = to_pci_dev(dev);
1037 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1039 /* device not translated by any IOMMU in the system? */
1040 if (_bdf > amd_iommu_last_bdf)
1043 *bdf = amd_iommu_alias_table[_bdf];
1045 *iommu = amd_iommu_rlookup_table[*bdf];
1048 *domain = domain_for_device(*bdf);
1049 if (*domain == NULL) {
1050 dma_dom = find_protection_domain(*bdf);
1052 dma_dom = (*iommu)->default_dom;
1053 *domain = &dma_dom->domain;
1054 attach_device(*iommu, *domain, *bdf);
1055 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1056 "device ", (*domain)->id);
1057 print_devid(_bdf, 1);
1060 if (domain_for_device(_bdf) == NULL)
1061 attach_device(*iommu, *domain, _bdf);
1067 * This is the generic map function. It maps one 4kb page at paddr to
1068 * the given address in the DMA address space for the domain.
1070 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1071 struct dma_ops_domain *dom,
1072 unsigned long address,
1078 WARN_ON(address > dom->aperture_size);
1082 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1083 pte += IOMMU_PTE_L0_INDEX(address);
1085 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1087 if (direction == DMA_TO_DEVICE)
1088 __pte |= IOMMU_PTE_IR;
1089 else if (direction == DMA_FROM_DEVICE)
1090 __pte |= IOMMU_PTE_IW;
1091 else if (direction == DMA_BIDIRECTIONAL)
1092 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1098 return (dma_addr_t)address;
1102 * The generic unmapping function for on page in the DMA address space.
1104 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1105 struct dma_ops_domain *dom,
1106 unsigned long address)
1110 if (address >= dom->aperture_size)
1113 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1115 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1116 pte += IOMMU_PTE_L0_INDEX(address);
1124 * This function contains common code for mapping of a physically
1125 * contiguous memory region into DMA address space. It is used by all
1126 * mapping functions provided with this IOMMU driver.
1127 * Must be called with the domain lock held.
1129 static dma_addr_t __map_single(struct device *dev,
1130 struct amd_iommu *iommu,
1131 struct dma_ops_domain *dma_dom,
1138 dma_addr_t offset = paddr & ~PAGE_MASK;
1139 dma_addr_t address, start;
1141 unsigned long align_mask = 0;
1144 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1148 align_mask = (1UL << get_order(size)) - 1;
1150 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1152 if (unlikely(address == bad_dma_address))
1156 for (i = 0; i < pages; ++i) {
1157 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1163 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1164 iommu_flush_tlb(iommu, dma_dom->domain.id);
1165 dma_dom->need_flush = false;
1166 } else if (unlikely(iommu_has_npcache(iommu)))
1167 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1174 * Does the reverse of the __map_single function. Must be called with
1175 * the domain lock held too
1177 static void __unmap_single(struct amd_iommu *iommu,
1178 struct dma_ops_domain *dma_dom,
1179 dma_addr_t dma_addr,
1183 dma_addr_t i, start;
1186 if ((dma_addr == bad_dma_address) ||
1187 (dma_addr + size > dma_dom->aperture_size))
1190 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1191 dma_addr &= PAGE_MASK;
1194 for (i = 0; i < pages; ++i) {
1195 dma_ops_domain_unmap(iommu, dma_dom, start);
1199 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1201 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1202 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1203 dma_dom->need_flush = false;
1208 * The exported map_single function for dma_ops.
1210 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1211 size_t size, int dir)
1213 unsigned long flags;
1214 struct amd_iommu *iommu;
1215 struct protection_domain *domain;
1220 if (!check_device(dev))
1221 return bad_dma_address;
1223 dma_mask = *dev->dma_mask;
1225 get_device_resources(dev, &iommu, &domain, &devid);
1227 if (iommu == NULL || domain == NULL)
1228 /* device not handled by any AMD IOMMU */
1229 return (dma_addr_t)paddr;
1231 if (!dma_ops_domain(domain))
1232 return bad_dma_address;
1234 spin_lock_irqsave(&domain->lock, flags);
1235 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1237 if (addr == bad_dma_address)
1240 iommu_completion_wait(iommu);
1243 spin_unlock_irqrestore(&domain->lock, flags);
1249 * The exported unmap_single function for dma_ops.
1251 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1252 size_t size, int dir)
1254 unsigned long flags;
1255 struct amd_iommu *iommu;
1256 struct protection_domain *domain;
1259 if (!check_device(dev) ||
1260 !get_device_resources(dev, &iommu, &domain, &devid))
1261 /* device not handled by any AMD IOMMU */
1264 if (!dma_ops_domain(domain))
1267 spin_lock_irqsave(&domain->lock, flags);
1269 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1271 iommu_completion_wait(iommu);
1273 spin_unlock_irqrestore(&domain->lock, flags);
1277 * This is a special map_sg function which is used if we should map a
1278 * device which is not handled by an AMD IOMMU in the system.
1280 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1281 int nelems, int dir)
1283 struct scatterlist *s;
1286 for_each_sg(sglist, s, nelems, i) {
1287 s->dma_address = (dma_addr_t)sg_phys(s);
1288 s->dma_length = s->length;
1295 * The exported map_sg function for dma_ops (handles scatter-gather
1298 static int map_sg(struct device *dev, struct scatterlist *sglist,
1299 int nelems, int dir)
1301 unsigned long flags;
1302 struct amd_iommu *iommu;
1303 struct protection_domain *domain;
1306 struct scatterlist *s;
1308 int mapped_elems = 0;
1311 if (!check_device(dev))
1314 dma_mask = *dev->dma_mask;
1316 get_device_resources(dev, &iommu, &domain, &devid);
1318 if (!iommu || !domain)
1319 return map_sg_no_iommu(dev, sglist, nelems, dir);
1321 if (!dma_ops_domain(domain))
1324 spin_lock_irqsave(&domain->lock, flags);
1326 for_each_sg(sglist, s, nelems, i) {
1329 s->dma_address = __map_single(dev, iommu, domain->priv,
1330 paddr, s->length, dir, false,
1333 if (s->dma_address) {
1334 s->dma_length = s->length;
1340 iommu_completion_wait(iommu);
1343 spin_unlock_irqrestore(&domain->lock, flags);
1345 return mapped_elems;
1347 for_each_sg(sglist, s, mapped_elems, i) {
1349 __unmap_single(iommu, domain->priv, s->dma_address,
1350 s->dma_length, dir);
1351 s->dma_address = s->dma_length = 0;
1360 * The exported map_sg function for dma_ops (handles scatter-gather
1363 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1364 int nelems, int dir)
1366 unsigned long flags;
1367 struct amd_iommu *iommu;
1368 struct protection_domain *domain;
1369 struct scatterlist *s;
1373 if (!check_device(dev) ||
1374 !get_device_resources(dev, &iommu, &domain, &devid))
1377 if (!dma_ops_domain(domain))
1380 spin_lock_irqsave(&domain->lock, flags);
1382 for_each_sg(sglist, s, nelems, i) {
1383 __unmap_single(iommu, domain->priv, s->dma_address,
1384 s->dma_length, dir);
1385 s->dma_address = s->dma_length = 0;
1388 iommu_completion_wait(iommu);
1390 spin_unlock_irqrestore(&domain->lock, flags);
1394 * The exported alloc_coherent function for dma_ops.
1396 static void *alloc_coherent(struct device *dev, size_t size,
1397 dma_addr_t *dma_addr, gfp_t flag)
1399 unsigned long flags;
1401 struct amd_iommu *iommu;
1402 struct protection_domain *domain;
1405 u64 dma_mask = dev->coherent_dma_mask;
1407 if (!check_device(dev))
1410 if (!get_device_resources(dev, &iommu, &domain, &devid))
1411 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1414 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1418 paddr = virt_to_phys(virt_addr);
1420 if (!iommu || !domain) {
1421 *dma_addr = (dma_addr_t)paddr;
1425 if (!dma_ops_domain(domain))
1429 dma_mask = *dev->dma_mask;
1431 spin_lock_irqsave(&domain->lock, flags);
1433 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1434 size, DMA_BIDIRECTIONAL, true, dma_mask);
1436 if (*dma_addr == bad_dma_address)
1439 iommu_completion_wait(iommu);
1441 spin_unlock_irqrestore(&domain->lock, flags);
1447 free_pages((unsigned long)virt_addr, get_order(size));
1453 * The exported free_coherent function for dma_ops.
1455 static void free_coherent(struct device *dev, size_t size,
1456 void *virt_addr, dma_addr_t dma_addr)
1458 unsigned long flags;
1459 struct amd_iommu *iommu;
1460 struct protection_domain *domain;
1463 if (!check_device(dev))
1466 get_device_resources(dev, &iommu, &domain, &devid);
1468 if (!iommu || !domain)
1471 if (!dma_ops_domain(domain))
1474 spin_lock_irqsave(&domain->lock, flags);
1476 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1478 iommu_completion_wait(iommu);
1480 spin_unlock_irqrestore(&domain->lock, flags);
1483 free_pages((unsigned long)virt_addr, get_order(size));
1487 * This function is called by the DMA layer to find out if we can handle a
1488 * particular device. It is part of the dma_ops.
1490 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1493 struct pci_dev *pcidev;
1495 /* No device or no PCI device */
1496 if (!dev || dev->bus != &pci_bus_type)
1499 pcidev = to_pci_dev(dev);
1501 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1503 /* Out of our scope? */
1504 if (bdf > amd_iommu_last_bdf)
1511 * The function for pre-allocating protection domains.
1513 * If the driver core informs the DMA layer if a driver grabs a device
1514 * we don't need to preallocate the protection domains anymore.
1515 * For now we have to.
1517 void prealloc_protection_domains(void)
1519 struct pci_dev *dev = NULL;
1520 struct dma_ops_domain *dma_dom;
1521 struct amd_iommu *iommu;
1522 int order = amd_iommu_aperture_order;
1525 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1526 devid = (dev->bus->number << 8) | dev->devfn;
1527 if (devid > amd_iommu_last_bdf)
1529 devid = amd_iommu_alias_table[devid];
1530 if (domain_for_device(devid))
1532 iommu = amd_iommu_rlookup_table[devid];
1535 dma_dom = dma_ops_domain_alloc(iommu, order);
1538 init_unity_mappings_for_device(dma_dom, devid);
1539 dma_dom->target_dev = devid;
1541 list_add_tail(&dma_dom->list, &iommu_pd_list);
1545 static struct dma_mapping_ops amd_iommu_dma_ops = {
1546 .alloc_coherent = alloc_coherent,
1547 .free_coherent = free_coherent,
1548 .map_single = map_single,
1549 .unmap_single = unmap_single,
1551 .unmap_sg = unmap_sg,
1552 .dma_supported = amd_iommu_dma_supported,
1556 * The function which clues the AMD IOMMU driver into dma_ops.
1558 int __init amd_iommu_init_dma_ops(void)
1560 struct amd_iommu *iommu;
1561 int order = amd_iommu_aperture_order;
1565 * first allocate a default protection domain for every IOMMU we
1566 * found in the system. Devices not assigned to any other
1567 * protection domain will be assigned to the default one.
1569 list_for_each_entry(iommu, &amd_iommu_list, list) {
1570 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1571 if (iommu->default_dom == NULL)
1573 ret = iommu_init_unity_mappings(iommu);
1579 * If device isolation is enabled, pre-allocate the protection
1580 * domains for each device.
1582 if (amd_iommu_isolate)
1583 prealloc_protection_domains();
1587 bad_dma_address = 0;
1588 #ifdef CONFIG_GART_IOMMU
1589 gart_iommu_aperture_disabled = 1;
1590 gart_iommu_aperture = 0;
1593 /* Make the driver finally visible to the drivers */
1594 dma_ops = &amd_iommu_dma_ops;
1596 bus_register_notifier(&pci_bus_type, &device_nb);
1602 list_for_each_entry(iommu, &amd_iommu_list, list) {
1603 if (iommu->default_dom)
1604 dma_ops_domain_free(iommu->default_dom);
1610 /*****************************************************************************
1612 * The following functions belong to the exported interface of AMD IOMMU
1614 * This interface allows access to lower level functions of the IOMMU
1615 * like protection domain handling and assignement of devices to domains
1616 * which is not possible with the dma_ops interface.
1618 *****************************************************************************/
1620 #ifdef CONFIG_IOMMU_API
1622 static void cleanup_domain(struct protection_domain *domain)
1624 unsigned long flags;
1627 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1629 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1630 if (amd_iommu_pd_table[devid] == domain)
1631 __detach_device(domain, devid);
1633 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1636 static int amd_iommu_domain_init(struct iommu_domain *dom)
1638 struct protection_domain *domain;
1640 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1644 spin_lock_init(&domain->lock);
1645 domain->mode = PAGE_MODE_3_LEVEL;
1646 domain->id = domain_id_alloc();
1649 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1650 if (!domain->pt_root)
1663 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1665 struct protection_domain *domain = dom->priv;
1670 if (domain->dev_cnt > 0)
1671 cleanup_domain(domain);
1673 BUG_ON(domain->dev_cnt != 0);
1675 free_pagetable(domain);
1677 domain_id_free(domain->id);
1684 static void amd_iommu_detach_device(struct iommu_domain *dom,
1687 struct protection_domain *domain = dom->priv;
1688 struct amd_iommu *iommu;
1689 struct pci_dev *pdev;
1692 if (dev->bus != &pci_bus_type)
1695 pdev = to_pci_dev(dev);
1697 devid = calc_devid(pdev->bus->number, pdev->devfn);
1700 detach_device(domain, devid);
1702 iommu = amd_iommu_rlookup_table[devid];
1706 iommu_queue_inv_dev_entry(iommu, devid);
1707 iommu_completion_wait(iommu);
1710 static int amd_iommu_attach_device(struct iommu_domain *dom,
1713 struct protection_domain *domain = dom->priv;
1714 struct protection_domain *old_domain;
1715 struct amd_iommu *iommu;
1716 struct pci_dev *pdev;
1719 if (dev->bus != &pci_bus_type)
1722 pdev = to_pci_dev(dev);
1724 devid = calc_devid(pdev->bus->number, pdev->devfn);
1726 if (devid >= amd_iommu_last_bdf ||
1727 devid != amd_iommu_alias_table[devid])
1730 iommu = amd_iommu_rlookup_table[devid];
1734 old_domain = domain_for_device(devid);
1738 attach_device(iommu, domain, devid);
1740 iommu_completion_wait(iommu);
1745 static int amd_iommu_map_range(struct iommu_domain *dom,
1746 unsigned long iova, phys_addr_t paddr,
1747 size_t size, int iommu_prot)
1749 struct protection_domain *domain = dom->priv;
1750 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1754 if (iommu_prot & IOMMU_READ)
1755 prot |= IOMMU_PROT_IR;
1756 if (iommu_prot & IOMMU_WRITE)
1757 prot |= IOMMU_PROT_IW;
1762 for (i = 0; i < npages; ++i) {
1763 ret = iommu_map_page(domain, iova, paddr, prot);
1774 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1775 unsigned long iova, size_t size)
1778 struct protection_domain *domain = dom->priv;
1779 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1783 for (i = 0; i < npages; ++i) {
1784 iommu_unmap_page(domain, iova);
1788 iommu_flush_domain(domain->id);
1791 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1794 struct protection_domain *domain = dom->priv;
1795 unsigned long offset = iova & ~PAGE_MASK;
1799 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1801 if (!IOMMU_PTE_PRESENT(*pte))
1804 pte = IOMMU_PTE_PAGE(*pte);
1805 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1807 if (!IOMMU_PTE_PRESENT(*pte))
1810 pte = IOMMU_PTE_PAGE(*pte);
1811 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1813 if (!IOMMU_PTE_PRESENT(*pte))
1816 paddr = *pte & IOMMU_PAGE_MASK;