2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
31 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
33 #define EXIT_LOOP_COUNT 10000000
35 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 /* A list of preallocated protection domains */
38 static LIST_HEAD(iommu_pd_list);
39 static DEFINE_SPINLOCK(iommu_pd_list_lock);
42 * general struct to manage commands send to an IOMMU
48 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
49 struct unity_map_entry *e);
51 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
52 static int iommu_has_npcache(struct amd_iommu *iommu)
54 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
57 /****************************************************************************
59 * Interrupt handling functions
61 ****************************************************************************/
63 static void iommu_print_event(void *__evt)
66 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
67 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
68 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
69 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
70 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
72 printk(KERN_ERR "AMD IOMMU: Event logged [");
75 case EVENT_TYPE_ILL_DEV:
76 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
77 "address=0x%016llx flags=0x%04x]\n",
78 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
81 case EVENT_TYPE_IO_FAULT:
82 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
83 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
84 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
85 domid, address, flags);
87 case EVENT_TYPE_DEV_TAB_ERR:
88 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
89 "address=0x%016llx flags=0x%04x]\n",
90 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
93 case EVENT_TYPE_PAGE_TAB_ERR:
94 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
95 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
96 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
97 domid, address, flags);
99 case EVENT_TYPE_ILL_CMD:
100 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
102 case EVENT_TYPE_CMD_HARD_ERR:
103 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
104 "flags=0x%04x]\n", address, flags);
106 case EVENT_TYPE_IOTLB_INV_TO:
107 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
108 "address=0x%016llx]\n",
109 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
112 case EVENT_TYPE_INV_DEV_REQ:
113 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
114 "address=0x%016llx flags=0x%04x]\n",
115 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
119 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
123 static void iommu_poll_events(struct amd_iommu *iommu)
128 spin_lock_irqsave(&iommu->lock, flags);
130 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
131 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
133 while (head != tail) {
134 iommu_print_event(iommu->evt_buf + head);
135 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
138 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
140 spin_unlock_irqrestore(&iommu->lock, flags);
143 irqreturn_t amd_iommu_int_handler(int irq, void *data)
145 struct amd_iommu *iommu;
147 list_for_each_entry(iommu, &amd_iommu_list, list)
148 iommu_poll_events(iommu);
153 /****************************************************************************
155 * IOMMU command queuing functions
157 ****************************************************************************/
160 * Writes the command to the IOMMUs command buffer and informs the
161 * hardware about the new command. Must be called with iommu->lock held.
163 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
168 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
169 target = iommu->cmd_buf + tail;
170 memcpy_toio(target, cmd, sizeof(*cmd));
171 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
172 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
175 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
181 * General queuing function for commands. Takes iommu->lock and calls
182 * __iommu_queue_command().
184 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
189 spin_lock_irqsave(&iommu->lock, flags);
190 ret = __iommu_queue_command(iommu, cmd);
192 iommu->need_sync = 1;
193 spin_unlock_irqrestore(&iommu->lock, flags);
199 * This function waits until an IOMMU has completed a completion
202 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
208 while (!ready && (i < EXIT_LOOP_COUNT)) {
210 /* wait for the bit to become one */
211 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
212 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
215 /* set bit back to zero */
216 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
217 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
219 if (unlikely(i == EXIT_LOOP_COUNT))
220 panic("AMD IOMMU: Completion wait loop failed\n");
224 * This function queues a completion wait command into the command
227 static int __iommu_completion_wait(struct amd_iommu *iommu)
229 struct iommu_cmd cmd;
231 memset(&cmd, 0, sizeof(cmd));
232 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
233 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
235 return __iommu_queue_command(iommu, &cmd);
239 * This function is called whenever we need to ensure that the IOMMU has
240 * completed execution of all commands we sent. It sends a
241 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
242 * us about that by writing a value to a physical address we pass with
245 static int iommu_completion_wait(struct amd_iommu *iommu)
250 spin_lock_irqsave(&iommu->lock, flags);
252 if (!iommu->need_sync)
255 ret = __iommu_completion_wait(iommu);
257 iommu->need_sync = 0;
262 __iommu_wait_for_completion(iommu);
265 spin_unlock_irqrestore(&iommu->lock, flags);
271 * Command send function for invalidating a device table entry
273 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
275 struct iommu_cmd cmd;
278 BUG_ON(iommu == NULL);
280 memset(&cmd, 0, sizeof(cmd));
281 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
284 ret = iommu_queue_command(iommu, &cmd);
289 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
290 u16 domid, int pde, int s)
292 memset(cmd, 0, sizeof(*cmd));
293 address &= PAGE_MASK;
294 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
295 cmd->data[1] |= domid;
296 cmd->data[2] = lower_32_bits(address);
297 cmd->data[3] = upper_32_bits(address);
298 if (s) /* size bit - we flush more than one 4kb page */
299 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
300 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
301 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
305 * Generic command send function for invalidaing TLB entries
307 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
308 u64 address, u16 domid, int pde, int s)
310 struct iommu_cmd cmd;
313 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
315 ret = iommu_queue_command(iommu, &cmd);
321 * TLB invalidation function which is called from the mapping functions.
322 * It invalidates a single PTE if the range to flush is within a single
323 * page. Otherwise it flushes the whole TLB of the IOMMU.
325 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
326 u64 address, size_t size)
329 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
331 address &= PAGE_MASK;
335 * If we have to flush more than one page, flush all
336 * TLB entries for this domain
338 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
342 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
347 /* Flush the whole IO/TLB for a given protection domain */
348 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
350 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
352 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
355 /****************************************************************************
357 * The functions below are used the create the page table mappings for
358 * unity mapped regions.
360 ****************************************************************************/
363 * Generic mapping functions. It maps a physical address into a DMA
364 * address space. It allocates the page table pages if necessary.
365 * In the future it can be extended to a generic mapping function
366 * supporting all features of AMD IOMMU page tables like level skipping
367 * and full 64 bit address spaces.
369 static int iommu_map_page(struct protection_domain *dom,
370 unsigned long bus_addr,
371 unsigned long phys_addr,
374 u64 __pte, *pte, *page;
376 bus_addr = PAGE_ALIGN(bus_addr);
377 phys_addr = PAGE_ALIGN(phys_addr);
379 /* only support 512GB address spaces for now */
380 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
383 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
385 if (!IOMMU_PTE_PRESENT(*pte)) {
386 page = (u64 *)get_zeroed_page(GFP_KERNEL);
389 *pte = IOMMU_L2_PDE(virt_to_phys(page));
392 pte = IOMMU_PTE_PAGE(*pte);
393 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
395 if (!IOMMU_PTE_PRESENT(*pte)) {
396 page = (u64 *)get_zeroed_page(GFP_KERNEL);
399 *pte = IOMMU_L1_PDE(virt_to_phys(page));
402 pte = IOMMU_PTE_PAGE(*pte);
403 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
405 if (IOMMU_PTE_PRESENT(*pte))
408 __pte = phys_addr | IOMMU_PTE_P;
409 if (prot & IOMMU_PROT_IR)
410 __pte |= IOMMU_PTE_IR;
411 if (prot & IOMMU_PROT_IW)
412 __pte |= IOMMU_PTE_IW;
420 * This function checks if a specific unity mapping entry is needed for
421 * this specific IOMMU.
423 static int iommu_for_unity_map(struct amd_iommu *iommu,
424 struct unity_map_entry *entry)
428 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
429 bdf = amd_iommu_alias_table[i];
430 if (amd_iommu_rlookup_table[bdf] == iommu)
438 * Init the unity mappings for a specific IOMMU in the system
440 * Basically iterates over all unity mapping entries and applies them to
441 * the default domain DMA of that IOMMU if necessary.
443 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
445 struct unity_map_entry *entry;
448 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
449 if (!iommu_for_unity_map(iommu, entry))
451 ret = dma_ops_unity_map(iommu->default_dom, entry);
460 * This function actually applies the mapping to the page table of the
463 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
464 struct unity_map_entry *e)
469 for (addr = e->address_start; addr < e->address_end;
471 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
475 * if unity mapping is in aperture range mark the page
476 * as allocated in the aperture
478 if (addr < dma_dom->aperture_size)
479 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
486 * Inits the unity mappings required for a specific device
488 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
491 struct unity_map_entry *e;
494 list_for_each_entry(e, &amd_iommu_unity_map, list) {
495 if (!(devid >= e->devid_start && devid <= e->devid_end))
497 ret = dma_ops_unity_map(dma_dom, e);
505 /****************************************************************************
507 * The next functions belong to the address allocator for the dma_ops
508 * interface functions. They work like the allocators in the other IOMMU
509 * drivers. Its basically a bitmap which marks the allocated pages in
510 * the aperture. Maybe it could be enhanced in the future to a more
511 * efficient allocator.
513 ****************************************************************************/
516 * The address allocator core function.
518 * called with domain->lock held
520 static unsigned long dma_ops_alloc_addresses(struct device *dev,
521 struct dma_ops_domain *dom,
523 unsigned long align_mask,
527 unsigned long address;
528 unsigned long boundary_size;
530 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
531 PAGE_SIZE) >> PAGE_SHIFT;
532 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
533 dma_mask >> PAGE_SHIFT);
535 if (dom->next_bit >= limit) {
537 dom->need_flush = true;
540 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
541 0 , boundary_size, align_mask);
543 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
544 0, boundary_size, align_mask);
545 dom->need_flush = true;
548 if (likely(address != -1)) {
549 dom->next_bit = address + pages;
550 address <<= PAGE_SHIFT;
552 address = bad_dma_address;
554 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
560 * The address free function.
562 * called with domain->lock held
564 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
565 unsigned long address,
568 address >>= PAGE_SHIFT;
569 iommu_area_free(dom->bitmap, address, pages);
571 if (address >= dom->next_bit)
572 dom->need_flush = true;
575 /****************************************************************************
577 * The next functions belong to the domain allocation. A domain is
578 * allocated for every IOMMU as the default domain. If device isolation
579 * is enabled, every device get its own domain. The most important thing
580 * about domains is the page table mapping the DMA address space they
583 ****************************************************************************/
585 static u16 domain_id_alloc(void)
590 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
591 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
593 if (id > 0 && id < MAX_DOMAIN_ID)
594 __set_bit(id, amd_iommu_pd_alloc_bitmap);
597 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
602 #ifdef CONFIG_IOMMU_API
603 static void domain_id_free(int id)
607 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
608 if (id > 0 && id < MAX_DOMAIN_ID)
609 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
610 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
615 * Used to reserve address ranges in the aperture (e.g. for exclusion
618 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
619 unsigned long start_page,
622 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
624 if (start_page + pages > last_page)
625 pages = last_page - start_page;
627 iommu_area_reserve(dom->bitmap, start_page, pages);
630 static void free_pagetable(struct protection_domain *domain)
635 p1 = domain->pt_root;
640 for (i = 0; i < 512; ++i) {
641 if (!IOMMU_PTE_PRESENT(p1[i]))
644 p2 = IOMMU_PTE_PAGE(p1[i]);
645 for (j = 0; j < 512; ++j) {
646 if (!IOMMU_PTE_PRESENT(p2[j]))
648 p3 = IOMMU_PTE_PAGE(p2[j]);
649 free_page((unsigned long)p3);
652 free_page((unsigned long)p2);
655 free_page((unsigned long)p1);
657 domain->pt_root = NULL;
661 * Free a domain, only used if something went wrong in the
662 * allocation path and we need to free an already allocated page table
664 static void dma_ops_domain_free(struct dma_ops_domain *dom)
669 free_pagetable(&dom->domain);
671 kfree(dom->pte_pages);
679 * Allocates a new protection domain usable for the dma_ops functions.
680 * It also intializes the page table and the address allocator data
681 * structures required for the dma_ops interface
683 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
686 struct dma_ops_domain *dma_dom;
687 unsigned i, num_pte_pages;
692 * Currently the DMA aperture must be between 32 MB and 1GB in size
694 if ((order < 25) || (order > 30))
697 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
701 spin_lock_init(&dma_dom->domain.lock);
703 dma_dom->domain.id = domain_id_alloc();
704 if (dma_dom->domain.id == 0)
706 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
707 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
708 dma_dom->domain.priv = dma_dom;
709 if (!dma_dom->domain.pt_root)
711 dma_dom->aperture_size = (1ULL << order);
712 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
714 if (!dma_dom->bitmap)
717 * mark the first page as allocated so we never return 0 as
718 * a valid dma-address. So we can use 0 as error value
720 dma_dom->bitmap[0] = 1;
721 dma_dom->next_bit = 0;
723 dma_dom->need_flush = false;
724 dma_dom->target_dev = 0xffff;
726 /* Intialize the exclusion range if necessary */
727 if (iommu->exclusion_start &&
728 iommu->exclusion_start < dma_dom->aperture_size) {
729 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
730 int pages = iommu_num_pages(iommu->exclusion_start,
731 iommu->exclusion_length,
733 dma_ops_reserve_addresses(dma_dom, startpage, pages);
737 * At the last step, build the page tables so we don't need to
738 * allocate page table pages in the dma_ops mapping/unmapping
741 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
742 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
744 if (!dma_dom->pte_pages)
747 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
751 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
753 for (i = 0; i < num_pte_pages; ++i) {
754 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
755 if (!dma_dom->pte_pages[i])
757 address = virt_to_phys(dma_dom->pte_pages[i]);
758 l2_pde[i] = IOMMU_L1_PDE(address);
764 dma_ops_domain_free(dma_dom);
770 * Find out the protection domain structure for a given PCI device. This
771 * will give us the pointer to the page table root for example.
773 static struct protection_domain *domain_for_device(u16 devid)
775 struct protection_domain *dom;
778 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
779 dom = amd_iommu_pd_table[devid];
780 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
786 * If a device is not yet associated with a domain, this function does
787 * assigns it visible for the hardware
789 static void set_device_domain(struct amd_iommu *iommu,
790 struct protection_domain *domain,
795 u64 pte_root = virt_to_phys(domain->pt_root);
797 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
798 << DEV_ENTRY_MODE_SHIFT;
799 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
801 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
802 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
803 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
804 amd_iommu_dev_table[devid].data[2] = domain->id;
806 amd_iommu_pd_table[devid] = domain;
807 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
809 iommu_queue_inv_dev_entry(iommu, devid);
812 /*****************************************************************************
814 * The next functions belong to the dma_ops mapping/unmapping code.
816 *****************************************************************************/
819 * This function checks if the driver got a valid device from the caller to
820 * avoid dereferencing invalid pointers.
822 static bool check_device(struct device *dev)
824 if (!dev || !dev->dma_mask)
831 * In this function the list of preallocated protection domains is traversed to
832 * find the domain for a specific device
834 static struct dma_ops_domain *find_protection_domain(u16 devid)
836 struct dma_ops_domain *entry, *ret = NULL;
839 if (list_empty(&iommu_pd_list))
842 spin_lock_irqsave(&iommu_pd_list_lock, flags);
844 list_for_each_entry(entry, &iommu_pd_list, list) {
845 if (entry->target_dev == devid) {
851 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
857 * In the dma_ops path we only have the struct device. This function
858 * finds the corresponding IOMMU, the protection domain and the
859 * requestor id for a given device.
860 * If the device is not yet associated with a domain this is also done
863 static int get_device_resources(struct device *dev,
864 struct amd_iommu **iommu,
865 struct protection_domain **domain,
868 struct dma_ops_domain *dma_dom;
869 struct pci_dev *pcidev;
876 if (dev->bus != &pci_bus_type)
879 pcidev = to_pci_dev(dev);
880 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
882 /* device not translated by any IOMMU in the system? */
883 if (_bdf > amd_iommu_last_bdf)
886 *bdf = amd_iommu_alias_table[_bdf];
888 *iommu = amd_iommu_rlookup_table[*bdf];
891 *domain = domain_for_device(*bdf);
892 if (*domain == NULL) {
893 dma_dom = find_protection_domain(*bdf);
895 dma_dom = (*iommu)->default_dom;
896 *domain = &dma_dom->domain;
897 set_device_domain(*iommu, *domain, *bdf);
898 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
899 "device ", (*domain)->id);
900 print_devid(_bdf, 1);
903 if (domain_for_device(_bdf) == NULL)
904 set_device_domain(*iommu, *domain, _bdf);
910 * This is the generic map function. It maps one 4kb page at paddr to
911 * the given address in the DMA address space for the domain.
913 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
914 struct dma_ops_domain *dom,
915 unsigned long address,
921 WARN_ON(address > dom->aperture_size);
925 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
926 pte += IOMMU_PTE_L0_INDEX(address);
928 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
930 if (direction == DMA_TO_DEVICE)
931 __pte |= IOMMU_PTE_IR;
932 else if (direction == DMA_FROM_DEVICE)
933 __pte |= IOMMU_PTE_IW;
934 else if (direction == DMA_BIDIRECTIONAL)
935 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
941 return (dma_addr_t)address;
945 * The generic unmapping function for on page in the DMA address space.
947 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
948 struct dma_ops_domain *dom,
949 unsigned long address)
953 if (address >= dom->aperture_size)
956 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
958 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
959 pte += IOMMU_PTE_L0_INDEX(address);
967 * This function contains common code for mapping of a physically
968 * contiguous memory region into DMA address space. It is used by all
969 * mapping functions provided with this IOMMU driver.
970 * Must be called with the domain lock held.
972 static dma_addr_t __map_single(struct device *dev,
973 struct amd_iommu *iommu,
974 struct dma_ops_domain *dma_dom,
981 dma_addr_t offset = paddr & ~PAGE_MASK;
982 dma_addr_t address, start;
984 unsigned long align_mask = 0;
987 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
991 align_mask = (1UL << get_order(size)) - 1;
993 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
995 if (unlikely(address == bad_dma_address))
999 for (i = 0; i < pages; ++i) {
1000 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1006 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1007 iommu_flush_tlb(iommu, dma_dom->domain.id);
1008 dma_dom->need_flush = false;
1009 } else if (unlikely(iommu_has_npcache(iommu)))
1010 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1017 * Does the reverse of the __map_single function. Must be called with
1018 * the domain lock held too
1020 static void __unmap_single(struct amd_iommu *iommu,
1021 struct dma_ops_domain *dma_dom,
1022 dma_addr_t dma_addr,
1026 dma_addr_t i, start;
1029 if ((dma_addr == bad_dma_address) ||
1030 (dma_addr + size > dma_dom->aperture_size))
1033 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1034 dma_addr &= PAGE_MASK;
1037 for (i = 0; i < pages; ++i) {
1038 dma_ops_domain_unmap(iommu, dma_dom, start);
1042 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1044 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1045 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1046 dma_dom->need_flush = false;
1051 * The exported map_single function for dma_ops.
1053 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1054 size_t size, int dir)
1056 unsigned long flags;
1057 struct amd_iommu *iommu;
1058 struct protection_domain *domain;
1063 if (!check_device(dev))
1064 return bad_dma_address;
1066 dma_mask = *dev->dma_mask;
1068 get_device_resources(dev, &iommu, &domain, &devid);
1070 if (iommu == NULL || domain == NULL)
1071 /* device not handled by any AMD IOMMU */
1072 return (dma_addr_t)paddr;
1074 spin_lock_irqsave(&domain->lock, flags);
1075 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1077 if (addr == bad_dma_address)
1080 iommu_completion_wait(iommu);
1083 spin_unlock_irqrestore(&domain->lock, flags);
1089 * The exported unmap_single function for dma_ops.
1091 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1092 size_t size, int dir)
1094 unsigned long flags;
1095 struct amd_iommu *iommu;
1096 struct protection_domain *domain;
1099 if (!check_device(dev) ||
1100 !get_device_resources(dev, &iommu, &domain, &devid))
1101 /* device not handled by any AMD IOMMU */
1104 spin_lock_irqsave(&domain->lock, flags);
1106 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1108 iommu_completion_wait(iommu);
1110 spin_unlock_irqrestore(&domain->lock, flags);
1114 * This is a special map_sg function which is used if we should map a
1115 * device which is not handled by an AMD IOMMU in the system.
1117 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1118 int nelems, int dir)
1120 struct scatterlist *s;
1123 for_each_sg(sglist, s, nelems, i) {
1124 s->dma_address = (dma_addr_t)sg_phys(s);
1125 s->dma_length = s->length;
1132 * The exported map_sg function for dma_ops (handles scatter-gather
1135 static int map_sg(struct device *dev, struct scatterlist *sglist,
1136 int nelems, int dir)
1138 unsigned long flags;
1139 struct amd_iommu *iommu;
1140 struct protection_domain *domain;
1143 struct scatterlist *s;
1145 int mapped_elems = 0;
1148 if (!check_device(dev))
1151 dma_mask = *dev->dma_mask;
1153 get_device_resources(dev, &iommu, &domain, &devid);
1155 if (!iommu || !domain)
1156 return map_sg_no_iommu(dev, sglist, nelems, dir);
1158 spin_lock_irqsave(&domain->lock, flags);
1160 for_each_sg(sglist, s, nelems, i) {
1163 s->dma_address = __map_single(dev, iommu, domain->priv,
1164 paddr, s->length, dir, false,
1167 if (s->dma_address) {
1168 s->dma_length = s->length;
1174 iommu_completion_wait(iommu);
1177 spin_unlock_irqrestore(&domain->lock, flags);
1179 return mapped_elems;
1181 for_each_sg(sglist, s, mapped_elems, i) {
1183 __unmap_single(iommu, domain->priv, s->dma_address,
1184 s->dma_length, dir);
1185 s->dma_address = s->dma_length = 0;
1194 * The exported map_sg function for dma_ops (handles scatter-gather
1197 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1198 int nelems, int dir)
1200 unsigned long flags;
1201 struct amd_iommu *iommu;
1202 struct protection_domain *domain;
1203 struct scatterlist *s;
1207 if (!check_device(dev) ||
1208 !get_device_resources(dev, &iommu, &domain, &devid))
1211 spin_lock_irqsave(&domain->lock, flags);
1213 for_each_sg(sglist, s, nelems, i) {
1214 __unmap_single(iommu, domain->priv, s->dma_address,
1215 s->dma_length, dir);
1216 s->dma_address = s->dma_length = 0;
1219 iommu_completion_wait(iommu);
1221 spin_unlock_irqrestore(&domain->lock, flags);
1225 * The exported alloc_coherent function for dma_ops.
1227 static void *alloc_coherent(struct device *dev, size_t size,
1228 dma_addr_t *dma_addr, gfp_t flag)
1230 unsigned long flags;
1232 struct amd_iommu *iommu;
1233 struct protection_domain *domain;
1236 u64 dma_mask = dev->coherent_dma_mask;
1238 if (!check_device(dev))
1241 if (!get_device_resources(dev, &iommu, &domain, &devid))
1242 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1245 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1249 paddr = virt_to_phys(virt_addr);
1251 if (!iommu || !domain) {
1252 *dma_addr = (dma_addr_t)paddr;
1257 dma_mask = *dev->dma_mask;
1259 spin_lock_irqsave(&domain->lock, flags);
1261 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1262 size, DMA_BIDIRECTIONAL, true, dma_mask);
1264 if (*dma_addr == bad_dma_address) {
1265 free_pages((unsigned long)virt_addr, get_order(size));
1270 iommu_completion_wait(iommu);
1273 spin_unlock_irqrestore(&domain->lock, flags);
1279 * The exported free_coherent function for dma_ops.
1281 static void free_coherent(struct device *dev, size_t size,
1282 void *virt_addr, dma_addr_t dma_addr)
1284 unsigned long flags;
1285 struct amd_iommu *iommu;
1286 struct protection_domain *domain;
1289 if (!check_device(dev))
1292 get_device_resources(dev, &iommu, &domain, &devid);
1294 if (!iommu || !domain)
1297 spin_lock_irqsave(&domain->lock, flags);
1299 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1301 iommu_completion_wait(iommu);
1303 spin_unlock_irqrestore(&domain->lock, flags);
1306 free_pages((unsigned long)virt_addr, get_order(size));
1310 * This function is called by the DMA layer to find out if we can handle a
1311 * particular device. It is part of the dma_ops.
1313 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1316 struct pci_dev *pcidev;
1318 /* No device or no PCI device */
1319 if (!dev || dev->bus != &pci_bus_type)
1322 pcidev = to_pci_dev(dev);
1324 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1326 /* Out of our scope? */
1327 if (bdf > amd_iommu_last_bdf)
1334 * The function for pre-allocating protection domains.
1336 * If the driver core informs the DMA layer if a driver grabs a device
1337 * we don't need to preallocate the protection domains anymore.
1338 * For now we have to.
1340 void prealloc_protection_domains(void)
1342 struct pci_dev *dev = NULL;
1343 struct dma_ops_domain *dma_dom;
1344 struct amd_iommu *iommu;
1345 int order = amd_iommu_aperture_order;
1348 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1349 devid = (dev->bus->number << 8) | dev->devfn;
1350 if (devid > amd_iommu_last_bdf)
1352 devid = amd_iommu_alias_table[devid];
1353 if (domain_for_device(devid))
1355 iommu = amd_iommu_rlookup_table[devid];
1358 dma_dom = dma_ops_domain_alloc(iommu, order);
1361 init_unity_mappings_for_device(dma_dom, devid);
1362 dma_dom->target_dev = devid;
1364 list_add_tail(&dma_dom->list, &iommu_pd_list);
1368 static struct dma_mapping_ops amd_iommu_dma_ops = {
1369 .alloc_coherent = alloc_coherent,
1370 .free_coherent = free_coherent,
1371 .map_single = map_single,
1372 .unmap_single = unmap_single,
1374 .unmap_sg = unmap_sg,
1375 .dma_supported = amd_iommu_dma_supported,
1379 * The function which clues the AMD IOMMU driver into dma_ops.
1381 int __init amd_iommu_init_dma_ops(void)
1383 struct amd_iommu *iommu;
1384 int order = amd_iommu_aperture_order;
1388 * first allocate a default protection domain for every IOMMU we
1389 * found in the system. Devices not assigned to any other
1390 * protection domain will be assigned to the default one.
1392 list_for_each_entry(iommu, &amd_iommu_list, list) {
1393 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1394 if (iommu->default_dom == NULL)
1396 ret = iommu_init_unity_mappings(iommu);
1402 * If device isolation is enabled, pre-allocate the protection
1403 * domains for each device.
1405 if (amd_iommu_isolate)
1406 prealloc_protection_domains();
1410 bad_dma_address = 0;
1411 #ifdef CONFIG_GART_IOMMU
1412 gart_iommu_aperture_disabled = 1;
1413 gart_iommu_aperture = 0;
1416 /* Make the driver finally visible to the drivers */
1417 dma_ops = &amd_iommu_dma_ops;
1423 list_for_each_entry(iommu, &amd_iommu_list, list) {
1424 if (iommu->default_dom)
1425 dma_ops_domain_free(iommu->default_dom);