2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
70 DECLARE_STATS_COUNTER(cnt_map_sg);
71 DECLARE_STATS_COUNTER(cnt_unmap_sg);
72 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
73 DECLARE_STATS_COUNTER(cnt_free_coherent);
74 DECLARE_STATS_COUNTER(cross_page);
76 static struct dentry *stats_dir;
77 static struct dentry *de_isolate;
78 static struct dentry *de_fflush;
80 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
82 if (stats_dir == NULL)
85 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
89 static void amd_iommu_stats_init(void)
91 stats_dir = debugfs_create_dir("amd-iommu", NULL);
92 if (stats_dir == NULL)
95 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
96 (u32 *)&amd_iommu_isolate);
98 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
99 (u32 *)&amd_iommu_unmap_flush);
101 amd_iommu_stats_add(&compl_wait);
102 amd_iommu_stats_add(&cnt_map_single);
103 amd_iommu_stats_add(&cnt_unmap_single);
104 amd_iommu_stats_add(&cnt_map_sg);
105 amd_iommu_stats_add(&cnt_unmap_sg);
106 amd_iommu_stats_add(&cnt_alloc_coherent);
107 amd_iommu_stats_add(&cnt_free_coherent);
108 amd_iommu_stats_add(&cross_page);
113 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
114 static int iommu_has_npcache(struct amd_iommu *iommu)
116 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
119 /****************************************************************************
121 * Interrupt handling functions
123 ****************************************************************************/
125 static void iommu_print_event(void *__evt)
128 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
129 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
130 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
131 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
132 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
134 printk(KERN_ERR "AMD IOMMU: Event logged [");
137 case EVENT_TYPE_ILL_DEV:
138 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
139 "address=0x%016llx flags=0x%04x]\n",
140 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
143 case EVENT_TYPE_IO_FAULT:
144 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
145 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
146 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
147 domid, address, flags);
149 case EVENT_TYPE_DEV_TAB_ERR:
150 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
151 "address=0x%016llx flags=0x%04x]\n",
152 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
155 case EVENT_TYPE_PAGE_TAB_ERR:
156 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
157 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
158 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
159 domid, address, flags);
161 case EVENT_TYPE_ILL_CMD:
162 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
164 case EVENT_TYPE_CMD_HARD_ERR:
165 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
166 "flags=0x%04x]\n", address, flags);
168 case EVENT_TYPE_IOTLB_INV_TO:
169 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
170 "address=0x%016llx]\n",
171 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
174 case EVENT_TYPE_INV_DEV_REQ:
175 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
176 "address=0x%016llx flags=0x%04x]\n",
177 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
185 static void iommu_poll_events(struct amd_iommu *iommu)
190 spin_lock_irqsave(&iommu->lock, flags);
192 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
193 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
195 while (head != tail) {
196 iommu_print_event(iommu->evt_buf + head);
197 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
200 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
202 spin_unlock_irqrestore(&iommu->lock, flags);
205 irqreturn_t amd_iommu_int_handler(int irq, void *data)
207 struct amd_iommu *iommu;
209 list_for_each_entry(iommu, &amd_iommu_list, list)
210 iommu_poll_events(iommu);
215 /****************************************************************************
217 * IOMMU command queuing functions
219 ****************************************************************************/
222 * Writes the command to the IOMMUs command buffer and informs the
223 * hardware about the new command. Must be called with iommu->lock held.
225 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
230 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
231 target = iommu->cmd_buf + tail;
232 memcpy_toio(target, cmd, sizeof(*cmd));
233 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
234 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
237 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
243 * General queuing function for commands. Takes iommu->lock and calls
244 * __iommu_queue_command().
246 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
251 spin_lock_irqsave(&iommu->lock, flags);
252 ret = __iommu_queue_command(iommu, cmd);
254 iommu->need_sync = true;
255 spin_unlock_irqrestore(&iommu->lock, flags);
261 * This function waits until an IOMMU has completed a completion
264 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
270 INC_STATS_COUNTER(compl_wait);
272 while (!ready && (i < EXIT_LOOP_COUNT)) {
274 /* wait for the bit to become one */
275 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
276 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
279 /* set bit back to zero */
280 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
281 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
283 if (unlikely(i == EXIT_LOOP_COUNT))
284 panic("AMD IOMMU: Completion wait loop failed\n");
288 * This function queues a completion wait command into the command
291 static int __iommu_completion_wait(struct amd_iommu *iommu)
293 struct iommu_cmd cmd;
295 memset(&cmd, 0, sizeof(cmd));
296 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
297 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
299 return __iommu_queue_command(iommu, &cmd);
303 * This function is called whenever we need to ensure that the IOMMU has
304 * completed execution of all commands we sent. It sends a
305 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
306 * us about that by writing a value to a physical address we pass with
309 static int iommu_completion_wait(struct amd_iommu *iommu)
314 spin_lock_irqsave(&iommu->lock, flags);
316 if (!iommu->need_sync)
319 ret = __iommu_completion_wait(iommu);
321 iommu->need_sync = false;
326 __iommu_wait_for_completion(iommu);
329 spin_unlock_irqrestore(&iommu->lock, flags);
335 * Command send function for invalidating a device table entry
337 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
339 struct iommu_cmd cmd;
342 BUG_ON(iommu == NULL);
344 memset(&cmd, 0, sizeof(cmd));
345 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
348 ret = iommu_queue_command(iommu, &cmd);
353 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
354 u16 domid, int pde, int s)
356 memset(cmd, 0, sizeof(*cmd));
357 address &= PAGE_MASK;
358 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
359 cmd->data[1] |= domid;
360 cmd->data[2] = lower_32_bits(address);
361 cmd->data[3] = upper_32_bits(address);
362 if (s) /* size bit - we flush more than one 4kb page */
363 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
364 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
365 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
369 * Generic command send function for invalidaing TLB entries
371 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
372 u64 address, u16 domid, int pde, int s)
374 struct iommu_cmd cmd;
377 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
379 ret = iommu_queue_command(iommu, &cmd);
385 * TLB invalidation function which is called from the mapping functions.
386 * It invalidates a single PTE if the range to flush is within a single
387 * page. Otherwise it flushes the whole TLB of the IOMMU.
389 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
390 u64 address, size_t size)
393 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
395 address &= PAGE_MASK;
399 * If we have to flush more than one page, flush all
400 * TLB entries for this domain
402 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
406 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
411 /* Flush the whole IO/TLB for a given protection domain */
412 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
414 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
416 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
419 #ifdef CONFIG_IOMMU_API
421 * This function is used to flush the IO/TLB for a given protection domain
422 * on every IOMMU in the system
424 static void iommu_flush_domain(u16 domid)
427 struct amd_iommu *iommu;
428 struct iommu_cmd cmd;
430 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
433 list_for_each_entry(iommu, &amd_iommu_list, list) {
434 spin_lock_irqsave(&iommu->lock, flags);
435 __iommu_queue_command(iommu, &cmd);
436 __iommu_completion_wait(iommu);
437 __iommu_wait_for_completion(iommu);
438 spin_unlock_irqrestore(&iommu->lock, flags);
443 /****************************************************************************
445 * The functions below are used the create the page table mappings for
446 * unity mapped regions.
448 ****************************************************************************/
451 * Generic mapping functions. It maps a physical address into a DMA
452 * address space. It allocates the page table pages if necessary.
453 * In the future it can be extended to a generic mapping function
454 * supporting all features of AMD IOMMU page tables like level skipping
455 * and full 64 bit address spaces.
457 static int iommu_map_page(struct protection_domain *dom,
458 unsigned long bus_addr,
459 unsigned long phys_addr,
462 u64 __pte, *pte, *page;
464 bus_addr = PAGE_ALIGN(bus_addr);
465 phys_addr = PAGE_ALIGN(phys_addr);
467 /* only support 512GB address spaces for now */
468 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
471 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
473 if (!IOMMU_PTE_PRESENT(*pte)) {
474 page = (u64 *)get_zeroed_page(GFP_KERNEL);
477 *pte = IOMMU_L2_PDE(virt_to_phys(page));
480 pte = IOMMU_PTE_PAGE(*pte);
481 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
483 if (!IOMMU_PTE_PRESENT(*pte)) {
484 page = (u64 *)get_zeroed_page(GFP_KERNEL);
487 *pte = IOMMU_L1_PDE(virt_to_phys(page));
490 pte = IOMMU_PTE_PAGE(*pte);
491 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
493 if (IOMMU_PTE_PRESENT(*pte))
496 __pte = phys_addr | IOMMU_PTE_P;
497 if (prot & IOMMU_PROT_IR)
498 __pte |= IOMMU_PTE_IR;
499 if (prot & IOMMU_PROT_IW)
500 __pte |= IOMMU_PTE_IW;
507 #ifdef CONFIG_IOMMU_API
508 static void iommu_unmap_page(struct protection_domain *dom,
509 unsigned long bus_addr)
513 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
515 if (!IOMMU_PTE_PRESENT(*pte))
518 pte = IOMMU_PTE_PAGE(*pte);
519 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
521 if (!IOMMU_PTE_PRESENT(*pte))
524 pte = IOMMU_PTE_PAGE(*pte);
525 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
532 * This function checks if a specific unity mapping entry is needed for
533 * this specific IOMMU.
535 static int iommu_for_unity_map(struct amd_iommu *iommu,
536 struct unity_map_entry *entry)
540 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
541 bdf = amd_iommu_alias_table[i];
542 if (amd_iommu_rlookup_table[bdf] == iommu)
550 * Init the unity mappings for a specific IOMMU in the system
552 * Basically iterates over all unity mapping entries and applies them to
553 * the default domain DMA of that IOMMU if necessary.
555 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
557 struct unity_map_entry *entry;
560 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
561 if (!iommu_for_unity_map(iommu, entry))
563 ret = dma_ops_unity_map(iommu->default_dom, entry);
572 * This function actually applies the mapping to the page table of the
575 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
576 struct unity_map_entry *e)
581 for (addr = e->address_start; addr < e->address_end;
583 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
587 * if unity mapping is in aperture range mark the page
588 * as allocated in the aperture
590 if (addr < dma_dom->aperture_size)
591 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
598 * Inits the unity mappings required for a specific device
600 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
603 struct unity_map_entry *e;
606 list_for_each_entry(e, &amd_iommu_unity_map, list) {
607 if (!(devid >= e->devid_start && devid <= e->devid_end))
609 ret = dma_ops_unity_map(dma_dom, e);
617 /****************************************************************************
619 * The next functions belong to the address allocator for the dma_ops
620 * interface functions. They work like the allocators in the other IOMMU
621 * drivers. Its basically a bitmap which marks the allocated pages in
622 * the aperture. Maybe it could be enhanced in the future to a more
623 * efficient allocator.
625 ****************************************************************************/
628 * The address allocator core function.
630 * called with domain->lock held
632 static unsigned long dma_ops_alloc_addresses(struct device *dev,
633 struct dma_ops_domain *dom,
635 unsigned long align_mask,
639 unsigned long address;
640 unsigned long boundary_size;
642 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
643 PAGE_SIZE) >> PAGE_SHIFT;
644 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
645 dma_mask >> PAGE_SHIFT);
647 if (dom->next_bit >= limit) {
649 dom->need_flush = true;
652 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
653 0 , boundary_size, align_mask);
655 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
656 0, boundary_size, align_mask);
657 dom->need_flush = true;
660 if (likely(address != -1)) {
661 dom->next_bit = address + pages;
662 address <<= PAGE_SHIFT;
664 address = bad_dma_address;
666 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
672 * The address free function.
674 * called with domain->lock held
676 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
677 unsigned long address,
680 address >>= PAGE_SHIFT;
681 iommu_area_free(dom->bitmap, address, pages);
683 if (address >= dom->next_bit)
684 dom->need_flush = true;
687 /****************************************************************************
689 * The next functions belong to the domain allocation. A domain is
690 * allocated for every IOMMU as the default domain. If device isolation
691 * is enabled, every device get its own domain. The most important thing
692 * about domains is the page table mapping the DMA address space they
695 ****************************************************************************/
697 static u16 domain_id_alloc(void)
702 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
703 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
705 if (id > 0 && id < MAX_DOMAIN_ID)
706 __set_bit(id, amd_iommu_pd_alloc_bitmap);
709 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
714 #ifdef CONFIG_IOMMU_API
715 static void domain_id_free(int id)
719 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
720 if (id > 0 && id < MAX_DOMAIN_ID)
721 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
722 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
727 * Used to reserve address ranges in the aperture (e.g. for exclusion
730 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
731 unsigned long start_page,
734 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
736 if (start_page + pages > last_page)
737 pages = last_page - start_page;
739 iommu_area_reserve(dom->bitmap, start_page, pages);
742 static void free_pagetable(struct protection_domain *domain)
747 p1 = domain->pt_root;
752 for (i = 0; i < 512; ++i) {
753 if (!IOMMU_PTE_PRESENT(p1[i]))
756 p2 = IOMMU_PTE_PAGE(p1[i]);
757 for (j = 0; j < 512; ++j) {
758 if (!IOMMU_PTE_PRESENT(p2[j]))
760 p3 = IOMMU_PTE_PAGE(p2[j]);
761 free_page((unsigned long)p3);
764 free_page((unsigned long)p2);
767 free_page((unsigned long)p1);
769 domain->pt_root = NULL;
773 * Free a domain, only used if something went wrong in the
774 * allocation path and we need to free an already allocated page table
776 static void dma_ops_domain_free(struct dma_ops_domain *dom)
781 free_pagetable(&dom->domain);
783 kfree(dom->pte_pages);
791 * Allocates a new protection domain usable for the dma_ops functions.
792 * It also intializes the page table and the address allocator data
793 * structures required for the dma_ops interface
795 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
798 struct dma_ops_domain *dma_dom;
799 unsigned i, num_pte_pages;
804 * Currently the DMA aperture must be between 32 MB and 1GB in size
806 if ((order < 25) || (order > 30))
809 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
813 spin_lock_init(&dma_dom->domain.lock);
815 dma_dom->domain.id = domain_id_alloc();
816 if (dma_dom->domain.id == 0)
818 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
819 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
820 dma_dom->domain.flags = PD_DMA_OPS_MASK;
821 dma_dom->domain.priv = dma_dom;
822 if (!dma_dom->domain.pt_root)
824 dma_dom->aperture_size = (1ULL << order);
825 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
827 if (!dma_dom->bitmap)
830 * mark the first page as allocated so we never return 0 as
831 * a valid dma-address. So we can use 0 as error value
833 dma_dom->bitmap[0] = 1;
834 dma_dom->next_bit = 0;
836 dma_dom->need_flush = false;
837 dma_dom->target_dev = 0xffff;
839 /* Intialize the exclusion range if necessary */
840 if (iommu->exclusion_start &&
841 iommu->exclusion_start < dma_dom->aperture_size) {
842 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
843 int pages = iommu_num_pages(iommu->exclusion_start,
844 iommu->exclusion_length,
846 dma_ops_reserve_addresses(dma_dom, startpage, pages);
850 * At the last step, build the page tables so we don't need to
851 * allocate page table pages in the dma_ops mapping/unmapping
854 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
855 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
857 if (!dma_dom->pte_pages)
860 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
864 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
866 for (i = 0; i < num_pte_pages; ++i) {
867 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
868 if (!dma_dom->pte_pages[i])
870 address = virt_to_phys(dma_dom->pte_pages[i]);
871 l2_pde[i] = IOMMU_L1_PDE(address);
877 dma_ops_domain_free(dma_dom);
883 * little helper function to check whether a given protection domain is a
886 static bool dma_ops_domain(struct protection_domain *domain)
888 return domain->flags & PD_DMA_OPS_MASK;
892 * Find out the protection domain structure for a given PCI device. This
893 * will give us the pointer to the page table root for example.
895 static struct protection_domain *domain_for_device(u16 devid)
897 struct protection_domain *dom;
900 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
901 dom = amd_iommu_pd_table[devid];
902 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
908 * If a device is not yet associated with a domain, this function does
909 * assigns it visible for the hardware
911 static void attach_device(struct amd_iommu *iommu,
912 struct protection_domain *domain,
916 u64 pte_root = virt_to_phys(domain->pt_root);
918 domain->dev_cnt += 1;
920 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
921 << DEV_ENTRY_MODE_SHIFT;
922 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
924 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
925 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
926 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
927 amd_iommu_dev_table[devid].data[2] = domain->id;
929 amd_iommu_pd_table[devid] = domain;
930 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
932 iommu_queue_inv_dev_entry(iommu, devid);
936 * Removes a device from a protection domain (unlocked)
938 static void __detach_device(struct protection_domain *domain, u16 devid)
942 spin_lock(&domain->lock);
944 /* remove domain from the lookup table */
945 amd_iommu_pd_table[devid] = NULL;
947 /* remove entry from the device table seen by the hardware */
948 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
949 amd_iommu_dev_table[devid].data[1] = 0;
950 amd_iommu_dev_table[devid].data[2] = 0;
952 /* decrease reference counter */
953 domain->dev_cnt -= 1;
956 spin_unlock(&domain->lock);
960 * Removes a device from a protection domain (with devtable_lock held)
962 static void detach_device(struct protection_domain *domain, u16 devid)
966 /* lock device table */
967 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
968 __detach_device(domain, devid);
969 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
972 static int device_change_notifier(struct notifier_block *nb,
973 unsigned long action, void *data)
975 struct device *dev = data;
976 struct pci_dev *pdev = to_pci_dev(dev);
977 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
978 struct protection_domain *domain;
979 struct dma_ops_domain *dma_domain;
980 struct amd_iommu *iommu;
981 int order = amd_iommu_aperture_order;
984 if (devid > amd_iommu_last_bdf)
987 devid = amd_iommu_alias_table[devid];
989 iommu = amd_iommu_rlookup_table[devid];
993 domain = domain_for_device(devid);
995 if (domain && !dma_ops_domain(domain))
996 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
997 "to a non-dma-ops domain\n", dev_name(dev));
1000 case BUS_NOTIFY_BOUND_DRIVER:
1003 dma_domain = find_protection_domain(devid);
1005 dma_domain = iommu->default_dom;
1006 attach_device(iommu, &dma_domain->domain, devid);
1007 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1008 "device %s\n", dma_domain->domain.id, dev_name(dev));
1010 case BUS_NOTIFY_UNBIND_DRIVER:
1013 detach_device(domain, devid);
1015 case BUS_NOTIFY_ADD_DEVICE:
1016 /* allocate a protection domain if a device is added */
1017 dma_domain = find_protection_domain(devid);
1020 dma_domain = dma_ops_domain_alloc(iommu, order);
1023 dma_domain->target_dev = devid;
1025 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1026 list_add_tail(&dma_domain->list, &iommu_pd_list);
1027 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1034 iommu_queue_inv_dev_entry(iommu, devid);
1035 iommu_completion_wait(iommu);
1041 struct notifier_block device_nb = {
1042 .notifier_call = device_change_notifier,
1045 /*****************************************************************************
1047 * The next functions belong to the dma_ops mapping/unmapping code.
1049 *****************************************************************************/
1052 * This function checks if the driver got a valid device from the caller to
1053 * avoid dereferencing invalid pointers.
1055 static bool check_device(struct device *dev)
1057 if (!dev || !dev->dma_mask)
1064 * In this function the list of preallocated protection domains is traversed to
1065 * find the domain for a specific device
1067 static struct dma_ops_domain *find_protection_domain(u16 devid)
1069 struct dma_ops_domain *entry, *ret = NULL;
1070 unsigned long flags;
1072 if (list_empty(&iommu_pd_list))
1075 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1077 list_for_each_entry(entry, &iommu_pd_list, list) {
1078 if (entry->target_dev == devid) {
1084 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1090 * In the dma_ops path we only have the struct device. This function
1091 * finds the corresponding IOMMU, the protection domain and the
1092 * requestor id for a given device.
1093 * If the device is not yet associated with a domain this is also done
1096 static int get_device_resources(struct device *dev,
1097 struct amd_iommu **iommu,
1098 struct protection_domain **domain,
1101 struct dma_ops_domain *dma_dom;
1102 struct pci_dev *pcidev;
1109 if (dev->bus != &pci_bus_type)
1112 pcidev = to_pci_dev(dev);
1113 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1115 /* device not translated by any IOMMU in the system? */
1116 if (_bdf > amd_iommu_last_bdf)
1119 *bdf = amd_iommu_alias_table[_bdf];
1121 *iommu = amd_iommu_rlookup_table[*bdf];
1124 *domain = domain_for_device(*bdf);
1125 if (*domain == NULL) {
1126 dma_dom = find_protection_domain(*bdf);
1128 dma_dom = (*iommu)->default_dom;
1129 *domain = &dma_dom->domain;
1130 attach_device(*iommu, *domain, *bdf);
1131 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1132 "device %s\n", (*domain)->id, dev_name(dev));
1135 if (domain_for_device(_bdf) == NULL)
1136 attach_device(*iommu, *domain, _bdf);
1142 * This is the generic map function. It maps one 4kb page at paddr to
1143 * the given address in the DMA address space for the domain.
1145 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1146 struct dma_ops_domain *dom,
1147 unsigned long address,
1153 WARN_ON(address > dom->aperture_size);
1157 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1158 pte += IOMMU_PTE_L0_INDEX(address);
1160 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1162 if (direction == DMA_TO_DEVICE)
1163 __pte |= IOMMU_PTE_IR;
1164 else if (direction == DMA_FROM_DEVICE)
1165 __pte |= IOMMU_PTE_IW;
1166 else if (direction == DMA_BIDIRECTIONAL)
1167 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1173 return (dma_addr_t)address;
1177 * The generic unmapping function for on page in the DMA address space.
1179 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1180 struct dma_ops_domain *dom,
1181 unsigned long address)
1185 if (address >= dom->aperture_size)
1188 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1190 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1191 pte += IOMMU_PTE_L0_INDEX(address);
1199 * This function contains common code for mapping of a physically
1200 * contiguous memory region into DMA address space. It is used by all
1201 * mapping functions provided with this IOMMU driver.
1202 * Must be called with the domain lock held.
1204 static dma_addr_t __map_single(struct device *dev,
1205 struct amd_iommu *iommu,
1206 struct dma_ops_domain *dma_dom,
1213 dma_addr_t offset = paddr & ~PAGE_MASK;
1214 dma_addr_t address, start;
1216 unsigned long align_mask = 0;
1219 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1223 INC_STATS_COUNTER(cross_page);
1226 align_mask = (1UL << get_order(size)) - 1;
1228 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1230 if (unlikely(address == bad_dma_address))
1234 for (i = 0; i < pages; ++i) {
1235 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1241 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1242 iommu_flush_tlb(iommu, dma_dom->domain.id);
1243 dma_dom->need_flush = false;
1244 } else if (unlikely(iommu_has_npcache(iommu)))
1245 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1252 * Does the reverse of the __map_single function. Must be called with
1253 * the domain lock held too
1255 static void __unmap_single(struct amd_iommu *iommu,
1256 struct dma_ops_domain *dma_dom,
1257 dma_addr_t dma_addr,
1261 dma_addr_t i, start;
1264 if ((dma_addr == bad_dma_address) ||
1265 (dma_addr + size > dma_dom->aperture_size))
1268 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1269 dma_addr &= PAGE_MASK;
1272 for (i = 0; i < pages; ++i) {
1273 dma_ops_domain_unmap(iommu, dma_dom, start);
1277 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1279 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1280 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1281 dma_dom->need_flush = false;
1286 * The exported map_single function for dma_ops.
1288 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1289 size_t size, int dir)
1291 unsigned long flags;
1292 struct amd_iommu *iommu;
1293 struct protection_domain *domain;
1298 INC_STATS_COUNTER(cnt_map_single);
1300 if (!check_device(dev))
1301 return bad_dma_address;
1303 dma_mask = *dev->dma_mask;
1305 get_device_resources(dev, &iommu, &domain, &devid);
1307 if (iommu == NULL || domain == NULL)
1308 /* device not handled by any AMD IOMMU */
1309 return (dma_addr_t)paddr;
1311 if (!dma_ops_domain(domain))
1312 return bad_dma_address;
1314 spin_lock_irqsave(&domain->lock, flags);
1315 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1317 if (addr == bad_dma_address)
1320 iommu_completion_wait(iommu);
1323 spin_unlock_irqrestore(&domain->lock, flags);
1329 * The exported unmap_single function for dma_ops.
1331 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1332 size_t size, int dir)
1334 unsigned long flags;
1335 struct amd_iommu *iommu;
1336 struct protection_domain *domain;
1339 INC_STATS_COUNTER(cnt_unmap_single);
1341 if (!check_device(dev) ||
1342 !get_device_resources(dev, &iommu, &domain, &devid))
1343 /* device not handled by any AMD IOMMU */
1346 if (!dma_ops_domain(domain))
1349 spin_lock_irqsave(&domain->lock, flags);
1351 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1353 iommu_completion_wait(iommu);
1355 spin_unlock_irqrestore(&domain->lock, flags);
1359 * This is a special map_sg function which is used if we should map a
1360 * device which is not handled by an AMD IOMMU in the system.
1362 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1363 int nelems, int dir)
1365 struct scatterlist *s;
1368 for_each_sg(sglist, s, nelems, i) {
1369 s->dma_address = (dma_addr_t)sg_phys(s);
1370 s->dma_length = s->length;
1377 * The exported map_sg function for dma_ops (handles scatter-gather
1380 static int map_sg(struct device *dev, struct scatterlist *sglist,
1381 int nelems, int dir)
1383 unsigned long flags;
1384 struct amd_iommu *iommu;
1385 struct protection_domain *domain;
1388 struct scatterlist *s;
1390 int mapped_elems = 0;
1393 INC_STATS_COUNTER(cnt_map_sg);
1395 if (!check_device(dev))
1398 dma_mask = *dev->dma_mask;
1400 get_device_resources(dev, &iommu, &domain, &devid);
1402 if (!iommu || !domain)
1403 return map_sg_no_iommu(dev, sglist, nelems, dir);
1405 if (!dma_ops_domain(domain))
1408 spin_lock_irqsave(&domain->lock, flags);
1410 for_each_sg(sglist, s, nelems, i) {
1413 s->dma_address = __map_single(dev, iommu, domain->priv,
1414 paddr, s->length, dir, false,
1417 if (s->dma_address) {
1418 s->dma_length = s->length;
1424 iommu_completion_wait(iommu);
1427 spin_unlock_irqrestore(&domain->lock, flags);
1429 return mapped_elems;
1431 for_each_sg(sglist, s, mapped_elems, i) {
1433 __unmap_single(iommu, domain->priv, s->dma_address,
1434 s->dma_length, dir);
1435 s->dma_address = s->dma_length = 0;
1444 * The exported map_sg function for dma_ops (handles scatter-gather
1447 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1448 int nelems, int dir)
1450 unsigned long flags;
1451 struct amd_iommu *iommu;
1452 struct protection_domain *domain;
1453 struct scatterlist *s;
1457 INC_STATS_COUNTER(cnt_unmap_sg);
1459 if (!check_device(dev) ||
1460 !get_device_resources(dev, &iommu, &domain, &devid))
1463 if (!dma_ops_domain(domain))
1466 spin_lock_irqsave(&domain->lock, flags);
1468 for_each_sg(sglist, s, nelems, i) {
1469 __unmap_single(iommu, domain->priv, s->dma_address,
1470 s->dma_length, dir);
1471 s->dma_address = s->dma_length = 0;
1474 iommu_completion_wait(iommu);
1476 spin_unlock_irqrestore(&domain->lock, flags);
1480 * The exported alloc_coherent function for dma_ops.
1482 static void *alloc_coherent(struct device *dev, size_t size,
1483 dma_addr_t *dma_addr, gfp_t flag)
1485 unsigned long flags;
1487 struct amd_iommu *iommu;
1488 struct protection_domain *domain;
1491 u64 dma_mask = dev->coherent_dma_mask;
1493 INC_STATS_COUNTER(cnt_alloc_coherent);
1495 if (!check_device(dev))
1498 if (!get_device_resources(dev, &iommu, &domain, &devid))
1499 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1502 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1506 paddr = virt_to_phys(virt_addr);
1508 if (!iommu || !domain) {
1509 *dma_addr = (dma_addr_t)paddr;
1513 if (!dma_ops_domain(domain))
1517 dma_mask = *dev->dma_mask;
1519 spin_lock_irqsave(&domain->lock, flags);
1521 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1522 size, DMA_BIDIRECTIONAL, true, dma_mask);
1524 if (*dma_addr == bad_dma_address)
1527 iommu_completion_wait(iommu);
1529 spin_unlock_irqrestore(&domain->lock, flags);
1535 free_pages((unsigned long)virt_addr, get_order(size));
1541 * The exported free_coherent function for dma_ops.
1543 static void free_coherent(struct device *dev, size_t size,
1544 void *virt_addr, dma_addr_t dma_addr)
1546 unsigned long flags;
1547 struct amd_iommu *iommu;
1548 struct protection_domain *domain;
1551 INC_STATS_COUNTER(cnt_free_coherent);
1553 if (!check_device(dev))
1556 get_device_resources(dev, &iommu, &domain, &devid);
1558 if (!iommu || !domain)
1561 if (!dma_ops_domain(domain))
1564 spin_lock_irqsave(&domain->lock, flags);
1566 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1568 iommu_completion_wait(iommu);
1570 spin_unlock_irqrestore(&domain->lock, flags);
1573 free_pages((unsigned long)virt_addr, get_order(size));
1577 * This function is called by the DMA layer to find out if we can handle a
1578 * particular device. It is part of the dma_ops.
1580 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1583 struct pci_dev *pcidev;
1585 /* No device or no PCI device */
1586 if (!dev || dev->bus != &pci_bus_type)
1589 pcidev = to_pci_dev(dev);
1591 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1593 /* Out of our scope? */
1594 if (bdf > amd_iommu_last_bdf)
1601 * The function for pre-allocating protection domains.
1603 * If the driver core informs the DMA layer if a driver grabs a device
1604 * we don't need to preallocate the protection domains anymore.
1605 * For now we have to.
1607 void prealloc_protection_domains(void)
1609 struct pci_dev *dev = NULL;
1610 struct dma_ops_domain *dma_dom;
1611 struct amd_iommu *iommu;
1612 int order = amd_iommu_aperture_order;
1615 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1616 devid = calc_devid(dev->bus->number, dev->devfn);
1617 if (devid > amd_iommu_last_bdf)
1619 devid = amd_iommu_alias_table[devid];
1620 if (domain_for_device(devid))
1622 iommu = amd_iommu_rlookup_table[devid];
1625 dma_dom = dma_ops_domain_alloc(iommu, order);
1628 init_unity_mappings_for_device(dma_dom, devid);
1629 dma_dom->target_dev = devid;
1631 list_add_tail(&dma_dom->list, &iommu_pd_list);
1635 static struct dma_mapping_ops amd_iommu_dma_ops = {
1636 .alloc_coherent = alloc_coherent,
1637 .free_coherent = free_coherent,
1638 .map_single = map_single,
1639 .unmap_single = unmap_single,
1641 .unmap_sg = unmap_sg,
1642 .dma_supported = amd_iommu_dma_supported,
1646 * The function which clues the AMD IOMMU driver into dma_ops.
1648 int __init amd_iommu_init_dma_ops(void)
1650 struct amd_iommu *iommu;
1651 int order = amd_iommu_aperture_order;
1655 * first allocate a default protection domain for every IOMMU we
1656 * found in the system. Devices not assigned to any other
1657 * protection domain will be assigned to the default one.
1659 list_for_each_entry(iommu, &amd_iommu_list, list) {
1660 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1661 if (iommu->default_dom == NULL)
1663 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1664 ret = iommu_init_unity_mappings(iommu);
1670 * If device isolation is enabled, pre-allocate the protection
1671 * domains for each device.
1673 if (amd_iommu_isolate)
1674 prealloc_protection_domains();
1678 bad_dma_address = 0;
1679 #ifdef CONFIG_GART_IOMMU
1680 gart_iommu_aperture_disabled = 1;
1681 gart_iommu_aperture = 0;
1684 /* Make the driver finally visible to the drivers */
1685 dma_ops = &amd_iommu_dma_ops;
1687 #ifdef CONFIG_IOMMU_API
1688 register_iommu(&amd_iommu_ops);
1691 bus_register_notifier(&pci_bus_type, &device_nb);
1693 amd_iommu_stats_init();
1699 list_for_each_entry(iommu, &amd_iommu_list, list) {
1700 if (iommu->default_dom)
1701 dma_ops_domain_free(iommu->default_dom);
1707 /*****************************************************************************
1709 * The following functions belong to the exported interface of AMD IOMMU
1711 * This interface allows access to lower level functions of the IOMMU
1712 * like protection domain handling and assignement of devices to domains
1713 * which is not possible with the dma_ops interface.
1715 *****************************************************************************/
1717 #ifdef CONFIG_IOMMU_API
1719 static void cleanup_domain(struct protection_domain *domain)
1721 unsigned long flags;
1724 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1726 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1727 if (amd_iommu_pd_table[devid] == domain)
1728 __detach_device(domain, devid);
1730 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1733 static int amd_iommu_domain_init(struct iommu_domain *dom)
1735 struct protection_domain *domain;
1737 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1741 spin_lock_init(&domain->lock);
1742 domain->mode = PAGE_MODE_3_LEVEL;
1743 domain->id = domain_id_alloc();
1746 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1747 if (!domain->pt_root)
1760 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1762 struct protection_domain *domain = dom->priv;
1767 if (domain->dev_cnt > 0)
1768 cleanup_domain(domain);
1770 BUG_ON(domain->dev_cnt != 0);
1772 free_pagetable(domain);
1774 domain_id_free(domain->id);
1781 static void amd_iommu_detach_device(struct iommu_domain *dom,
1784 struct protection_domain *domain = dom->priv;
1785 struct amd_iommu *iommu;
1786 struct pci_dev *pdev;
1789 if (dev->bus != &pci_bus_type)
1792 pdev = to_pci_dev(dev);
1794 devid = calc_devid(pdev->bus->number, pdev->devfn);
1797 detach_device(domain, devid);
1799 iommu = amd_iommu_rlookup_table[devid];
1803 iommu_queue_inv_dev_entry(iommu, devid);
1804 iommu_completion_wait(iommu);
1807 static int amd_iommu_attach_device(struct iommu_domain *dom,
1810 struct protection_domain *domain = dom->priv;
1811 struct protection_domain *old_domain;
1812 struct amd_iommu *iommu;
1813 struct pci_dev *pdev;
1816 if (dev->bus != &pci_bus_type)
1819 pdev = to_pci_dev(dev);
1821 devid = calc_devid(pdev->bus->number, pdev->devfn);
1823 if (devid >= amd_iommu_last_bdf ||
1824 devid != amd_iommu_alias_table[devid])
1827 iommu = amd_iommu_rlookup_table[devid];
1831 old_domain = domain_for_device(devid);
1835 attach_device(iommu, domain, devid);
1837 iommu_completion_wait(iommu);
1842 static int amd_iommu_map_range(struct iommu_domain *dom,
1843 unsigned long iova, phys_addr_t paddr,
1844 size_t size, int iommu_prot)
1846 struct protection_domain *domain = dom->priv;
1847 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1851 if (iommu_prot & IOMMU_READ)
1852 prot |= IOMMU_PROT_IR;
1853 if (iommu_prot & IOMMU_WRITE)
1854 prot |= IOMMU_PROT_IW;
1859 for (i = 0; i < npages; ++i) {
1860 ret = iommu_map_page(domain, iova, paddr, prot);
1871 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1872 unsigned long iova, size_t size)
1875 struct protection_domain *domain = dom->priv;
1876 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1880 for (i = 0; i < npages; ++i) {
1881 iommu_unmap_page(domain, iova);
1885 iommu_flush_domain(domain->id);
1888 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1891 struct protection_domain *domain = dom->priv;
1892 unsigned long offset = iova & ~PAGE_MASK;
1896 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1898 if (!IOMMU_PTE_PRESENT(*pte))
1901 pte = IOMMU_PTE_PAGE(*pte);
1902 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1904 if (!IOMMU_PTE_PRESENT(*pte))
1907 pte = IOMMU_PTE_PAGE(*pte);
1908 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1910 if (!IOMMU_PTE_PRESENT(*pte))
1913 paddr = *pte & IOMMU_PAGE_MASK;
1919 static struct iommu_ops amd_iommu_ops = {
1920 .domain_init = amd_iommu_domain_init,
1921 .domain_destroy = amd_iommu_domain_destroy,
1922 .attach_dev = amd_iommu_attach_device,
1923 .detach_dev = amd_iommu_detach_device,
1924 .map = amd_iommu_map_range,
1925 .unmap = amd_iommu_unmap_range,
1926 .iova_to_phys = amd_iommu_iova_to_phys,