2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
70 DECLARE_STATS_COUNTER(cnt_map_sg);
72 static struct dentry *stats_dir;
73 static struct dentry *de_isolate;
74 static struct dentry *de_fflush;
76 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
78 if (stats_dir == NULL)
81 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
85 static void amd_iommu_stats_init(void)
87 stats_dir = debugfs_create_dir("amd-iommu", NULL);
88 if (stats_dir == NULL)
91 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
92 (u32 *)&amd_iommu_isolate);
94 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
95 (u32 *)&amd_iommu_unmap_flush);
97 amd_iommu_stats_add(&compl_wait);
98 amd_iommu_stats_add(&cnt_map_single);
99 amd_iommu_stats_add(&cnt_unmap_single);
100 amd_iommu_stats_add(&cnt_map_sg);
105 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
106 static int iommu_has_npcache(struct amd_iommu *iommu)
108 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
111 /****************************************************************************
113 * Interrupt handling functions
115 ****************************************************************************/
117 static void iommu_print_event(void *__evt)
120 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
121 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
122 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
123 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
124 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
126 printk(KERN_ERR "AMD IOMMU: Event logged [");
129 case EVENT_TYPE_ILL_DEV:
130 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
131 "address=0x%016llx flags=0x%04x]\n",
132 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
135 case EVENT_TYPE_IO_FAULT:
136 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
137 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
138 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
139 domid, address, flags);
141 case EVENT_TYPE_DEV_TAB_ERR:
142 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
143 "address=0x%016llx flags=0x%04x]\n",
144 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
147 case EVENT_TYPE_PAGE_TAB_ERR:
148 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
149 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
150 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
151 domid, address, flags);
153 case EVENT_TYPE_ILL_CMD:
154 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
156 case EVENT_TYPE_CMD_HARD_ERR:
157 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
158 "flags=0x%04x]\n", address, flags);
160 case EVENT_TYPE_IOTLB_INV_TO:
161 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
162 "address=0x%016llx]\n",
163 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
166 case EVENT_TYPE_INV_DEV_REQ:
167 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
168 "address=0x%016llx flags=0x%04x]\n",
169 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
173 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
177 static void iommu_poll_events(struct amd_iommu *iommu)
182 spin_lock_irqsave(&iommu->lock, flags);
184 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
185 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
187 while (head != tail) {
188 iommu_print_event(iommu->evt_buf + head);
189 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
192 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
194 spin_unlock_irqrestore(&iommu->lock, flags);
197 irqreturn_t amd_iommu_int_handler(int irq, void *data)
199 struct amd_iommu *iommu;
201 list_for_each_entry(iommu, &amd_iommu_list, list)
202 iommu_poll_events(iommu);
207 /****************************************************************************
209 * IOMMU command queuing functions
211 ****************************************************************************/
214 * Writes the command to the IOMMUs command buffer and informs the
215 * hardware about the new command. Must be called with iommu->lock held.
217 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
222 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
223 target = iommu->cmd_buf + tail;
224 memcpy_toio(target, cmd, sizeof(*cmd));
225 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
226 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
229 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
235 * General queuing function for commands. Takes iommu->lock and calls
236 * __iommu_queue_command().
238 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
243 spin_lock_irqsave(&iommu->lock, flags);
244 ret = __iommu_queue_command(iommu, cmd);
246 iommu->need_sync = true;
247 spin_unlock_irqrestore(&iommu->lock, flags);
253 * This function waits until an IOMMU has completed a completion
256 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
262 INC_STATS_COUNTER(compl_wait);
264 while (!ready && (i < EXIT_LOOP_COUNT)) {
266 /* wait for the bit to become one */
267 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
268 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
271 /* set bit back to zero */
272 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
273 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
275 if (unlikely(i == EXIT_LOOP_COUNT))
276 panic("AMD IOMMU: Completion wait loop failed\n");
280 * This function queues a completion wait command into the command
283 static int __iommu_completion_wait(struct amd_iommu *iommu)
285 struct iommu_cmd cmd;
287 memset(&cmd, 0, sizeof(cmd));
288 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
289 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
291 return __iommu_queue_command(iommu, &cmd);
295 * This function is called whenever we need to ensure that the IOMMU has
296 * completed execution of all commands we sent. It sends a
297 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
298 * us about that by writing a value to a physical address we pass with
301 static int iommu_completion_wait(struct amd_iommu *iommu)
306 spin_lock_irqsave(&iommu->lock, flags);
308 if (!iommu->need_sync)
311 ret = __iommu_completion_wait(iommu);
313 iommu->need_sync = false;
318 __iommu_wait_for_completion(iommu);
321 spin_unlock_irqrestore(&iommu->lock, flags);
327 * Command send function for invalidating a device table entry
329 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
331 struct iommu_cmd cmd;
334 BUG_ON(iommu == NULL);
336 memset(&cmd, 0, sizeof(cmd));
337 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
340 ret = iommu_queue_command(iommu, &cmd);
345 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
346 u16 domid, int pde, int s)
348 memset(cmd, 0, sizeof(*cmd));
349 address &= PAGE_MASK;
350 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
351 cmd->data[1] |= domid;
352 cmd->data[2] = lower_32_bits(address);
353 cmd->data[3] = upper_32_bits(address);
354 if (s) /* size bit - we flush more than one 4kb page */
355 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
356 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
357 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
361 * Generic command send function for invalidaing TLB entries
363 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
364 u64 address, u16 domid, int pde, int s)
366 struct iommu_cmd cmd;
369 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
371 ret = iommu_queue_command(iommu, &cmd);
377 * TLB invalidation function which is called from the mapping functions.
378 * It invalidates a single PTE if the range to flush is within a single
379 * page. Otherwise it flushes the whole TLB of the IOMMU.
381 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
382 u64 address, size_t size)
385 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
387 address &= PAGE_MASK;
391 * If we have to flush more than one page, flush all
392 * TLB entries for this domain
394 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
398 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
403 /* Flush the whole IO/TLB for a given protection domain */
404 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
406 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
408 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
411 #ifdef CONFIG_IOMMU_API
413 * This function is used to flush the IO/TLB for a given protection domain
414 * on every IOMMU in the system
416 static void iommu_flush_domain(u16 domid)
419 struct amd_iommu *iommu;
420 struct iommu_cmd cmd;
422 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
425 list_for_each_entry(iommu, &amd_iommu_list, list) {
426 spin_lock_irqsave(&iommu->lock, flags);
427 __iommu_queue_command(iommu, &cmd);
428 __iommu_completion_wait(iommu);
429 __iommu_wait_for_completion(iommu);
430 spin_unlock_irqrestore(&iommu->lock, flags);
435 /****************************************************************************
437 * The functions below are used the create the page table mappings for
438 * unity mapped regions.
440 ****************************************************************************/
443 * Generic mapping functions. It maps a physical address into a DMA
444 * address space. It allocates the page table pages if necessary.
445 * In the future it can be extended to a generic mapping function
446 * supporting all features of AMD IOMMU page tables like level skipping
447 * and full 64 bit address spaces.
449 static int iommu_map_page(struct protection_domain *dom,
450 unsigned long bus_addr,
451 unsigned long phys_addr,
454 u64 __pte, *pte, *page;
456 bus_addr = PAGE_ALIGN(bus_addr);
457 phys_addr = PAGE_ALIGN(phys_addr);
459 /* only support 512GB address spaces for now */
460 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
463 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
465 if (!IOMMU_PTE_PRESENT(*pte)) {
466 page = (u64 *)get_zeroed_page(GFP_KERNEL);
469 *pte = IOMMU_L2_PDE(virt_to_phys(page));
472 pte = IOMMU_PTE_PAGE(*pte);
473 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
475 if (!IOMMU_PTE_PRESENT(*pte)) {
476 page = (u64 *)get_zeroed_page(GFP_KERNEL);
479 *pte = IOMMU_L1_PDE(virt_to_phys(page));
482 pte = IOMMU_PTE_PAGE(*pte);
483 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
485 if (IOMMU_PTE_PRESENT(*pte))
488 __pte = phys_addr | IOMMU_PTE_P;
489 if (prot & IOMMU_PROT_IR)
490 __pte |= IOMMU_PTE_IR;
491 if (prot & IOMMU_PROT_IW)
492 __pte |= IOMMU_PTE_IW;
499 #ifdef CONFIG_IOMMU_API
500 static void iommu_unmap_page(struct protection_domain *dom,
501 unsigned long bus_addr)
505 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
507 if (!IOMMU_PTE_PRESENT(*pte))
510 pte = IOMMU_PTE_PAGE(*pte);
511 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
513 if (!IOMMU_PTE_PRESENT(*pte))
516 pte = IOMMU_PTE_PAGE(*pte);
517 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
524 * This function checks if a specific unity mapping entry is needed for
525 * this specific IOMMU.
527 static int iommu_for_unity_map(struct amd_iommu *iommu,
528 struct unity_map_entry *entry)
532 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
533 bdf = amd_iommu_alias_table[i];
534 if (amd_iommu_rlookup_table[bdf] == iommu)
542 * Init the unity mappings for a specific IOMMU in the system
544 * Basically iterates over all unity mapping entries and applies them to
545 * the default domain DMA of that IOMMU if necessary.
547 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
549 struct unity_map_entry *entry;
552 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
553 if (!iommu_for_unity_map(iommu, entry))
555 ret = dma_ops_unity_map(iommu->default_dom, entry);
564 * This function actually applies the mapping to the page table of the
567 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
568 struct unity_map_entry *e)
573 for (addr = e->address_start; addr < e->address_end;
575 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
579 * if unity mapping is in aperture range mark the page
580 * as allocated in the aperture
582 if (addr < dma_dom->aperture_size)
583 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
590 * Inits the unity mappings required for a specific device
592 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
595 struct unity_map_entry *e;
598 list_for_each_entry(e, &amd_iommu_unity_map, list) {
599 if (!(devid >= e->devid_start && devid <= e->devid_end))
601 ret = dma_ops_unity_map(dma_dom, e);
609 /****************************************************************************
611 * The next functions belong to the address allocator for the dma_ops
612 * interface functions. They work like the allocators in the other IOMMU
613 * drivers. Its basically a bitmap which marks the allocated pages in
614 * the aperture. Maybe it could be enhanced in the future to a more
615 * efficient allocator.
617 ****************************************************************************/
620 * The address allocator core function.
622 * called with domain->lock held
624 static unsigned long dma_ops_alloc_addresses(struct device *dev,
625 struct dma_ops_domain *dom,
627 unsigned long align_mask,
631 unsigned long address;
632 unsigned long boundary_size;
634 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
635 PAGE_SIZE) >> PAGE_SHIFT;
636 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
637 dma_mask >> PAGE_SHIFT);
639 if (dom->next_bit >= limit) {
641 dom->need_flush = true;
644 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
645 0 , boundary_size, align_mask);
647 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
648 0, boundary_size, align_mask);
649 dom->need_flush = true;
652 if (likely(address != -1)) {
653 dom->next_bit = address + pages;
654 address <<= PAGE_SHIFT;
656 address = bad_dma_address;
658 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
664 * The address free function.
666 * called with domain->lock held
668 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
669 unsigned long address,
672 address >>= PAGE_SHIFT;
673 iommu_area_free(dom->bitmap, address, pages);
675 if (address >= dom->next_bit)
676 dom->need_flush = true;
679 /****************************************************************************
681 * The next functions belong to the domain allocation. A domain is
682 * allocated for every IOMMU as the default domain. If device isolation
683 * is enabled, every device get its own domain. The most important thing
684 * about domains is the page table mapping the DMA address space they
687 ****************************************************************************/
689 static u16 domain_id_alloc(void)
694 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
695 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
697 if (id > 0 && id < MAX_DOMAIN_ID)
698 __set_bit(id, amd_iommu_pd_alloc_bitmap);
701 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
706 #ifdef CONFIG_IOMMU_API
707 static void domain_id_free(int id)
711 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
712 if (id > 0 && id < MAX_DOMAIN_ID)
713 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
714 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
719 * Used to reserve address ranges in the aperture (e.g. for exclusion
722 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
723 unsigned long start_page,
726 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
728 if (start_page + pages > last_page)
729 pages = last_page - start_page;
731 iommu_area_reserve(dom->bitmap, start_page, pages);
734 static void free_pagetable(struct protection_domain *domain)
739 p1 = domain->pt_root;
744 for (i = 0; i < 512; ++i) {
745 if (!IOMMU_PTE_PRESENT(p1[i]))
748 p2 = IOMMU_PTE_PAGE(p1[i]);
749 for (j = 0; j < 512; ++j) {
750 if (!IOMMU_PTE_PRESENT(p2[j]))
752 p3 = IOMMU_PTE_PAGE(p2[j]);
753 free_page((unsigned long)p3);
756 free_page((unsigned long)p2);
759 free_page((unsigned long)p1);
761 domain->pt_root = NULL;
765 * Free a domain, only used if something went wrong in the
766 * allocation path and we need to free an already allocated page table
768 static void dma_ops_domain_free(struct dma_ops_domain *dom)
773 free_pagetable(&dom->domain);
775 kfree(dom->pte_pages);
783 * Allocates a new protection domain usable for the dma_ops functions.
784 * It also intializes the page table and the address allocator data
785 * structures required for the dma_ops interface
787 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
790 struct dma_ops_domain *dma_dom;
791 unsigned i, num_pte_pages;
796 * Currently the DMA aperture must be between 32 MB and 1GB in size
798 if ((order < 25) || (order > 30))
801 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
805 spin_lock_init(&dma_dom->domain.lock);
807 dma_dom->domain.id = domain_id_alloc();
808 if (dma_dom->domain.id == 0)
810 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
811 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
812 dma_dom->domain.flags = PD_DMA_OPS_MASK;
813 dma_dom->domain.priv = dma_dom;
814 if (!dma_dom->domain.pt_root)
816 dma_dom->aperture_size = (1ULL << order);
817 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
819 if (!dma_dom->bitmap)
822 * mark the first page as allocated so we never return 0 as
823 * a valid dma-address. So we can use 0 as error value
825 dma_dom->bitmap[0] = 1;
826 dma_dom->next_bit = 0;
828 dma_dom->need_flush = false;
829 dma_dom->target_dev = 0xffff;
831 /* Intialize the exclusion range if necessary */
832 if (iommu->exclusion_start &&
833 iommu->exclusion_start < dma_dom->aperture_size) {
834 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
835 int pages = iommu_num_pages(iommu->exclusion_start,
836 iommu->exclusion_length,
838 dma_ops_reserve_addresses(dma_dom, startpage, pages);
842 * At the last step, build the page tables so we don't need to
843 * allocate page table pages in the dma_ops mapping/unmapping
846 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
847 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
849 if (!dma_dom->pte_pages)
852 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
856 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
858 for (i = 0; i < num_pte_pages; ++i) {
859 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
860 if (!dma_dom->pte_pages[i])
862 address = virt_to_phys(dma_dom->pte_pages[i]);
863 l2_pde[i] = IOMMU_L1_PDE(address);
869 dma_ops_domain_free(dma_dom);
875 * little helper function to check whether a given protection domain is a
878 static bool dma_ops_domain(struct protection_domain *domain)
880 return domain->flags & PD_DMA_OPS_MASK;
884 * Find out the protection domain structure for a given PCI device. This
885 * will give us the pointer to the page table root for example.
887 static struct protection_domain *domain_for_device(u16 devid)
889 struct protection_domain *dom;
892 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
893 dom = amd_iommu_pd_table[devid];
894 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
900 * If a device is not yet associated with a domain, this function does
901 * assigns it visible for the hardware
903 static void attach_device(struct amd_iommu *iommu,
904 struct protection_domain *domain,
908 u64 pte_root = virt_to_phys(domain->pt_root);
910 domain->dev_cnt += 1;
912 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
913 << DEV_ENTRY_MODE_SHIFT;
914 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
916 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
917 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
918 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
919 amd_iommu_dev_table[devid].data[2] = domain->id;
921 amd_iommu_pd_table[devid] = domain;
922 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
924 iommu_queue_inv_dev_entry(iommu, devid);
928 * Removes a device from a protection domain (unlocked)
930 static void __detach_device(struct protection_domain *domain, u16 devid)
934 spin_lock(&domain->lock);
936 /* remove domain from the lookup table */
937 amd_iommu_pd_table[devid] = NULL;
939 /* remove entry from the device table seen by the hardware */
940 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
941 amd_iommu_dev_table[devid].data[1] = 0;
942 amd_iommu_dev_table[devid].data[2] = 0;
944 /* decrease reference counter */
945 domain->dev_cnt -= 1;
948 spin_unlock(&domain->lock);
952 * Removes a device from a protection domain (with devtable_lock held)
954 static void detach_device(struct protection_domain *domain, u16 devid)
958 /* lock device table */
959 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
960 __detach_device(domain, devid);
961 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
964 static int device_change_notifier(struct notifier_block *nb,
965 unsigned long action, void *data)
967 struct device *dev = data;
968 struct pci_dev *pdev = to_pci_dev(dev);
969 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
970 struct protection_domain *domain;
971 struct dma_ops_domain *dma_domain;
972 struct amd_iommu *iommu;
973 int order = amd_iommu_aperture_order;
976 if (devid > amd_iommu_last_bdf)
979 devid = amd_iommu_alias_table[devid];
981 iommu = amd_iommu_rlookup_table[devid];
985 domain = domain_for_device(devid);
987 if (domain && !dma_ops_domain(domain))
988 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
989 "to a non-dma-ops domain\n", dev_name(dev));
992 case BUS_NOTIFY_BOUND_DRIVER:
995 dma_domain = find_protection_domain(devid);
997 dma_domain = iommu->default_dom;
998 attach_device(iommu, &dma_domain->domain, devid);
999 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1000 "device %s\n", dma_domain->domain.id, dev_name(dev));
1002 case BUS_NOTIFY_UNBIND_DRIVER:
1005 detach_device(domain, devid);
1007 case BUS_NOTIFY_ADD_DEVICE:
1008 /* allocate a protection domain if a device is added */
1009 dma_domain = find_protection_domain(devid);
1012 dma_domain = dma_ops_domain_alloc(iommu, order);
1015 dma_domain->target_dev = devid;
1017 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1018 list_add_tail(&dma_domain->list, &iommu_pd_list);
1019 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1026 iommu_queue_inv_dev_entry(iommu, devid);
1027 iommu_completion_wait(iommu);
1033 struct notifier_block device_nb = {
1034 .notifier_call = device_change_notifier,
1037 /*****************************************************************************
1039 * The next functions belong to the dma_ops mapping/unmapping code.
1041 *****************************************************************************/
1044 * This function checks if the driver got a valid device from the caller to
1045 * avoid dereferencing invalid pointers.
1047 static bool check_device(struct device *dev)
1049 if (!dev || !dev->dma_mask)
1056 * In this function the list of preallocated protection domains is traversed to
1057 * find the domain for a specific device
1059 static struct dma_ops_domain *find_protection_domain(u16 devid)
1061 struct dma_ops_domain *entry, *ret = NULL;
1062 unsigned long flags;
1064 if (list_empty(&iommu_pd_list))
1067 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1069 list_for_each_entry(entry, &iommu_pd_list, list) {
1070 if (entry->target_dev == devid) {
1076 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1082 * In the dma_ops path we only have the struct device. This function
1083 * finds the corresponding IOMMU, the protection domain and the
1084 * requestor id for a given device.
1085 * If the device is not yet associated with a domain this is also done
1088 static int get_device_resources(struct device *dev,
1089 struct amd_iommu **iommu,
1090 struct protection_domain **domain,
1093 struct dma_ops_domain *dma_dom;
1094 struct pci_dev *pcidev;
1101 if (dev->bus != &pci_bus_type)
1104 pcidev = to_pci_dev(dev);
1105 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1107 /* device not translated by any IOMMU in the system? */
1108 if (_bdf > amd_iommu_last_bdf)
1111 *bdf = amd_iommu_alias_table[_bdf];
1113 *iommu = amd_iommu_rlookup_table[*bdf];
1116 *domain = domain_for_device(*bdf);
1117 if (*domain == NULL) {
1118 dma_dom = find_protection_domain(*bdf);
1120 dma_dom = (*iommu)->default_dom;
1121 *domain = &dma_dom->domain;
1122 attach_device(*iommu, *domain, *bdf);
1123 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1124 "device %s\n", (*domain)->id, dev_name(dev));
1127 if (domain_for_device(_bdf) == NULL)
1128 attach_device(*iommu, *domain, _bdf);
1134 * This is the generic map function. It maps one 4kb page at paddr to
1135 * the given address in the DMA address space for the domain.
1137 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1138 struct dma_ops_domain *dom,
1139 unsigned long address,
1145 WARN_ON(address > dom->aperture_size);
1149 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1150 pte += IOMMU_PTE_L0_INDEX(address);
1152 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1154 if (direction == DMA_TO_DEVICE)
1155 __pte |= IOMMU_PTE_IR;
1156 else if (direction == DMA_FROM_DEVICE)
1157 __pte |= IOMMU_PTE_IW;
1158 else if (direction == DMA_BIDIRECTIONAL)
1159 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1165 return (dma_addr_t)address;
1169 * The generic unmapping function for on page in the DMA address space.
1171 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1172 struct dma_ops_domain *dom,
1173 unsigned long address)
1177 if (address >= dom->aperture_size)
1180 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1182 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1183 pte += IOMMU_PTE_L0_INDEX(address);
1191 * This function contains common code for mapping of a physically
1192 * contiguous memory region into DMA address space. It is used by all
1193 * mapping functions provided with this IOMMU driver.
1194 * Must be called with the domain lock held.
1196 static dma_addr_t __map_single(struct device *dev,
1197 struct amd_iommu *iommu,
1198 struct dma_ops_domain *dma_dom,
1205 dma_addr_t offset = paddr & ~PAGE_MASK;
1206 dma_addr_t address, start;
1208 unsigned long align_mask = 0;
1211 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1215 align_mask = (1UL << get_order(size)) - 1;
1217 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1219 if (unlikely(address == bad_dma_address))
1223 for (i = 0; i < pages; ++i) {
1224 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1230 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1231 iommu_flush_tlb(iommu, dma_dom->domain.id);
1232 dma_dom->need_flush = false;
1233 } else if (unlikely(iommu_has_npcache(iommu)))
1234 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1241 * Does the reverse of the __map_single function. Must be called with
1242 * the domain lock held too
1244 static void __unmap_single(struct amd_iommu *iommu,
1245 struct dma_ops_domain *dma_dom,
1246 dma_addr_t dma_addr,
1250 dma_addr_t i, start;
1253 if ((dma_addr == bad_dma_address) ||
1254 (dma_addr + size > dma_dom->aperture_size))
1257 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1258 dma_addr &= PAGE_MASK;
1261 for (i = 0; i < pages; ++i) {
1262 dma_ops_domain_unmap(iommu, dma_dom, start);
1266 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1268 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1269 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1270 dma_dom->need_flush = false;
1275 * The exported map_single function for dma_ops.
1277 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1278 size_t size, int dir)
1280 unsigned long flags;
1281 struct amd_iommu *iommu;
1282 struct protection_domain *domain;
1287 INC_STATS_COUNTER(cnt_map_single);
1289 if (!check_device(dev))
1290 return bad_dma_address;
1292 dma_mask = *dev->dma_mask;
1294 get_device_resources(dev, &iommu, &domain, &devid);
1296 if (iommu == NULL || domain == NULL)
1297 /* device not handled by any AMD IOMMU */
1298 return (dma_addr_t)paddr;
1300 if (!dma_ops_domain(domain))
1301 return bad_dma_address;
1303 spin_lock_irqsave(&domain->lock, flags);
1304 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1306 if (addr == bad_dma_address)
1309 iommu_completion_wait(iommu);
1312 spin_unlock_irqrestore(&domain->lock, flags);
1318 * The exported unmap_single function for dma_ops.
1320 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1321 size_t size, int dir)
1323 unsigned long flags;
1324 struct amd_iommu *iommu;
1325 struct protection_domain *domain;
1328 INC_STATS_COUNTER(cnt_unmap_single);
1330 if (!check_device(dev) ||
1331 !get_device_resources(dev, &iommu, &domain, &devid))
1332 /* device not handled by any AMD IOMMU */
1335 if (!dma_ops_domain(domain))
1338 spin_lock_irqsave(&domain->lock, flags);
1340 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1342 iommu_completion_wait(iommu);
1344 spin_unlock_irqrestore(&domain->lock, flags);
1348 * This is a special map_sg function which is used if we should map a
1349 * device which is not handled by an AMD IOMMU in the system.
1351 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1352 int nelems, int dir)
1354 struct scatterlist *s;
1357 for_each_sg(sglist, s, nelems, i) {
1358 s->dma_address = (dma_addr_t)sg_phys(s);
1359 s->dma_length = s->length;
1366 * The exported map_sg function for dma_ops (handles scatter-gather
1369 static int map_sg(struct device *dev, struct scatterlist *sglist,
1370 int nelems, int dir)
1372 unsigned long flags;
1373 struct amd_iommu *iommu;
1374 struct protection_domain *domain;
1377 struct scatterlist *s;
1379 int mapped_elems = 0;
1382 INC_STATS_COUNTER(cnt_map_sg);
1384 if (!check_device(dev))
1387 dma_mask = *dev->dma_mask;
1389 get_device_resources(dev, &iommu, &domain, &devid);
1391 if (!iommu || !domain)
1392 return map_sg_no_iommu(dev, sglist, nelems, dir);
1394 if (!dma_ops_domain(domain))
1397 spin_lock_irqsave(&domain->lock, flags);
1399 for_each_sg(sglist, s, nelems, i) {
1402 s->dma_address = __map_single(dev, iommu, domain->priv,
1403 paddr, s->length, dir, false,
1406 if (s->dma_address) {
1407 s->dma_length = s->length;
1413 iommu_completion_wait(iommu);
1416 spin_unlock_irqrestore(&domain->lock, flags);
1418 return mapped_elems;
1420 for_each_sg(sglist, s, mapped_elems, i) {
1422 __unmap_single(iommu, domain->priv, s->dma_address,
1423 s->dma_length, dir);
1424 s->dma_address = s->dma_length = 0;
1433 * The exported map_sg function for dma_ops (handles scatter-gather
1436 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1437 int nelems, int dir)
1439 unsigned long flags;
1440 struct amd_iommu *iommu;
1441 struct protection_domain *domain;
1442 struct scatterlist *s;
1446 if (!check_device(dev) ||
1447 !get_device_resources(dev, &iommu, &domain, &devid))
1450 if (!dma_ops_domain(domain))
1453 spin_lock_irqsave(&domain->lock, flags);
1455 for_each_sg(sglist, s, nelems, i) {
1456 __unmap_single(iommu, domain->priv, s->dma_address,
1457 s->dma_length, dir);
1458 s->dma_address = s->dma_length = 0;
1461 iommu_completion_wait(iommu);
1463 spin_unlock_irqrestore(&domain->lock, flags);
1467 * The exported alloc_coherent function for dma_ops.
1469 static void *alloc_coherent(struct device *dev, size_t size,
1470 dma_addr_t *dma_addr, gfp_t flag)
1472 unsigned long flags;
1474 struct amd_iommu *iommu;
1475 struct protection_domain *domain;
1478 u64 dma_mask = dev->coherent_dma_mask;
1480 if (!check_device(dev))
1483 if (!get_device_resources(dev, &iommu, &domain, &devid))
1484 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1487 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1491 paddr = virt_to_phys(virt_addr);
1493 if (!iommu || !domain) {
1494 *dma_addr = (dma_addr_t)paddr;
1498 if (!dma_ops_domain(domain))
1502 dma_mask = *dev->dma_mask;
1504 spin_lock_irqsave(&domain->lock, flags);
1506 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1507 size, DMA_BIDIRECTIONAL, true, dma_mask);
1509 if (*dma_addr == bad_dma_address)
1512 iommu_completion_wait(iommu);
1514 spin_unlock_irqrestore(&domain->lock, flags);
1520 free_pages((unsigned long)virt_addr, get_order(size));
1526 * The exported free_coherent function for dma_ops.
1528 static void free_coherent(struct device *dev, size_t size,
1529 void *virt_addr, dma_addr_t dma_addr)
1531 unsigned long flags;
1532 struct amd_iommu *iommu;
1533 struct protection_domain *domain;
1536 if (!check_device(dev))
1539 get_device_resources(dev, &iommu, &domain, &devid);
1541 if (!iommu || !domain)
1544 if (!dma_ops_domain(domain))
1547 spin_lock_irqsave(&domain->lock, flags);
1549 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1551 iommu_completion_wait(iommu);
1553 spin_unlock_irqrestore(&domain->lock, flags);
1556 free_pages((unsigned long)virt_addr, get_order(size));
1560 * This function is called by the DMA layer to find out if we can handle a
1561 * particular device. It is part of the dma_ops.
1563 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1566 struct pci_dev *pcidev;
1568 /* No device or no PCI device */
1569 if (!dev || dev->bus != &pci_bus_type)
1572 pcidev = to_pci_dev(dev);
1574 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1576 /* Out of our scope? */
1577 if (bdf > amd_iommu_last_bdf)
1584 * The function for pre-allocating protection domains.
1586 * If the driver core informs the DMA layer if a driver grabs a device
1587 * we don't need to preallocate the protection domains anymore.
1588 * For now we have to.
1590 void prealloc_protection_domains(void)
1592 struct pci_dev *dev = NULL;
1593 struct dma_ops_domain *dma_dom;
1594 struct amd_iommu *iommu;
1595 int order = amd_iommu_aperture_order;
1598 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1599 devid = calc_devid(dev->bus->number, dev->devfn);
1600 if (devid > amd_iommu_last_bdf)
1602 devid = amd_iommu_alias_table[devid];
1603 if (domain_for_device(devid))
1605 iommu = amd_iommu_rlookup_table[devid];
1608 dma_dom = dma_ops_domain_alloc(iommu, order);
1611 init_unity_mappings_for_device(dma_dom, devid);
1612 dma_dom->target_dev = devid;
1614 list_add_tail(&dma_dom->list, &iommu_pd_list);
1618 static struct dma_mapping_ops amd_iommu_dma_ops = {
1619 .alloc_coherent = alloc_coherent,
1620 .free_coherent = free_coherent,
1621 .map_single = map_single,
1622 .unmap_single = unmap_single,
1624 .unmap_sg = unmap_sg,
1625 .dma_supported = amd_iommu_dma_supported,
1629 * The function which clues the AMD IOMMU driver into dma_ops.
1631 int __init amd_iommu_init_dma_ops(void)
1633 struct amd_iommu *iommu;
1634 int order = amd_iommu_aperture_order;
1638 * first allocate a default protection domain for every IOMMU we
1639 * found in the system. Devices not assigned to any other
1640 * protection domain will be assigned to the default one.
1642 list_for_each_entry(iommu, &amd_iommu_list, list) {
1643 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1644 if (iommu->default_dom == NULL)
1646 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1647 ret = iommu_init_unity_mappings(iommu);
1653 * If device isolation is enabled, pre-allocate the protection
1654 * domains for each device.
1656 if (amd_iommu_isolate)
1657 prealloc_protection_domains();
1661 bad_dma_address = 0;
1662 #ifdef CONFIG_GART_IOMMU
1663 gart_iommu_aperture_disabled = 1;
1664 gart_iommu_aperture = 0;
1667 /* Make the driver finally visible to the drivers */
1668 dma_ops = &amd_iommu_dma_ops;
1670 #ifdef CONFIG_IOMMU_API
1671 register_iommu(&amd_iommu_ops);
1674 bus_register_notifier(&pci_bus_type, &device_nb);
1676 amd_iommu_stats_init();
1682 list_for_each_entry(iommu, &amd_iommu_list, list) {
1683 if (iommu->default_dom)
1684 dma_ops_domain_free(iommu->default_dom);
1690 /*****************************************************************************
1692 * The following functions belong to the exported interface of AMD IOMMU
1694 * This interface allows access to lower level functions of the IOMMU
1695 * like protection domain handling and assignement of devices to domains
1696 * which is not possible with the dma_ops interface.
1698 *****************************************************************************/
1700 #ifdef CONFIG_IOMMU_API
1702 static void cleanup_domain(struct protection_domain *domain)
1704 unsigned long flags;
1707 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1709 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1710 if (amd_iommu_pd_table[devid] == domain)
1711 __detach_device(domain, devid);
1713 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1716 static int amd_iommu_domain_init(struct iommu_domain *dom)
1718 struct protection_domain *domain;
1720 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1724 spin_lock_init(&domain->lock);
1725 domain->mode = PAGE_MODE_3_LEVEL;
1726 domain->id = domain_id_alloc();
1729 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1730 if (!domain->pt_root)
1743 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1745 struct protection_domain *domain = dom->priv;
1750 if (domain->dev_cnt > 0)
1751 cleanup_domain(domain);
1753 BUG_ON(domain->dev_cnt != 0);
1755 free_pagetable(domain);
1757 domain_id_free(domain->id);
1764 static void amd_iommu_detach_device(struct iommu_domain *dom,
1767 struct protection_domain *domain = dom->priv;
1768 struct amd_iommu *iommu;
1769 struct pci_dev *pdev;
1772 if (dev->bus != &pci_bus_type)
1775 pdev = to_pci_dev(dev);
1777 devid = calc_devid(pdev->bus->number, pdev->devfn);
1780 detach_device(domain, devid);
1782 iommu = amd_iommu_rlookup_table[devid];
1786 iommu_queue_inv_dev_entry(iommu, devid);
1787 iommu_completion_wait(iommu);
1790 static int amd_iommu_attach_device(struct iommu_domain *dom,
1793 struct protection_domain *domain = dom->priv;
1794 struct protection_domain *old_domain;
1795 struct amd_iommu *iommu;
1796 struct pci_dev *pdev;
1799 if (dev->bus != &pci_bus_type)
1802 pdev = to_pci_dev(dev);
1804 devid = calc_devid(pdev->bus->number, pdev->devfn);
1806 if (devid >= amd_iommu_last_bdf ||
1807 devid != amd_iommu_alias_table[devid])
1810 iommu = amd_iommu_rlookup_table[devid];
1814 old_domain = domain_for_device(devid);
1818 attach_device(iommu, domain, devid);
1820 iommu_completion_wait(iommu);
1825 static int amd_iommu_map_range(struct iommu_domain *dom,
1826 unsigned long iova, phys_addr_t paddr,
1827 size_t size, int iommu_prot)
1829 struct protection_domain *domain = dom->priv;
1830 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1834 if (iommu_prot & IOMMU_READ)
1835 prot |= IOMMU_PROT_IR;
1836 if (iommu_prot & IOMMU_WRITE)
1837 prot |= IOMMU_PROT_IW;
1842 for (i = 0; i < npages; ++i) {
1843 ret = iommu_map_page(domain, iova, paddr, prot);
1854 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1855 unsigned long iova, size_t size)
1858 struct protection_domain *domain = dom->priv;
1859 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1863 for (i = 0; i < npages; ++i) {
1864 iommu_unmap_page(domain, iova);
1868 iommu_flush_domain(domain->id);
1871 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1874 struct protection_domain *domain = dom->priv;
1875 unsigned long offset = iova & ~PAGE_MASK;
1879 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1881 if (!IOMMU_PTE_PRESENT(*pte))
1884 pte = IOMMU_PTE_PAGE(*pte);
1885 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1887 if (!IOMMU_PTE_PRESENT(*pte))
1890 pte = IOMMU_PTE_PAGE(*pte);
1891 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1893 if (!IOMMU_PTE_PRESENT(*pte))
1896 paddr = *pte & IOMMU_PAGE_MASK;
1902 static struct iommu_ops amd_iommu_ops = {
1903 .domain_init = amd_iommu_domain_init,
1904 .domain_destroy = amd_iommu_domain_destroy,
1905 .attach_dev = amd_iommu_attach_device,
1906 .detach_dev = amd_iommu_detach_device,
1907 .map = amd_iommu_map_range,
1908 .unmap = amd_iommu_unmap_range,
1909 .iova_to_phys = amd_iommu_iova_to_phys,