2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_event.h>
39 #include <asm/x86_init.h>
40 #include <asm/pgalloc.h>
41 #include <asm/atomic.h>
42 #include <asm/mpspec.h>
43 #include <asm/i8253.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
53 #include <asm/kvm_para.h>
56 unsigned int num_processors;
58 unsigned disabled_cpus __cpuinitdata;
60 /* Processor that is doing the boot up */
61 unsigned int boot_cpu_physical_apicid = -1U;
64 * The highest APIC ID seen during enumeration.
66 unsigned int max_physical_apicid;
69 * Bitmask of physically existing CPUs:
71 physid_mask_t phys_cpu_present_map;
74 * Map cpu index to physical APIC ID
76 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
77 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
83 * Knob to control our willingness to enable the local APIC.
87 static int force_enable_local_apic;
89 * APIC command line parameters
91 static int __init parse_lapic(char *arg)
93 force_enable_local_apic = 1;
96 early_param("lapic", parse_lapic);
97 /* Local APIC was disabled by the BIOS and enabled by the kernel */
98 static int enabled_via_apicbase;
101 * Handle interrupt mode configuration register (IMCR).
102 * This register controls whether the interrupt signals
103 * that reach the BSP come from the master PIC or from the
104 * local APIC. Before entering Symmetric I/O Mode, either
105 * the BIOS or the operating system must switch out of
106 * PIC Mode by changing the IMCR.
108 static inline void imcr_pic_to_apic(void)
110 /* select IMCR register */
112 /* NMI and 8259 INTR go through APIC */
116 static inline void imcr_apic_to_pic(void)
118 /* select IMCR register */
120 /* NMI and 8259 INTR go directly to BSP */
126 static int apic_calibrate_pmtmr __initdata;
127 static __init int setup_apicpmtimer(char *s)
129 apic_calibrate_pmtmr = 1;
133 __setup("apicpmtimer", setup_apicpmtimer);
137 #ifdef CONFIG_X86_X2APIC
138 /* x2apic enabled before OS handover */
139 static int x2apic_preenabled;
140 static __init int setup_nox2apic(char *str)
142 if (x2apic_enabled()) {
143 pr_warning("Bios already enabled x2apic, "
144 "can't enforce nox2apic");
148 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
151 early_param("nox2apic", setup_nox2apic);
154 unsigned long mp_lapic_addr;
156 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
157 static int disable_apic_timer __cpuinitdata;
158 /* Local APIC timer works in C2 */
159 int local_apic_timer_c2_ok;
160 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
162 int first_system_vector = 0xfe;
165 * Debug level, exported for io_apic.c
167 unsigned int apic_verbosity;
171 /* Have we found an MP table */
172 int smp_found_config;
174 static struct resource lapic_resource = {
175 .name = "Local APIC",
176 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
179 static unsigned int calibration_result;
181 static int lapic_next_event(unsigned long delta,
182 struct clock_event_device *evt);
183 static void lapic_timer_setup(enum clock_event_mode mode,
184 struct clock_event_device *evt);
185 static void lapic_timer_broadcast(const struct cpumask *mask);
186 static void apic_pm_activate(void);
189 * The local apic timer can be used for any function which is CPU local.
191 static struct clock_event_device lapic_clockevent = {
193 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
194 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
196 .set_mode = lapic_timer_setup,
197 .set_next_event = lapic_next_event,
198 .broadcast = lapic_timer_broadcast,
202 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
204 static unsigned long apic_phys;
207 * Get the LAPIC version
209 static inline int lapic_get_version(void)
211 return GET_APIC_VERSION(apic_read(APIC_LVR));
215 * Check, if the APIC is integrated or a separate chip
217 static inline int lapic_is_integrated(void)
222 return APIC_INTEGRATED(lapic_get_version());
227 * Check, whether this is a modern or a first generation APIC
229 static int modern_apic(void)
231 /* AMD systems use old APIC versions, so check the CPU */
232 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
233 boot_cpu_data.x86 >= 0xf)
235 return lapic_get_version() >= 0x14;
239 * right after this call apic become NOOP driven
240 * so apic->write/read doesn't do anything
242 void apic_disable(void)
244 pr_info("APIC: switched to apic NOOP\n");
248 void native_apic_wait_icr_idle(void)
250 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
254 u32 native_safe_apic_wait_icr_idle(void)
261 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
265 } while (timeout++ < 1000);
270 void native_apic_icr_write(u32 low, u32 id)
272 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
273 apic_write(APIC_ICR, low);
276 u64 native_apic_icr_read(void)
280 icr2 = apic_read(APIC_ICR2);
281 icr1 = apic_read(APIC_ICR);
283 return icr1 | ((u64)icr2 << 32);
287 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
289 void __cpuinit enable_NMI_through_LVT0(void)
293 /* unmask and set to NMI */
296 /* Level triggered for 82489DX (32bit mode) */
297 if (!lapic_is_integrated())
298 v |= APIC_LVT_LEVEL_TRIGGER;
300 apic_write(APIC_LVT0, v);
305 * get_physical_broadcast - Get number of physical broadcast IDs
307 int get_physical_broadcast(void)
309 return modern_apic() ? 0xff : 0xf;
314 * lapic_get_maxlvt - get the maximum number of local vector table entries
316 int lapic_get_maxlvt(void)
320 v = apic_read(APIC_LVR);
322 * - we always have APIC integrated on 64bit mode
323 * - 82489DXs do not report # of LVT entries
325 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
333 #define APIC_DIVISOR 16
336 * This function sets up the local APIC timer, with a timeout of
337 * 'clocks' APIC bus clock. During calibration we actually call
338 * this function twice on the boot CPU, once with a bogus timeout
339 * value, second time for real. The other (noncalibrating) CPUs
340 * call this function only once, with the real, calibrated value.
342 * We do reads before writes even if unnecessary, to get around the
343 * P5 APIC double write bug.
345 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
347 unsigned int lvtt_value, tmp_value;
349 lvtt_value = LOCAL_TIMER_VECTOR;
351 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
352 if (!lapic_is_integrated())
353 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
356 lvtt_value |= APIC_LVT_MASKED;
358 apic_write(APIC_LVTT, lvtt_value);
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
373 * Setup extended LVT, AMD specific
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 unsigned int rsvd; /* 0: uninitialized */
405 if (offset >= APIC_EILVT_NR_MAX)
408 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
411 !eilvt_entry_is_changeable(rsvd, new))
412 /* may not change if vectors are different */
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
421 * If mask=1, the LVT entry does not generate interrupts while mask=0
422 * enables the vector. See also the BKDGs.
425 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
427 unsigned long reg = APIC_EILVTn(offset);
428 unsigned int new, old, reserved;
430 new = (mask << 16) | (msg_type << 8) | vector;
431 old = apic_read(reg);
432 reserved = reserve_eilvt_offset(offset, new);
434 if (reserved != new) {
435 pr_err(FW_BUG "cpu %d, try to setup vector 0x%x, but "
436 "vector 0x%x was already reserved by another core, "
438 smp_processor_id(), new, reserved, reg, old);
442 if (!eilvt_entry_is_changeable(old, new)) {
443 pr_err(FW_BUG "cpu %d, try to setup vector 0x%x but "
444 "register already in use, APIC%lX=0x%x\n",
445 smp_processor_id(), new, reg, old);
449 apic_write(reg, new);
453 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
456 * Program the next event, relative to now
458 static int lapic_next_event(unsigned long delta,
459 struct clock_event_device *evt)
461 apic_write(APIC_TMICT, delta);
466 * Setup the lapic timer in periodic or oneshot mode
468 static void lapic_timer_setup(enum clock_event_mode mode,
469 struct clock_event_device *evt)
474 /* Lapic used as dummy for broadcast ? */
475 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
478 local_irq_save(flags);
481 case CLOCK_EVT_MODE_PERIODIC:
482 case CLOCK_EVT_MODE_ONESHOT:
483 __setup_APIC_LVTT(calibration_result,
484 mode != CLOCK_EVT_MODE_PERIODIC, 1);
486 case CLOCK_EVT_MODE_UNUSED:
487 case CLOCK_EVT_MODE_SHUTDOWN:
488 v = apic_read(APIC_LVTT);
489 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
490 apic_write(APIC_LVTT, v);
491 apic_write(APIC_TMICT, 0);
493 case CLOCK_EVT_MODE_RESUME:
494 /* Nothing to do here */
498 local_irq_restore(flags);
502 * Local APIC timer broadcast function
504 static void lapic_timer_broadcast(const struct cpumask *mask)
507 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
512 * Setup the local APIC timer for this CPU. Copy the initialized values
513 * of the boot CPU and register the clock event in the framework.
515 static void __cpuinit setup_APIC_timer(void)
517 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
519 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) {
520 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
521 /* Make LAPIC timer preferrable over percpu HPET */
522 lapic_clockevent.rating = 150;
525 memcpy(levt, &lapic_clockevent, sizeof(*levt));
526 levt->cpumask = cpumask_of(smp_processor_id());
528 clockevents_register_device(levt);
532 * In this functions we calibrate APIC bus clocks to the external timer.
534 * We want to do the calibration only once since we want to have local timer
535 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
538 * This was previously done by reading the PIT/HPET and waiting for a wrap
539 * around to find out, that a tick has elapsed. I have a box, where the PIT
540 * readout is broken, so it never gets out of the wait loop again. This was
541 * also reported by others.
543 * Monitoring the jiffies value is inaccurate and the clockevents
544 * infrastructure allows us to do a simple substitution of the interrupt
547 * The calibration routine also uses the pm_timer when possible, as the PIT
548 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
549 * back to normal later in the boot process).
552 #define LAPIC_CAL_LOOPS (HZ/10)
554 static __initdata int lapic_cal_loops = -1;
555 static __initdata long lapic_cal_t1, lapic_cal_t2;
556 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
557 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
558 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
561 * Temporary interrupt handler.
563 static void __init lapic_cal_handler(struct clock_event_device *dev)
565 unsigned long long tsc = 0;
566 long tapic = apic_read(APIC_TMCCT);
567 unsigned long pm = acpi_pm_read_early();
572 switch (lapic_cal_loops++) {
574 lapic_cal_t1 = tapic;
575 lapic_cal_tsc1 = tsc;
577 lapic_cal_j1 = jiffies;
580 case LAPIC_CAL_LOOPS:
581 lapic_cal_t2 = tapic;
582 lapic_cal_tsc2 = tsc;
583 if (pm < lapic_cal_pm1)
584 pm += ACPI_PM_OVRRUN;
586 lapic_cal_j2 = jiffies;
592 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
594 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
595 const long pm_thresh = pm_100ms / 100;
599 #ifndef CONFIG_X86_PM_TIMER
603 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
605 /* Check, if the PM timer is available */
609 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
611 if (deltapm > (pm_100ms - pm_thresh) &&
612 deltapm < (pm_100ms + pm_thresh)) {
613 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
617 res = (((u64)deltapm) * mult) >> 22;
618 do_div(res, 1000000);
619 pr_warning("APIC calibration not consistent "
620 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
622 /* Correct the lapic counter value */
623 res = (((u64)(*delta)) * pm_100ms);
624 do_div(res, deltapm);
625 pr_info("APIC delta adjusted to PM-Timer: "
626 "%lu (%ld)\n", (unsigned long)res, *delta);
629 /* Correct the tsc counter value */
631 res = (((u64)(*deltatsc)) * pm_100ms);
632 do_div(res, deltapm);
633 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
634 "PM-Timer: %lu (%ld)\n",
635 (unsigned long)res, *deltatsc);
636 *deltatsc = (long)res;
642 static int __init calibrate_APIC_clock(void)
644 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
645 void (*real_handler)(struct clock_event_device *dev);
646 unsigned long deltaj;
647 long delta, deltatsc;
648 int pm_referenced = 0;
652 /* Replace the global interrupt handler */
653 real_handler = global_clock_event->event_handler;
654 global_clock_event->event_handler = lapic_cal_handler;
657 * Setup the APIC counter to maximum. There is no way the lapic
658 * can underflow in the 100ms detection time frame
660 __setup_APIC_LVTT(0xffffffff, 0, 0);
662 /* Let the interrupts run */
665 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
670 /* Restore the real event handler */
671 global_clock_event->event_handler = real_handler;
673 /* Build delta t1-t2 as apic timer counts down */
674 delta = lapic_cal_t1 - lapic_cal_t2;
675 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
677 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
679 /* we trust the PM based calibration if possible */
680 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
683 /* Calculate the scaled math multiplication factor */
684 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
685 lapic_clockevent.shift);
686 lapic_clockevent.max_delta_ns =
687 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
688 lapic_clockevent.min_delta_ns =
689 clockevent_delta2ns(0xF, &lapic_clockevent);
691 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
693 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
694 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
695 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
699 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
701 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
702 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
705 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
707 calibration_result / (1000000 / HZ),
708 calibration_result % (1000000 / HZ));
711 * Do a sanity check on the APIC calibration result
713 if (calibration_result < (1000000 / HZ)) {
715 pr_warning("APIC frequency too slow, disabling apic timer\n");
719 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
722 * PM timer calibration failed or not turned on
723 * so lets try APIC timer based calibration
725 if (!pm_referenced) {
726 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
729 * Setup the apic timer manually
731 levt->event_handler = lapic_cal_handler;
732 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
733 lapic_cal_loops = -1;
735 /* Let the interrupts run */
738 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
741 /* Stop the lapic timer */
742 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
745 deltaj = lapic_cal_j2 - lapic_cal_j1;
746 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
748 /* Check, if the jiffies result is consistent */
749 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
750 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
752 levt->features |= CLOCK_EVT_FEAT_DUMMY;
756 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
757 pr_warning("APIC timer disabled due to verification failure\n");
765 * Setup the boot APIC
767 * Calibrate and verify the result.
769 void __init setup_boot_APIC_clock(void)
772 * The local apic timer can be disabled via the kernel
773 * commandline or from the CPU detection code. Register the lapic
774 * timer as a dummy clock event source on SMP systems, so the
775 * broadcast mechanism is used. On UP systems simply ignore it.
777 if (disable_apic_timer) {
778 pr_info("Disabling APIC timer\n");
779 /* No broadcast on UP ! */
780 if (num_possible_cpus() > 1) {
781 lapic_clockevent.mult = 1;
787 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
788 "calibrating APIC timer ...\n");
790 if (calibrate_APIC_clock()) {
791 /* No broadcast on UP ! */
792 if (num_possible_cpus() > 1)
798 * If nmi_watchdog is set to IO_APIC, we need the
799 * PIT/HPET going. Otherwise register lapic as a dummy
802 if (nmi_watchdog != NMI_IO_APIC)
803 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
805 pr_warning("APIC timer registered as dummy,"
806 " due to nmi_watchdog=%d!\n", nmi_watchdog);
808 /* Setup the lapic or request the broadcast */
812 void __cpuinit setup_secondary_APIC_clock(void)
818 * The guts of the apic timer interrupt
820 static void local_apic_timer_interrupt(void)
822 int cpu = smp_processor_id();
823 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
826 * Normally we should not be here till LAPIC has been initialized but
827 * in some cases like kdump, its possible that there is a pending LAPIC
828 * timer interrupt from previous kernel's context and is delivered in
829 * new kernel the moment interrupts are enabled.
831 * Interrupts are enabled early and LAPIC is setup much later, hence
832 * its possible that when we get here evt->event_handler is NULL.
833 * Check for event_handler being NULL and discard the interrupt as
836 if (!evt->event_handler) {
837 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
839 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
844 * the NMI deadlock-detector uses this.
846 inc_irq_stat(apic_timer_irqs);
848 evt->event_handler(evt);
852 * Local APIC timer interrupt. This is the most natural way for doing
853 * local interrupts, but local timer interrupts can be emulated by
854 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
856 * [ if a single-CPU system runs an SMP kernel then we call the local
857 * interrupt as well. Thus we cannot inline the local irq ... ]
859 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
861 struct pt_regs *old_regs = set_irq_regs(regs);
864 * NOTE! We'd better ACK the irq immediately,
865 * because timer handling can be slow.
869 * update_process_times() expects us to have done irq_enter().
870 * Besides, if we don't timer interrupts ignore the global
871 * interrupt lock, which is the WrongThing (tm) to do.
875 local_apic_timer_interrupt();
878 set_irq_regs(old_regs);
881 int setup_profiling_timer(unsigned int multiplier)
887 * Local APIC start and shutdown
891 * clear_local_APIC - shutdown the local APIC
893 * This is called, when a CPU is disabled and before rebooting, so the state of
894 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
895 * leftovers during boot.
897 void clear_local_APIC(void)
902 /* APIC hasn't been mapped yet */
903 if (!x2apic_mode && !apic_phys)
906 maxlvt = lapic_get_maxlvt();
908 * Masking an LVT entry can trigger a local APIC error
909 * if the vector is zero. Mask LVTERR first to prevent this.
912 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
913 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
916 * Careful: we have to set masks only first to deassert
917 * any level-triggered sources.
919 v = apic_read(APIC_LVTT);
920 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
921 v = apic_read(APIC_LVT0);
922 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
923 v = apic_read(APIC_LVT1);
924 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
926 v = apic_read(APIC_LVTPC);
927 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
930 /* lets not touch this if we didn't frob it */
931 #ifdef CONFIG_X86_THERMAL_VECTOR
933 v = apic_read(APIC_LVTTHMR);
934 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
937 #ifdef CONFIG_X86_MCE_INTEL
939 v = apic_read(APIC_LVTCMCI);
940 if (!(v & APIC_LVT_MASKED))
941 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
946 * Clean APIC state for other OSs:
948 apic_write(APIC_LVTT, APIC_LVT_MASKED);
949 apic_write(APIC_LVT0, APIC_LVT_MASKED);
950 apic_write(APIC_LVT1, APIC_LVT_MASKED);
952 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
954 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
956 /* Integrated APIC (!82489DX) ? */
957 if (lapic_is_integrated()) {
959 /* Clear ESR due to Pentium errata 3AP and 11AP */
960 apic_write(APIC_ESR, 0);
966 * disable_local_APIC - clear and disable the local APIC
968 void disable_local_APIC(void)
972 /* APIC hasn't been mapped yet */
973 if (!x2apic_mode && !apic_phys)
979 * Disable APIC (implies clearing of registers
982 value = apic_read(APIC_SPIV);
983 value &= ~APIC_SPIV_APIC_ENABLED;
984 apic_write(APIC_SPIV, value);
988 * When LAPIC was disabled by the BIOS and enabled by the kernel,
989 * restore the disabled state.
991 if (enabled_via_apicbase) {
994 rdmsr(MSR_IA32_APICBASE, l, h);
995 l &= ~MSR_IA32_APICBASE_ENABLE;
996 wrmsr(MSR_IA32_APICBASE, l, h);
1002 * If Linux enabled the LAPIC against the BIOS default disable it down before
1003 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1004 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1005 * for the case where Linux didn't enable the LAPIC.
1007 void lapic_shutdown(void)
1009 unsigned long flags;
1011 if (!cpu_has_apic && !apic_from_smp_config())
1014 local_irq_save(flags);
1016 #ifdef CONFIG_X86_32
1017 if (!enabled_via_apicbase)
1021 disable_local_APIC();
1024 local_irq_restore(flags);
1028 * This is to verify that we're looking at a real local APIC.
1029 * Check these against your board if the CPUs aren't getting
1030 * started for no apparent reason.
1032 int __init verify_local_APIC(void)
1034 unsigned int reg0, reg1;
1037 * The version register is read-only in a real APIC.
1039 reg0 = apic_read(APIC_LVR);
1040 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1041 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1042 reg1 = apic_read(APIC_LVR);
1043 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1046 * The two version reads above should print the same
1047 * numbers. If the second one is different, then we
1048 * poke at a non-APIC.
1054 * Check if the version looks reasonably.
1056 reg1 = GET_APIC_VERSION(reg0);
1057 if (reg1 == 0x00 || reg1 == 0xff)
1059 reg1 = lapic_get_maxlvt();
1060 if (reg1 < 0x02 || reg1 == 0xff)
1064 * The ID register is read/write in a real APIC.
1066 reg0 = apic_read(APIC_ID);
1067 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1068 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1069 reg1 = apic_read(APIC_ID);
1070 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1071 apic_write(APIC_ID, reg0);
1072 if (reg1 != (reg0 ^ apic->apic_id_mask))
1076 * The next two are just to see if we have sane values.
1077 * They're only really relevant if we're in Virtual Wire
1078 * compatibility mode, but most boxes are anymore.
1080 reg0 = apic_read(APIC_LVT0);
1081 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1082 reg1 = apic_read(APIC_LVT1);
1083 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1089 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1091 void __init sync_Arb_IDs(void)
1094 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1097 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1103 apic_wait_icr_idle();
1105 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1106 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1107 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1111 * An initial setup of the virtual wire mode.
1113 void __init init_bsp_APIC(void)
1118 * Don't do the setup now if we have a SMP BIOS as the
1119 * through-I/O-APIC virtual wire mode might be active.
1121 if (smp_found_config || !cpu_has_apic)
1125 * Do not trust the local APIC being empty at bootup.
1132 value = apic_read(APIC_SPIV);
1133 value &= ~APIC_VECTOR_MASK;
1134 value |= APIC_SPIV_APIC_ENABLED;
1136 #ifdef CONFIG_X86_32
1137 /* This bit is reserved on P4/Xeon and should be cleared */
1138 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1139 (boot_cpu_data.x86 == 15))
1140 value &= ~APIC_SPIV_FOCUS_DISABLED;
1143 value |= APIC_SPIV_FOCUS_DISABLED;
1144 value |= SPURIOUS_APIC_VECTOR;
1145 apic_write(APIC_SPIV, value);
1148 * Set up the virtual wire mode.
1150 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1151 value = APIC_DM_NMI;
1152 if (!lapic_is_integrated()) /* 82489DX */
1153 value |= APIC_LVT_LEVEL_TRIGGER;
1154 apic_write(APIC_LVT1, value);
1157 static void __cpuinit lapic_setup_esr(void)
1159 unsigned int oldvalue, value, maxlvt;
1161 if (!lapic_is_integrated()) {
1162 pr_info("No ESR for 82489DX.\n");
1166 if (apic->disable_esr) {
1168 * Something untraceable is creating bad interrupts on
1169 * secondary quads ... for the moment, just leave the
1170 * ESR disabled - we can't do anything useful with the
1171 * errors anyway - mbligh
1173 pr_info("Leaving ESR disabled.\n");
1177 maxlvt = lapic_get_maxlvt();
1178 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1179 apic_write(APIC_ESR, 0);
1180 oldvalue = apic_read(APIC_ESR);
1182 /* enables sending errors */
1183 value = ERROR_APIC_VECTOR;
1184 apic_write(APIC_LVTERR, value);
1187 * spec says clear errors after enabling vector.
1190 apic_write(APIC_ESR, 0);
1191 value = apic_read(APIC_ESR);
1192 if (value != oldvalue)
1193 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1194 "vector: 0x%08x after: 0x%08x\n",
1200 * setup_local_APIC - setup the local APIC
1202 void __cpuinit setup_local_APIC(void)
1204 unsigned int value, queued;
1205 int i, j, acked = 0;
1206 unsigned long long tsc = 0, ntsc;
1207 long long max_loops = cpu_khz;
1213 arch_disable_smp_support();
1217 #ifdef CONFIG_X86_32
1218 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1219 if (lapic_is_integrated() && apic->disable_esr) {
1220 apic_write(APIC_ESR, 0);
1221 apic_write(APIC_ESR, 0);
1222 apic_write(APIC_ESR, 0);
1223 apic_write(APIC_ESR, 0);
1226 perf_events_lapic_init();
1231 * Double-check whether this APIC is really registered.
1232 * This is meaningless in clustered apic mode, so we skip it.
1234 BUG_ON(!apic->apic_id_registered());
1237 * Intel recommends to set DFR, LDR and TPR before enabling
1238 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1239 * document number 292116). So here it goes...
1241 apic->init_apic_ldr();
1244 * Set Task Priority to 'accept all'. We never change this
1247 value = apic_read(APIC_TASKPRI);
1248 value &= ~APIC_TPRI_MASK;
1249 apic_write(APIC_TASKPRI, value);
1252 * After a crash, we no longer service the interrupts and a pending
1253 * interrupt from previous kernel might still have ISR bit set.
1255 * Most probably by now CPU has serviced that pending interrupt and
1256 * it might not have done the ack_APIC_irq() because it thought,
1257 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1258 * does not clear the ISR bit and cpu thinks it has already serivced
1259 * the interrupt. Hence a vector might get locked. It was noticed
1260 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1264 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1265 queued |= apic_read(APIC_IRR + i*0x10);
1267 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1268 value = apic_read(APIC_ISR + i*0x10);
1269 for (j = 31; j >= 0; j--) {
1270 if (value & (1<<j)) {
1277 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1283 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1286 } while (queued && max_loops > 0);
1287 WARN_ON(max_loops <= 0);
1290 * Now that we are all set up, enable the APIC
1292 value = apic_read(APIC_SPIV);
1293 value &= ~APIC_VECTOR_MASK;
1297 value |= APIC_SPIV_APIC_ENABLED;
1299 #ifdef CONFIG_X86_32
1301 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1302 * certain networking cards. If high frequency interrupts are
1303 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1304 * entry is masked/unmasked at a high rate as well then sooner or
1305 * later IOAPIC line gets 'stuck', no more interrupts are received
1306 * from the device. If focus CPU is disabled then the hang goes
1309 * [ This bug can be reproduced easily with a level-triggered
1310 * PCI Ne2000 networking cards and PII/PIII processors, dual
1314 * Actually disabling the focus CPU check just makes the hang less
1315 * frequent as it makes the interrupt distributon model be more
1316 * like LRU than MRU (the short-term load is more even across CPUs).
1317 * See also the comment in end_level_ioapic_irq(). --macro
1321 * - enable focus processor (bit==0)
1322 * - 64bit mode always use processor focus
1323 * so no need to set it
1325 value &= ~APIC_SPIV_FOCUS_DISABLED;
1329 * Set spurious IRQ vector
1331 value |= SPURIOUS_APIC_VECTOR;
1332 apic_write(APIC_SPIV, value);
1335 * Set up LVT0, LVT1:
1337 * set up through-local-APIC on the BP's LINT0. This is not
1338 * strictly necessary in pure symmetric-IO mode, but sometimes
1339 * we delegate interrupts to the 8259A.
1342 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1344 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1345 if (!smp_processor_id() && (pic_mode || !value)) {
1346 value = APIC_DM_EXTINT;
1347 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1348 smp_processor_id());
1350 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1351 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1352 smp_processor_id());
1354 apic_write(APIC_LVT0, value);
1357 * only the BP should see the LINT1 NMI signal, obviously.
1359 if (!smp_processor_id())
1360 value = APIC_DM_NMI;
1362 value = APIC_DM_NMI | APIC_LVT_MASKED;
1363 if (!lapic_is_integrated()) /* 82489DX */
1364 value |= APIC_LVT_LEVEL_TRIGGER;
1365 apic_write(APIC_LVT1, value);
1369 #ifdef CONFIG_X86_MCE_INTEL
1370 /* Recheck CMCI information after local APIC is up on CPU #0 */
1371 if (smp_processor_id() == 0)
1376 void __cpuinit end_local_APIC_setup(void)
1380 #ifdef CONFIG_X86_32
1383 /* Disable the local apic timer */
1384 value = apic_read(APIC_LVTT);
1385 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1386 apic_write(APIC_LVTT, value);
1390 setup_apic_nmi_watchdog(NULL);
1394 * Now that local APIC setup is completed for BP, configure the fault
1395 * handling for interrupt remapping.
1397 if (!smp_processor_id() && intr_remapping_enabled)
1398 enable_drhd_fault_handling();
1402 #ifdef CONFIG_X86_X2APIC
1403 void check_x2apic(void)
1405 if (x2apic_enabled()) {
1406 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1407 x2apic_preenabled = x2apic_mode = 1;
1411 void enable_x2apic(void)
1418 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1419 if (!(msr & X2APIC_ENABLE)) {
1420 printk_once(KERN_INFO "Enabling x2apic\n");
1421 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1424 #endif /* CONFIG_X86_X2APIC */
1426 int __init enable_IR(void)
1428 #ifdef CONFIG_INTR_REMAP
1429 if (!intr_remapping_supported()) {
1430 pr_debug("intr-remapping not supported\n");
1434 if (!x2apic_preenabled && skip_ioapic_setup) {
1435 pr_info("Skipped enabling intr-remap because of skipping "
1440 if (enable_intr_remapping(x2apic_supported()))
1443 pr_info("Enabled Interrupt-remapping\n");
1451 void __init enable_IR_x2apic(void)
1453 unsigned long flags;
1454 struct IO_APIC_route_entry **ioapic_entries = NULL;
1455 int ret, x2apic_enabled = 0;
1456 int dmar_table_init_ret;
1458 dmar_table_init_ret = dmar_table_init();
1459 if (dmar_table_init_ret && !x2apic_supported())
1462 ioapic_entries = alloc_ioapic_entries();
1463 if (!ioapic_entries) {
1464 pr_err("Allocate ioapic_entries failed\n");
1468 ret = save_IO_APIC_setup(ioapic_entries);
1470 pr_info("Saving IO-APIC state failed: %d\n", ret);
1474 local_irq_save(flags);
1475 legacy_pic->mask_all();
1476 mask_IO_APIC_setup(ioapic_entries);
1478 if (dmar_table_init_ret)
1484 /* IR is required if there is APIC ID > 255 even when running
1487 if (max_physical_apicid > 255 || !kvm_para_available())
1490 * without IR all CPUs can be addressed by IOAPIC/MSI
1491 * only in physical mode
1493 x2apic_force_phys();
1498 if (x2apic_supported() && !x2apic_mode) {
1501 pr_info("Enabled x2apic\n");
1505 if (!ret) /* IR enabling failed */
1506 restore_IO_APIC_setup(ioapic_entries);
1507 legacy_pic->restore_mask();
1508 local_irq_restore(flags);
1512 free_ioapic_entries(ioapic_entries);
1517 if (x2apic_preenabled)
1518 panic("x2apic: enabled by BIOS but kernel init failed.");
1519 else if (cpu_has_x2apic)
1520 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1523 #ifdef CONFIG_X86_64
1525 * Detect and enable local APICs on non-SMP boards.
1526 * Original code written by Keir Fraser.
1527 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1528 * not correctly set up (usually the APIC timer won't work etc.)
1530 static int __init detect_init_APIC(void)
1532 if (!cpu_has_apic) {
1533 pr_info("No local APIC present\n");
1537 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1542 * Detect and initialize APIC
1544 static int __init detect_init_APIC(void)
1548 /* Disabled by kernel option? */
1552 switch (boot_cpu_data.x86_vendor) {
1553 case X86_VENDOR_AMD:
1554 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1555 (boot_cpu_data.x86 >= 15))
1558 case X86_VENDOR_INTEL:
1559 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1560 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1567 if (!cpu_has_apic) {
1569 * Over-ride BIOS and try to enable the local APIC only if
1570 * "lapic" specified.
1572 if (!force_enable_local_apic) {
1573 pr_info("Local APIC disabled by BIOS -- "
1574 "you can enable it with \"lapic\"\n");
1578 * Some BIOSes disable the local APIC in the APIC_BASE
1579 * MSR. This can only be done in software for Intel P6 or later
1580 * and AMD K7 (Model > 1) or later.
1582 rdmsr(MSR_IA32_APICBASE, l, h);
1583 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1584 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1585 l &= ~MSR_IA32_APICBASE_BASE;
1586 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1587 wrmsr(MSR_IA32_APICBASE, l, h);
1588 enabled_via_apicbase = 1;
1592 * The APIC feature bit should now be enabled
1595 features = cpuid_edx(1);
1596 if (!(features & (1 << X86_FEATURE_APIC))) {
1597 pr_warning("Could not enable APIC!\n");
1600 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1601 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1603 /* The BIOS may have set up the APIC at some other address */
1604 rdmsr(MSR_IA32_APICBASE, l, h);
1605 if (l & MSR_IA32_APICBASE_ENABLE)
1606 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1608 pr_info("Found and enabled local APIC!\n");
1615 pr_info("No local APIC present or hardware disabled\n");
1620 #ifdef CONFIG_X86_64
1621 void __init early_init_lapic_mapping(void)
1624 * If no local APIC can be found then go out
1625 * : it means there is no mpatable and MADT
1627 if (!smp_found_config)
1630 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
1631 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1632 APIC_BASE, mp_lapic_addr);
1635 * Fetch the APIC ID of the BSP in case we have a
1636 * default configuration (or the MP table is broken).
1638 boot_cpu_physical_apicid = read_apic_id();
1643 * init_apic_mappings - initialize APIC mappings
1645 void __init init_apic_mappings(void)
1647 unsigned int new_apicid;
1650 boot_cpu_physical_apicid = read_apic_id();
1654 /* If no local APIC can be found return early */
1655 if (!smp_found_config && detect_init_APIC()) {
1656 /* lets NOP'ify apic operations */
1657 pr_info("APIC: disable apic facility\n");
1660 apic_phys = mp_lapic_addr;
1663 * acpi lapic path already maps that address in
1664 * acpi_register_lapic_address()
1666 if (!acpi_lapic && !smp_found_config)
1667 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1669 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1670 APIC_BASE, apic_phys);
1674 * Fetch the APIC ID of the BSP in case we have a
1675 * default configuration (or the MP table is broken).
1677 new_apicid = read_apic_id();
1678 if (boot_cpu_physical_apicid != new_apicid) {
1679 boot_cpu_physical_apicid = new_apicid;
1681 * yeah -- we lie about apic_version
1682 * in case if apic was disabled via boot option
1683 * but it's not a problem for SMP compiled kernel
1684 * since smp_sanity_check is prepared for such a case
1685 * and disable smp mode
1687 apic_version[new_apicid] =
1688 GET_APIC_VERSION(apic_read(APIC_LVR));
1693 * This initializes the IO-APIC and APIC hardware if this is
1696 int apic_version[MAX_APICS];
1698 int __init APIC_init_uniprocessor(void)
1701 pr_info("Apic disabled\n");
1704 #ifdef CONFIG_X86_64
1705 if (!cpu_has_apic) {
1707 pr_info("Apic disabled by BIOS\n");
1711 if (!smp_found_config && !cpu_has_apic)
1715 * Complain if the BIOS pretends there is one.
1717 if (!cpu_has_apic &&
1718 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1719 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1720 boot_cpu_physical_apicid);
1725 default_setup_apic_routing();
1727 verify_local_APIC();
1730 #ifdef CONFIG_X86_64
1731 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1734 * Hack: In case of kdump, after a crash, kernel might be booting
1735 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1736 * might be zero if read from MP tables. Get it from LAPIC.
1738 # ifdef CONFIG_CRASH_DUMP
1739 boot_cpu_physical_apicid = read_apic_id();
1742 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1745 #ifdef CONFIG_X86_IO_APIC
1747 * Now enable IO-APICs, actually call clear_IO_APIC
1748 * We need clear_IO_APIC before enabling error vector
1750 if (!skip_ioapic_setup && nr_ioapics)
1754 end_local_APIC_setup();
1756 #ifdef CONFIG_X86_IO_APIC
1757 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1761 localise_nmi_watchdog();
1764 localise_nmi_watchdog();
1767 x86_init.timers.setup_percpu_clockev();
1768 #ifdef CONFIG_X86_64
1769 check_nmi_watchdog();
1776 * Local APIC interrupts
1780 * This interrupt should _never_ happen with our APIC/SMP architecture
1782 void smp_spurious_interrupt(struct pt_regs *regs)
1789 * Check if this really is a spurious interrupt and ACK it
1790 * if it is a vectored one. Just in case...
1791 * Spurious interrupts should not be ACKed.
1793 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1794 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1797 inc_irq_stat(irq_spurious_count);
1799 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1800 pr_info("spurious APIC interrupt on CPU#%d, "
1801 "should never happen.\n", smp_processor_id());
1806 * This interrupt should never happen with our APIC/SMP architecture
1808 void smp_error_interrupt(struct pt_regs *regs)
1814 /* First tickle the hardware, only then report what went on. -- REW */
1815 v = apic_read(APIC_ESR);
1816 apic_write(APIC_ESR, 0);
1817 v1 = apic_read(APIC_ESR);
1819 atomic_inc(&irq_err_count);
1822 * Here is what the APIC error bits mean:
1824 * 1: Receive CS error
1825 * 2: Send accept error
1826 * 3: Receive accept error
1828 * 5: Send illegal vector
1829 * 6: Received illegal vector
1830 * 7: Illegal register address
1832 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1833 smp_processor_id(), v , v1);
1838 * connect_bsp_APIC - attach the APIC to the interrupt system
1840 void __init connect_bsp_APIC(void)
1842 #ifdef CONFIG_X86_32
1845 * Do not trust the local APIC being empty at bootup.
1849 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1850 * local APIC to INT and NMI lines.
1852 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1853 "enabling APIC mode.\n");
1857 if (apic->enable_apic_mode)
1858 apic->enable_apic_mode();
1862 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1863 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1865 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1868 void disconnect_bsp_APIC(int virt_wire_setup)
1872 #ifdef CONFIG_X86_32
1875 * Put the board back into PIC mode (has an effect only on
1876 * certain older boards). Note that APIC interrupts, including
1877 * IPIs, won't work beyond this point! The only exception are
1880 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1881 "entering PIC mode.\n");
1887 /* Go back to Virtual Wire compatibility mode */
1889 /* For the spurious interrupt use vector F, and enable it */
1890 value = apic_read(APIC_SPIV);
1891 value &= ~APIC_VECTOR_MASK;
1892 value |= APIC_SPIV_APIC_ENABLED;
1894 apic_write(APIC_SPIV, value);
1896 if (!virt_wire_setup) {
1898 * For LVT0 make it edge triggered, active high,
1899 * external and enabled
1901 value = apic_read(APIC_LVT0);
1902 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1903 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1904 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1905 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1906 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1907 apic_write(APIC_LVT0, value);
1910 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1914 * For LVT1 make it edge triggered, active high,
1917 value = apic_read(APIC_LVT1);
1918 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1919 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1920 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1921 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1922 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1923 apic_write(APIC_LVT1, value);
1926 void __cpuinit generic_processor_info(int apicid, int version)
1933 if (version == 0x0) {
1934 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1935 "fixing up to 0x10. (tell your hw vendor)\n",
1939 apic_version[apicid] = version;
1941 if (num_processors >= nr_cpu_ids) {
1942 int max = nr_cpu_ids;
1943 int thiscpu = max + disabled_cpus;
1946 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1947 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1954 cpu = cpumask_next_zero(-1, cpu_present_mask);
1956 if (version != apic_version[boot_cpu_physical_apicid])
1958 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1959 apic_version[boot_cpu_physical_apicid], cpu, version);
1961 physid_set(apicid, phys_cpu_present_map);
1962 if (apicid == boot_cpu_physical_apicid) {
1964 * x86_bios_cpu_apicid is required to have processors listed
1965 * in same order as logical cpu numbers. Hence the first
1966 * entry is BSP, and so on.
1970 if (apicid > max_physical_apicid)
1971 max_physical_apicid = apicid;
1973 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1974 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1975 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1978 set_cpu_possible(cpu, true);
1979 set_cpu_present(cpu, true);
1982 int hard_smp_processor_id(void)
1984 return read_apic_id();
1987 void default_init_apic_ldr(void)
1991 apic_write(APIC_DFR, APIC_DFR_VALUE);
1992 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1993 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1994 apic_write(APIC_LDR, val);
1997 #ifdef CONFIG_X86_32
1998 int default_apicid_to_node(int logical_apicid)
2001 return apicid_2_node[hard_smp_processor_id()];
2015 * 'active' is true if the local APIC was enabled by us and
2016 * not the BIOS; this signifies that we are also responsible
2017 * for disabling it before entering apm/acpi suspend
2020 /* r/w apic fields */
2021 unsigned int apic_id;
2022 unsigned int apic_taskpri;
2023 unsigned int apic_ldr;
2024 unsigned int apic_dfr;
2025 unsigned int apic_spiv;
2026 unsigned int apic_lvtt;
2027 unsigned int apic_lvtpc;
2028 unsigned int apic_lvt0;
2029 unsigned int apic_lvt1;
2030 unsigned int apic_lvterr;
2031 unsigned int apic_tmict;
2032 unsigned int apic_tdcr;
2033 unsigned int apic_thmr;
2036 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
2038 unsigned long flags;
2041 if (!apic_pm_state.active)
2044 maxlvt = lapic_get_maxlvt();
2046 apic_pm_state.apic_id = apic_read(APIC_ID);
2047 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2048 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2049 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2050 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2051 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2053 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2054 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2055 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2056 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2057 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2058 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2059 #ifdef CONFIG_X86_THERMAL_VECTOR
2061 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2064 local_irq_save(flags);
2065 disable_local_APIC();
2067 if (intr_remapping_enabled)
2068 disable_intr_remapping();
2070 local_irq_restore(flags);
2074 static int lapic_resume(struct sys_device *dev)
2077 unsigned long flags;
2080 struct IO_APIC_route_entry **ioapic_entries = NULL;
2082 if (!apic_pm_state.active)
2085 local_irq_save(flags);
2086 if (intr_remapping_enabled) {
2087 ioapic_entries = alloc_ioapic_entries();
2088 if (!ioapic_entries) {
2089 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2094 ret = save_IO_APIC_setup(ioapic_entries);
2096 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2097 free_ioapic_entries(ioapic_entries);
2101 mask_IO_APIC_setup(ioapic_entries);
2102 legacy_pic->mask_all();
2109 * Make sure the APICBASE points to the right address
2111 * FIXME! This will be wrong if we ever support suspend on
2112 * SMP! We'll need to do this as part of the CPU restore!
2114 rdmsr(MSR_IA32_APICBASE, l, h);
2115 l &= ~MSR_IA32_APICBASE_BASE;
2116 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2117 wrmsr(MSR_IA32_APICBASE, l, h);
2120 maxlvt = lapic_get_maxlvt();
2121 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2122 apic_write(APIC_ID, apic_pm_state.apic_id);
2123 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2124 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2125 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2126 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2127 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2128 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2129 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2131 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2134 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2135 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2136 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2137 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2138 apic_write(APIC_ESR, 0);
2139 apic_read(APIC_ESR);
2140 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2141 apic_write(APIC_ESR, 0);
2142 apic_read(APIC_ESR);
2144 if (intr_remapping_enabled) {
2145 reenable_intr_remapping(x2apic_mode);
2146 legacy_pic->restore_mask();
2147 restore_IO_APIC_setup(ioapic_entries);
2148 free_ioapic_entries(ioapic_entries);
2151 local_irq_restore(flags);
2157 * This device has no shutdown method - fully functioning local APICs
2158 * are needed on every CPU up until machine_halt/restart/poweroff.
2161 static struct sysdev_class lapic_sysclass = {
2163 .resume = lapic_resume,
2164 .suspend = lapic_suspend,
2167 static struct sys_device device_lapic = {
2169 .cls = &lapic_sysclass,
2172 static void __cpuinit apic_pm_activate(void)
2174 apic_pm_state.active = 1;
2177 static int __init init_lapic_sysfs(void)
2183 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2185 error = sysdev_class_register(&lapic_sysclass);
2187 error = sysdev_register(&device_lapic);
2191 /* local apic needs to resume before other devices access its registers. */
2192 core_initcall(init_lapic_sysfs);
2194 #else /* CONFIG_PM */
2196 static void apic_pm_activate(void) { }
2198 #endif /* CONFIG_PM */
2200 #ifdef CONFIG_X86_64
2202 static int __cpuinit apic_cluster_num(void)
2204 int i, clusters, zeros;
2206 u16 *bios_cpu_apicid;
2207 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2209 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2210 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2212 for (i = 0; i < nr_cpu_ids; i++) {
2213 /* are we being called early in kernel startup? */
2214 if (bios_cpu_apicid) {
2215 id = bios_cpu_apicid[i];
2216 } else if (i < nr_cpu_ids) {
2218 id = per_cpu(x86_bios_cpu_apicid, i);
2224 if (id != BAD_APICID)
2225 __set_bit(APIC_CLUSTERID(id), clustermap);
2228 /* Problem: Partially populated chassis may not have CPUs in some of
2229 * the APIC clusters they have been allocated. Only present CPUs have
2230 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2231 * Since clusters are allocated sequentially, count zeros only if
2232 * they are bounded by ones.
2236 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2237 if (test_bit(i, clustermap)) {
2238 clusters += 1 + zeros;
2247 static int __cpuinitdata multi_checked;
2248 static int __cpuinitdata multi;
2250 static int __cpuinit set_multi(const struct dmi_system_id *d)
2254 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2259 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2261 .callback = set_multi,
2262 .ident = "IBM System Summit2",
2264 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2265 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2271 static void __cpuinit dmi_check_multi(void)
2276 dmi_check_system(multi_dmi_table);
2281 * apic_is_clustered_box() -- Check if we can expect good TSC
2283 * Thus far, the major user of this is IBM's Summit2 series:
2284 * Clustered boxes may have unsynced TSC problems if they are
2286 * Use DMI to check them
2288 __cpuinit int apic_is_clustered_box(void)
2298 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2299 * not guaranteed to be synced between boards
2301 if (apic_cluster_num() > 1)
2309 * APIC command line parameters
2311 static int __init setup_disableapic(char *arg)
2314 setup_clear_cpu_cap(X86_FEATURE_APIC);
2317 early_param("disableapic", setup_disableapic);
2319 /* same as disableapic, for compatibility */
2320 static int __init setup_nolapic(char *arg)
2322 return setup_disableapic(arg);
2324 early_param("nolapic", setup_nolapic);
2326 static int __init parse_lapic_timer_c2_ok(char *arg)
2328 local_apic_timer_c2_ok = 1;
2331 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2333 static int __init parse_disable_apic_timer(char *arg)
2335 disable_apic_timer = 1;
2338 early_param("noapictimer", parse_disable_apic_timer);
2340 static int __init parse_nolapic_timer(char *arg)
2342 disable_apic_timer = 1;
2345 early_param("nolapic_timer", parse_nolapic_timer);
2347 static int __init apic_set_verbosity(char *arg)
2350 #ifdef CONFIG_X86_64
2351 skip_ioapic_setup = 0;
2357 if (strcmp("debug", arg) == 0)
2358 apic_verbosity = APIC_DEBUG;
2359 else if (strcmp("verbose", arg) == 0)
2360 apic_verbosity = APIC_VERBOSE;
2362 pr_warning("APIC Verbosity level %s not recognised"
2363 " use apic=verbose or apic=debug\n", arg);
2369 early_param("apic", apic_set_verbosity);
2371 static int __init lapic_insert_resource(void)
2376 /* Put local APIC into the resource map. */
2377 lapic_resource.start = apic_phys;
2378 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2379 insert_resource(&iomem_resource, &lapic_resource);
2385 * need call insert after e820_reserve_resources()
2386 * that is using request_resource
2388 late_initcall(lapic_insert_resource);